DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15, 18-22 have been considered but are not found persuasive.
Applicant argues on page 8-9 of the remarks that the shielding wall of Kim is not described as a unitary continuous ring-shaped leadframe with a leadframe opening through the top and bottom leadframe surfaces disposed in a central portion. Applicant further argues that Kim only teaches a continuous leadframe, which is not equivalent to a unitary continuous ring-shaped leadframe.
Examiner respectfully disagrees. the claimed “unitary continuous ring-shaped leadframe” is merely a name given a particular element, which in this application is element 130 of fig. 1a,b. The only positively recited structural limitation is that the unitary continuous ring-shaped leadframe is provided with a leadframe opening. Further, since the specification as filed fails to provide an explicit definition on how to interpret “unitary,” Examiner takes the position that any continuous leadframe would also be unitary as being formed from a single structure. Therefore, since element 130 of Kim is continuous and made from a single element, this element would meet the claimed structure of “unitary continuous ring-shaped leadframe.”
Other arguments provided are based on the same logic and therefore the same reply as above would also apply.
The rejection is being maintained and the Office Action has been updated to include the newly added limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-15, and 18-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PGPub 2019/0051612; hereinafter “Kim”).
Re claim 1: Kim teaches (e.g. fig. 1A, 1B) a semiconductor package comprising: a flip chip (140A) having opposing active (bottom surface of 140A; hereinafter “AS”) and inactive (top surface of 140A; hereinafter “IS”) chip surfaces, wherein the active chip surface (AS) includes chip pads (160); a unitary continuous ring-shaped leadframe (shielding wall 130 may be spaced from first semiconductor chip 140A and (continuously) extend along an outer perimeter of the chip portion 112 to surround the first semiconductor chip 140A; e.g. paragraph 25) having top (top surface of 130 and 120; hereinafter “TS”) and bottom (bottom surface of 130; hereinafter “BS”) leadframe surfaces, wherein the bottom leadframe surface (BS) includes leadframe pads (bottom surface of BS is a pad; hereinafter “LFP”), the bottom leadframe surface (BS) is in thermal communication with the top leadframe surface (TS), a leadframe opening (chip portion 112 of heat spreading layer 110 delineated by 130; e.g. paragraph 21 and fig. 1A; hereinafter “LFO”) through the top and bottom leadframe surfaces (TS, BS) disposed in a central portion (112) of the continuous ring-shaped leadframe (130) wherein the flip chip (140A) is disposed within the leadframe opening (LFO), bottom chip pad surfaces (bottom surface of 160) of the chip pads (160) on the active chip surface (AS) are coplanar with the bottom leadframe surface (BS) with the leadframe pads (LFP), and a gap (gap between 140A and 130; hereinafter “G”) exists between sides of the flip chip (140A) and the unitary continuous ring-shaped leadframe (130), the gap (G) physically separates the flip chip (140A) from the unitary continuous ring-shaped leadframe (130); an encapsulant (170) having opposing top (top surface of 170; hereinafter “TES”) and bottom (bottom surface of 170; hereinafter “BES”) encapsulant surfaces, the encapsulant (170) encapsulates the unitary continuous ring-shaped leadframe (130), the flip chip (140A) and the gap (G) between the flip chip (140A) and the unitary continuous ring-shaped leadframe(130), wherein the bottom encapsulant surface (BES) exposes the leadframe pads (LFP) and chip pads (160); first package contacts (182 connected to LFP; hereinafter “1PC”) coupled to the leadframe pads (LFP); second package contacts (182 connected to 160; hereinafter “2PC”) coupled to the chip pads (160); and wherein the first and second package contacts (1PC, 2PC) protrude from the bottom encapsulant surface (BES) and form package contacts of the semiconductor package (100), the first package contacts (1PC) connected to the leadframe pads (LFP) enables the leadframe (130) to serve as a leadframe heat dissipator.
Re claim 2: Kim teaches the semiconductor package of claim 1, wherein the top encapsulant surface (TES) is disposed below the top leadframe surface (TS), the top leadframe surface (TS) and the inactive chip surface (IS) are about coplanar.
Re claim 4: Kim teaches the semiconductor package of claim 1, wherein the top leadframe surface (TS) and the inactive chip surface (IS) are about coplanar.
Re claim 5: Kim teaches the semiconductor package of claim 1, wherein the top leadframe surface (TS) and the inactive chip surface (IS) are exposed by the top encapsulant surface (TES).
Re claim 6: Kim teaches the semiconductor package of claim 1, wherein the top encapsulant surface (TES), the top leadframe surface (TS) and the inactive chip surface (IS) are coplanar.
Re claim 7: Kim teaches the semiconductor package of claim 5 comprises a heat dissipation structure (110), the heat dissipation structure (110) is thermally connected to the inactive chip surface (IS) and top leadframe surface (TS).
Re claim 8: Kim teaches the semiconductor package of claim 7, wherein the heat dissipation structure (110) comprises a bonded heat dissipation structure.
Re claim 9: Kim teaches the semiconductor package of claim 8 comprises a thermal conductive adhesive (150), the thermal conductive adhesive (150) bonds the heat dissipation structure (110 can be stacked layers for proper thermal interface; e.g. paragraph 20) to the top leadframe surface (TLS), the top encapsulant surface (TES) and inactive chip surface (IS) with a thermal conductive adhesive (150.
Re claim 10: Salmon teaches the semiconductor package of claim 7, wherein the heat dissipation structure (110) comprises a deposited heat dissipation structure (110 is deposited).
Re claim 11: Kim teaches the semiconductor package of claim 1, wherein the first package contacts (1PC) are not electrically connected to the flip chip (140A).
Re claim 12: Kim teaches the semiconductor package of claim 1 wherein the unitary continuous ring-shaped leadframe (130) comprises: an upper leadframe portion (upper portion of 130; hereinafter “ULP”) which includes the top leadframe surface (TS); and a lower leadframe (lower portion of 130) which includes the leadframe pads (LFP).
Re claim 13: Kim teaches the semiconductor package of claim 12 wherein: side encapsulant surfaces (side surfaces of 170; hereinafter “SES”) of the encapsulant (170) are aligned with side leadframe surfaces (side surfaces of 130; hereinafter “SLS”) of the upper leadframe portion (ULP); and side encapsulant surfaces (SES) cover the leadframe pad sides (sides of LFP) of the leadframe pads (LFP) of the lower leadframe portion (lower portion of 130).
Re claim 14: Kim teaches the semiconductor package of claim 1 wherein the unitary continuous ring-shaped leadframe (130) comprises a rectangular shape (130 is rectangular as shown in fig. 1A).
Re claim 15: Kim teaches the semiconductor package of claim 14 wherein: the unitary continuous ring-shaped leadframe (130) comprises a unitary continuous rectangular-shaped leadframe (130 is continuous and rectangular as shown in fig. 1A).
Re claim 18: Kim teaches (e.g. fig. 1A, 1B) a semiconductor package comprising: a flip chip (140A) having opposing active (bottom surface of 140A; hereinafter “AS”) and inactive (top surface of 140A; hereinafter “IS”) chip surfaces, wherein the active chip surface (AS) includes chip pads (160); a unitary continuous ring-shaped leadframe (shielding wall 130 may be spaced from first semiconductor chip 140A and (continuously) extend along an outer perimeter of the chip portion 112 to surround the first semiconductor chip 140A; e.g. paragraph 25), the unitary continuous ring- shaped leadframe (130) includes top (top surface of 130 and 120; hereinafter “TS”) and bottom (bottom surface of 130; hereinafter “BS”) leadframe surfaces, wherein the bottom leadframe surface (BS) includes leadframe pads (bottom surface of BS is a pad; hereinafter “LFP”), the bottom leadframe surface (BS) is in thermal communication with the top leadframe surface (TS), a leadframe opening (chip portion 112 of heat spreading layer 110 delineated by 130; e.g. paragraph 21 and fig. 1A; hereinafter “LFO”) through the top and bottom leadframe surfaces (TS, BS) disposed in a central portion (112) of the unitary continuous ring- shaped leadframe (130), and the flip chip (140A) is disposed in the central portion (112) within the leadframe opening (LFO) of the unitary continuous ring-shaped leadframe (130) wherein a gap (gap between 140A and 130; hereinafter “G”) exists between sides of the flip chip (140A) and the unitary continuous ring-shaped leadframe (130), the gap (G) physically separates the flip chip (140A) from the unitary continuous ring-shaped leadframe (130); an encapsulant (170) having opposing top (top surface of 170; hereinafter “TES”) and bottom (bottom surface of 170; hereinafter “BES”) encapsulant surfaces, the encapsulant (170) encapsulates the unitary continuous ring-shaped leadframe (130), the flip chip (140A), and the gap (G) between the flip chip (140A) and the unitary continuous ring-shaped leadframe (130), wherein the bottom encapsulant surface (BES) exposes the leadframe pads (LFP) and chip pads (160); a heat dissipation structure (110), the heat dissipation structure (110) is disposed on the top encapsulant surface (TES); first package contacts (182 connected to LFP; hereinafter “1PC”) coupled to the leadframe pads (LFP), the first package contacts (1PC) connected to the leadframe pads (LFP) are thermally connected to the heat dissipation structure (110) and further serve as a leadframe heat dissipator; and second package contacts (182 connected to 160; hereinafter “2PC”) coupled to the chip pads (160).
Re claim 19: Kim teaches the semiconductor package of claim 18, wherein the first and second package contacts (1PC, 2PC) protrude from the bottom encapsulant surface (BS) and form package contacts of the semiconductor package (100).
Re claim 20: Kim teaches the semiconductor package of claim 18, wherein the unitary continuous ring-shaped leadframe (130) comprises: an upper leadframe portion (top portion of 130; hereinafter “ULP”) which includes the top leadframe surface (TS); and a lower leadframe portions (lower portion of 130; hereinafter “LLP”) which includes the leadframe pads (LFP).
Re claim 21: Kim teaches the semiconductor package of claim 18, wherein the top encapsulant surface (TES), the top leadframe surface (TS) and the inactive chip surface (IS) are coplanar.
Re claim 22: Kim teaches the semiconductor package of claim 21, wherein the heat dissipation structure (110) comprises a thermal conductive adhesive (thermal and electrically conductive adhesive 150; e.g. paragraph 20), the thermal conductive adhesive bonds the heat dissipation structure (110) to the top lead frame surface (TS), the top encapsulant surface (TES) and inactive chip surface (IS) with a thermal conductive adhesive (150).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 2, and further in view of Lin et al. (US PGPub 2016/0197033; hereinafter “Lin2”).
Re claim 3: Kim teaches the semiconductor package of claim 2, the top encapsulant surface (7 of Gomez/20 of Lui), the top leadframe surface (TLS) and the inactive chip surface (14 of Lui).
Lin2 teaches (Fig. 4A ) top encapsulant surface (top surface of 441) is disposed below the top leadframe surface (41) and the inactive chip surface (52) by less than about 5 um (441 is disposed below the surface of chip 52 and leadframe 41).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results to have the upper surface of the encapsulant less than five microns below the upper surface of the upper surface of the leadframe and inactive surface of the chip as taught by Lin2 in the device of Kim in order to have the predictable result of allowing space for thermal expansion of the encapsulant and prevent excess stress within the package from arising. The dimensional aspect would have been obvious to optimize through routine experimentation since the coefficient of the encapsulation is a result effective variable and the location of the upper surface of the encapsulant would be known to be optimized for minimal stress within the package.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898