DETAILED ACTION
This Office Action is in response to the request for continued examination filed on 10/20/2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/20/2025 has been entered. Claims 1-8 and 11-21 are pending. Claims 9-10 are canceled. Claims 6 and 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/25/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 11 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 2012/0161121) and in further view of Lee (US 2014/0374746).
With respect to claim 1, Yamazaki discloses (Fig 4b) most aspects of the present invention including a semiconductor device comprising:
a substrate (201);
a buried insulating layer (202) on the substrate;
a channel layer (205,207) and a source/drain layer (209a,209b) on the buried insulating layer;
a gate electrode pattern (213) on the channel layer,
a gate spacer (215a,215b) on a side surface of the gate electrode pattern
wherein the channel layer includes: a main channel layer (205) vertically overlapping the gate electrode pattern; and a side channel layer (207a, 207b) formed between the main channel layer and a source/drain layer
wherein the channel layer and the source/drain layer include an oxide semiconducting material (par 68,160)
wherein an upper surface of the side channel layer us entirely covered by the gate spacer
However, Yamazaki does not disclose an oxygen concentration of the side channel layer is higher than an oxygen concentration of the source/drain layer.
On the other hand, and in the same field endeavor, Lee teaches (Fig 5) a semiconductor device comprising a channel layer (130C) and a source/drain layer (130D/130S) on the substrate, wherein an oxygen concentration of the channel layer (including a portion closest to the source/drain layer i.e. side channel layer) is higher than an oxygen concentration of the source/drain layer (abstract & par 13). Lee teaches doing so to improve the electrical stability of the device, and thus reducing an oxygen vacancy ratio of the channel area (par 13).
As a result, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the same outcomes as describe in the instant invention, i.e. an oxygen concentration of the side channel layer is higher than an oxygen concentration of the source/drain layer, in the device of Yamazaki, due to an oxygen ion bombardment method to implant oxygen into the channel area, thus reducing an oxygen vacancy ratio of the channel area and increasing an oxygen concentration in the channel area, as disclosed by Lee, and implementing the channel layer and the source/drain layer for their conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to claim 3, Yamazaki discloses (Fig 4b) wherein a hydrogen concentration in the source/drain layer is higher than a hydrogen concentration in the channel layer (Yamazaki discloses par 142-148; dopant 150 which is hydrogen is added to the oxide semiconductor film; par 29 the concentration of the dopant in the source/drain layer is 5×1019 atoms/cm3 to 1×1022 atoms/cm3; par 72 the concentration of the dopant in the channel layer is lower than or equal to 1×1018 atoms/cm3).
With respect to claim 5, Yamazaki discloses (Fig 4b) wherein a hydrogen concentration of the main channel layer is lower than a hydrogen concentration in the side channel layer. Dopant 150 is hydrogen is added to the oxide semiconductor film; (the concentration of the dopant of the side channel layer 5×1018 atoms/cm3 to 5×1019 atoms/cm3 (par 29); the concentration of the dopant in the channel layer is lower than or equal to 1×1018 atoms/cm3 (par 72))
With respect to claim 11, Yamazaki discloses (Fig 4b) most aspects of the present invention including a semiconductor device comprising:
a buried insulating layer (202) on a substrate (201)
a channel layer (205,207) and a source/drain layer (209a,209b) on the buried insulating layer;
a gate electrode pattern (213) on the channel layer,
a gate spacer (215a,215b) on a side surface of the gate electrode pattern
wherein the channel layer and the source/drain layer include an oxide semiconducting material (par 68,160)
wherein the channel layer includes: a main channel layer (205) vertically overlapping the gate electrode pattern; and a side channel layer (207a, 207b) formed between the main channel layer and a source/drain layer
wherein an upper surface of the side channel layer us entirely covered by the gate spacer
However, Yamazaki does not disclose wherein an oxygen concentration of the channel layer is higher than an oxygen concentration of the source/drain layer and an oxygen concentration of the side channel layer is higher than an oxygen concentration of the source/drain layer.
On the other hand, and in the same field endeavor, Lee teaches (Fig 5) a semiconductor device comprising a channel layer (130C) and a source/drain layer (130D/130S) on the substrate, wherein an oxygen concentration of the channel layer (including a portion closest to the source/drain layer i.e. side channel layer) is higher than an oxygen concentration of the source/drain layer (abstract & par 13). Lee teaches doing so to improve the electrical stability of the device, and thus reducing an oxygen vacancy ratio of the channel area (par 13).
As a result, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the same outcomes as describe in the instant invention, i.e. an oxygen concentration of the channel layer is higher than an oxygen concentration of the source/drain layer and an oxygen concentration of the side channel layer is higher than an oxygen concentration of the source/drain layer, in the device of Yamazaki, due to an oxygen ion bombardment method to implant oxygen into the channel area, thus reducing an oxygen vacancy ratio of the channel area and increasing an oxygen concentration in the channel area, as disclosed by Lee, and implementing the channel layer and the source/drain layer for their conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to claim 21, Initially, Yamazaki does not disclose wherein an oxygen vacancy concentration of the source/drain layer and an oxygen vacancy concentration of the side channel layer is higher than an oxygen vacancy concentration of the main channel layer. However, Yamazaki discloses the channel layer and the source/drain layer are an oxide semiconductor film that is a metal oxide containing two or more elements selected from In, Ga, Sn, and Zn (par 68), similar to the instant invention. Additionally, Yamazaki discloses par 142-148; dopant 150 which is hydrogen is implanted into the oxide semiconductor film, with the main channel layer being more protected from the implantation than the side channel layer and the source/drain layer, thus allowing more hydrogen to be implanted into the side channel layer and the source/drain layer the main channel layer. This is done because diffusion of hydrogen to the main channel layer might cause deterioration of transistor characteristics (par 144). Lastly, the transistor 300 includes the oxide semiconductor film 303 including the first region (main channel layer) 305 (denoted by OS1), the pair of second regions (side channel layer) 307a/307b (denoted by OS2), and the pair of third regions 309a/309b (source/drain layer) (denoted by OS3); and hydrogen or one or more elements selected from rare gas elements are added as a dopant to OS2 and OS3 so as to function as a donor or cause an oxygen vacancy (see par 213-215).
As a result, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the same outcomes as describe in the instant invention, i.e. an oxygen vacancy concentration of the source/drain layer and an oxygen vacancy concentration of the side channel layer is higher than an oxygen vacancy concentration of the main channel layer, due to dopant 150 which is hydrogen being implanted into the oxide semiconductor film, with the channel layer being more protected from the from the implantation than source/drain layer, thus allowing more hydrogen to be implanted into the side channel layer and the source/drain layer than the main channel layer, as disclosed by Yamazaki, and implementing the channel layer and the source/drain layer for their conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Lee and Jeong (US 2017/0287986).
With respect to claim 2, Yamazaki in view of Lee discloses most aspects of the present invention. Yamazaki discloses (Fig 4b) wherein the buried insulating layer is a multi-stack layer comprising any of insulating films selected from oxide insulating films such as a silicon oxide film, a gallium oxide film, and an aluminum oxide film; nitride insulating films such as a silicon nitride film and an aluminum nitride film; a silicon oxynitride film; an aluminum oxynitride film; and a silicon nitride oxide film (par 83). However, the combination of references are silent of a middle-buried insulating layer including silicon carbon oxide.
On the other hand, and in the same field endeavor, Jeong teaches (Fig. 2a) a semiconductor device comprising a buried insulating layer (110) on the substrate (100), wherein the buried insulating layer is a multi-layer structure including at least two of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbide film, a silicon carbon nitride film, etc and teaches that those materials are suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a gate structure from an underlying bulk substrate or interconnect layer (par 56).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a lower buried insulating layer including silicon oxide; a middle buried insulating layer including silicon carbon oxide; and an upper buried insulating layer including silicon nitride in the structure of Yamazaki in view of Lee, because dielectric material of a multi-layer structure including at least two of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbide film, a silicon carbon nitride film, etc are materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a gate structure from an underlying bulk substrate or interconnect layer, as suggested by Jeong, and selecting a known material based on its suitability for its intended use would have been obvious to the skilled artisan. See, Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Lee and Bae (KR 20110027470).
With respect to claim 4, Yamazaki in view of Lee discloses most aspects of the present invention. Yamazaki discloses (Fig 4b) the side channel layer (207a, 207b) vertically overlapping the gate spacer. However, the combination of references do not show wherein an oxygen concentration of the main channel layer is higher than an oxygen concentration in the side channel layer.
On the other hand, and in the same field endeavor, Bae teaches (Fig 4e,5-6b) a semiconductor device comprising a channel layer (124c,124’) and a source/drain layer (124’’), wherein the channel layer includes: a main channel layer (124c) and a side channel layer (124’) formed between the main channel layer and the source/drain layer, the channel layer and the source/drain layer include an oxide semiconducting material, wherein an oxygen concentration of the channel layer is higher than an oxygen concentration of the source/drain layer and further wherein an oxygen concentration in the main channel layer is higher than an oxygen concentration in the side channel layer (Bae teaches resistance can be controlled by forming sidewalls using an insulating film containing oxygen, and the resistance of the active layer can be varied according to the region by using a change in the oxygen concentration in the oxide semiconductor).
Bae teaches it is possible to prevent problems caused by the ion implantation process at the source and additionally the use of the coplanar structure protects the channel region of the active layer from an external light source in the application of a reflective mode such as an electrophoretic display device, thereby reducing the light leakage current and improving driving characteristics.
Therefore, it would have been obvious at the time of the invention to one having ordinary skill in the art, or before the effective filing date of the invention to have the same outcomes as describe in the instant invention, i.e. an oxygen concentration of the main channel layer is higher than an oxygen concentration in the side channel layer, in the device of Yamazaki and Lee, to prevent problems caused by the ion implantation process at the source and additionally the use of the coplanar structure protects the channel region of the active layer from an external light source in the application of a reflective mode such as an electrophoretic display device, thereby reducing the light leakage current and improving driving characteristics, as disclosed by Bae, and implementing the channel layer and the source/drain layer for their conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki in view of Lee and Li (US 2011/0215409).
With respect to claim 7, Yamazaki in view of Lee discloses most aspects of the present invention. However, the combination of references do not show wherein the gate electrode pattern includes: an interface insulating layer on the channel layer; a gate insulating layer on the interface insulating layer; a gate barrier layer on the gate insulating layer; and a gate electrode on the gate barrier layer.
On the other hand, and in the same field endeavor, Li teaches (Fig. 7) a semiconductor device comprising a channel layer (SOI layer 14) on a substrate (12), a gate electrode pattern on the channel layer, wherein the gate electrode pattern includes: an interface insulating layer (8) on the channel layer; a gate insulating layer (9) on the interface insulating layer; a gate barrier layer (26) on the gate insulating layer; and a gate electrode (29) on the gate barrier layer.
Therefore one of ordinary skill in the art would have known that a gate electrode pattern includes: an interface insulating layer on the channel layer; a gate insulating layer on the interface insulating layer; a gate barrier layer on the gate insulating layer; and a gate electrode on the gate barrier layer, is typically used in the semiconductor package art to provide a gate structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device, e.g., memory device, through electrical or magnetic fields (par 68).
Therefore, it would have been obvious at the time of the invention to one having ordinary skill in the art, or before the effective filing date of the invention to incorporate wherein the gate electrode pattern includes: an interface insulating layer on the channel layer; a gate insulating layer on the interface insulating layer; a gate barrier layer on the gate insulating layer; and a gate electrode on the gate barrier layer in the device of Yamazaki in view of Lee, as suggested by Li, and implementing the gate electrode pattern for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to claim 8, Li teaches (Fig. 7) wherein the gate electrode pattern further includes a work function adjusting layer (25) between the gate barrier layer and the gate electrode.
Allowable Subject Matter
Regarding Claim 12, the prior art of record fails to disclose or suggest a method of forming a semiconductor device, the method comprising forming a source/drain layer by implanting hydrogen ions into the first oxide semiconducting layer; forming a second oxide semiconducting layer on the buried insulating layer exposed in the gate groove; forming a channel layer by implanting oxygen ions into the second oxide semiconducting layer.
Examiner’s comments: the closest prior art references (Yamazaki US 2012/0161121; Gu US 2021/0336064; Morosawa US 2011/0240998; Liu US 2020/0044039; Song US 2020/0227519) are all directed in part to a method of forming a semiconductor device comprising forming a channel layer and the source/drain layer on the buried insulating layer, the channel layer and the source/drain layer including an oxide semiconducting material, similar to the instant inventions.
However, none of the references disclose the particular method steps of forming a source/drain layer by implanting hydrogen ions into the first oxide semiconducting layer; forming a second oxide semiconducting layer on the buried insulating layer exposed in the gate groove; forming a channel layer by implanting oxygen ions into the second oxide semiconducting layer.
Regarding Claim 20, the prior art of record fails to disclose or suggest a method of forming a semiconductor device, the method comprising forming a groove passing through the interlayer insulating layer and the first oxide semiconducting layer to expose a top surface of the buried insulating layer; forming a second oxide semiconducting layer in the groove; forming a gate electrode pattern in the groove; and implanting oxygen ions into the second oxide semiconducting layer.
Examiner’s comments: the closest prior art references (Yamazaki (US 2012/0161121; Gu US 2021/0336064; Morosawa US 2011/0240998; Liu US 2020/0044039; Song US 2020/0227519) are all directed in part to a method of forming a semiconductor device comprising forming a channel layer and the source/drain layer on the buried insulating layer, the channel layer and the source/drain layer including an oxide semiconducting material, similar to the instant inventions. However, none of the references disclose the particular method steps of forming a groove passing through the interlayer insulating layer and the first oxide semiconducting layer to expose a top surface of the buried insulating layer; forming a second oxide semiconducting layer in the groove; forming a gate electrode pattern in the groove; and implanting oxygen ions into the second oxide semiconducting layer.
Response to Arguments
Applicant’s arguments with respect to claims 1-8, 11 and 21 have been considered but are moot because the new ground of rejection provided above in the rejection addresses the teachings or matters specifically challenged in the argument
Conclusion
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/Q.A.B/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814