DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 11/13/2025. Claims 1-14 & 23-36 are pending in this application. Claims 2, 5, 6 & 11 are withdrawn. Claims 15-22 are canceled.
Claims 1, 3, 4, 7-10, 12-14 & 23-36 are examined in this Office Action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 1, 3, 9, 10, 12 and 23-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carothers et al. (US 2016/0218175) in view of Qian et al. (US 2013/0264688).
Re claim 1, Carothers teaches, under BRI, in view of Fig. 1B, [0015-0016], an integrated circuit (IC), comprising:
-a semiconductor substrate (102) having a first surface and a second surface opposite the first surface, the semiconductor substrate (102) having a first region (region 112) including a first device and a second region (region 114) including a second device;
-a through wafer trench (TWT) (region 108) extending from the first surface of the semiconductor substrate (102) to the second surface of the semiconductor substrate and between the first region and the second region;
-a first dielectric material (110) in the TWT (108);
-an interconnect region (104) over the first surface of the semiconductor substrate (102), the interconnect region including a first metal interconnect structure (130, 132) and a second metal interconnect structure (130, 132, 134, 116) in a second dielectric material (layers of dielectric material of 104), the first metal interconnect structure (130, 132) coupled to the first device (in region 112), the second interconnect structure (130, 132, 134, 116) coupled to the second device (in region 114), and the first metal interconnect structure (130, 132) communicatively coupled to the second metal interconnect structure (130, 132, 134, 116) via at least part of the second dielectric material (of 104) over the TWT (108).
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Carothers does not explicitly teach the first dielectric material covering the second surface.
Qian teaches, Fig. 5A, [0030], the first dielectric material (521) covering the second surface (of 205).
As taught by Qian, one of ordinary skill in the art would utilize & modify the above teaching to obtain the first dielectric material covering the second surface as claimed, because it aids in enhancing protection to a surface of the substrate.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Qian in combination with Carothers due to above reason.
Re claim 1, Carothers teaches, under BRI, in view of Fig. 2B, [0018-0019], an integrated circuit (IC), comprising:
-a semiconductor substrate (202) having a first surface and a second surface opposite the first surface, the semiconductor substrate (202) having a first region (left 214) including a first device and a second region (right 214) including a second device;
-a through wafer trench (TWT) (region 208) extending from the first surface of the semiconductor substrate (202) to the second surface of the semiconductor substrate and between the first region and the second region;
-a first dielectric material (210) in the TWT (208);
-an interconnect region (204) over the first surface of the semiconductor substrate (202), the interconnect region including a first metal interconnect structure (indicated) and a second metal interconnect structure (indicated) in a second dielectric material (layers of dielectric material of 204), the first metal interconnect structure coupled to the first device (in left region 214), the second interconnect structure coupled to the second device (in right region 214), and the first metal interconnect structure (indicated) communicatively coupled to the second metal interconnect structure (indicated) via at least part of the second dielectric material (of 204) over the TWT (208).
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Carothers does not explicitly teach the first dielectric material covering the second surface.
Qian teaches, Fig. 5A, [0030], the first dielectric material (521) covering the second surface (of 205).
As taught by Qian, one of ordinary skill in the art would utilize & modify the above teaching to obtain the first dielectric material covering the second surface as claimed, because it aids in enhancing protection to a surface of the substrate.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Qian in combination with Carothers due to above reason.
Re claim 3, Carothers teaches, Fig. 2B, the first metal interconnect structure (in left 214) includes a first capacitor terminal (232 extended from bottom plate of a capacitor); and the second metal interconnect structure (in right 214) includes a second capacitor terminal (232 extended from top plate of the capacitor).
Re claim 9, Carothers/Qian does not explicitly teach the TWT has a width in a range of 3-50 microns.
Carothers does teach “a width 428 of the isolation region 408 may be 10 microns to 25 microns” [0030].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Carothers to obtain the TWT having a width in a range of 3-50 microns as claimed, because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Re claim 30, Carothers teaches, Fig. 2B, the first metal interconnect structure (indicated) is within a footprint of the first region (left 214), the second metal interconnect structure (indicated) is within a footprint of the second region (right 214), and the first metal interconnect structure (indicated) is communicatively coupled to the second metal interconnect structure (indicated) via a part of the second dielectric material (of 204) directly over the TWT (208) (see also Fig. 1B).
Re claims 31 & 32, Carothers teaches the first dielectric material (e.g., dielectric fill material 556) includes an organic material, wherein the organic material includes at least one of: proxy, polyimide, silicone, Teflon, or benzocyclobutene (BCB) [0039].
Re claims 33 & 34, Carothers teaches the first dielectric material includes an inorganic material, wherein the inorganic material includes at least one of: glass, ceramic, or silicon dioxide [0039].
Re claim 35, in combination cited above, Qian teaches, Fig. 8, [0036], a diffusion barrier layer (931) on the first dielectric material (521), in which the first dielectric material (521) is between the second surface (213) and the diffusion barrier layer (931).
Re claim 36, Carothers teaches at least one of the first or second surfaces (of 202) is a planar surface (Fig. 2B).
Re claim 10, Carothers teaches, under BRI, in view of Fig. 2B, [0003, 0018-0019], an integrated circuit (IC), comprising:
-a semiconductor substrate (202) having a first surface and a second surface opposite the first surface, the semiconductor substrate (202) having a first region (left 214) including a first circuit and a second region (right 214) including a second circuit;
-a trench (region 208) extending from the first surface of the semiconductor substrate (202) to the second surface of the semiconductor substrate and between the first region and the second region;
-a first dielectric material (210) in the trench (208);
-an interconnect region (204) over the first surface of the semiconductor substrate (202), the interconnect region including: a first metal interconnect structure (indicated) and a second metal interconnect structure (indicated) in a second dielectric material (layers of dielectric material of 204),
wherein the first circuit (in left 214) is configurable to transmit a signal (as functional/intended use) to the second circuit (in right 214) via the first metal interconnect structure (indicated), the second metal interconnect structure (indicated), and at least part of the second dielectric material (of 204) over the trench (208).
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Carothers does not explicitly teach the first dielectric material covering the second surface.
Qian teaches, Fig. 5A, [0030], the first dielectric material (521) covering the second surface (of 205).
As taught by Qian, one of ordinary skill in the art would utilize & modify the above teaching to obtain the first dielectric material covering the second surface as claimed, because it aids in enhancing protection to a surface of the substrate.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Qian in combination with Carothers due to above reason.
Re claim 12, Carothers teaches, Fig. 2B, the first metal interconnect structure (in left 214) includes a first capacitor terminal (232 extended from bottom plate of a capacitor); and the second metal interconnect structure (in right 214) includes a second capacitor terminal (232 extended from top plate of the capacitor).
Re claim 23, Carothers teaches, Fig. 2B, the first metal interconnect structure (indicated) is within a footprint of the first region (left 214), the second metal interconnect structure (indicated) is within a footprint of the second region (right 214), and the first circuit (in left 214) is configurable to transmit the signal to the second circuit (in right 214) via the first metal interconnect structure (indicated), a part of the second dielectric material (of 204) directly over the trench (208), and the second metal interconnect structure (indicated).
Re claims 24 & 25, Carothers teaches the first dielectric material (e.g., dielectric fill material 556) includes an organic material, wherein the organic material includes at least one of: proxy, polyimide, silicone, Teflon, or benzocyclobutene (BCB) [0039].
Re claim 26 & 27, Carothers teaches the first dielectric material includes an inorganic material, wherein the inorganic material includes at least one of: glass, ceramic, or silicon dioxide [0039].
Re claim 28, in combination cited above, Qian teaches, Fig. 8, [0036], a diffusion barrier layer (931) on the first dielectric material (521), in which the first dielectric material (521) is between the second surface (213) and the diffusion barrier layer (931).
Re claim 29, Carothers teaches at least one of the first or second surfaces (of 202) is a planar surface (Fig. 2B).
3. Claims 4 and 13 is/are rejected under 35 U.S.C. 103 as being obvious over Carothers as modified by Qian as applied to claims 1, 3, 10 & 12 above, and further in view of El-Hinnawy et al. (US 2020/0058581).
The teachings of Carothers/Qian have been discussed above.
Re claims 4 & 13, Carothers/Qian does not teach the first and second terminals are part of a metal-oxide-metal or a metal-insulator-metal capacitor.
El-Hinnawy teaches MIM and/or MOM capacitor structures [0033, 0052].
As taught by El-Hinnawy, one of ordinary skill in the art would utilize the above teaching capacitors to obtain at least one of a metal-oxide-metal or metal-insulator-metal capacitor as claimed, because they are known and widely utilized in the art for having better characteristics of stable capacitance.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by El-Hinnawy in combination Carothers/Qian due to above reason.
4. Claims 7, 8 and 14 is/are rejected under 35 U.S.C. 103 as being obvious over Carothers as modified by Qian as applied to claims 1 & 10 above, and further in view of Subramanian et al. (US 7,309,659).
The teachings of Carothers/Qian have been discussed above.
Re claims 7, 8 & 14, Carothers/Qian does not teach the first dielectric material includes a parylene compound; and includes a fluorinated parylene compound.
Subramanian teaches fluorinated parylenes (claim 2).
As taught by Subramanian, one of ordinary skill in the art would utilize the above teaching to obtain parylene compound or a fluorinated parylene compound as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Subramanian in combination Carothers/Qian due to above reason.
Response to Arguments
5. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant submits “the Office has not cited any portion of Carothers to support the metal line 132 (part of the alleged first metal interconnect structure) is commucatively coupled to metal line 116 (part of the alleged second metal interconnect structure) via the dielectric material of interconnection region 104, let alone part of the dielectric material over isolation region 108/110 (the alleged TWT). Quian and other references fail to cure the deficiencies of Carothers”.
The examiner respectfully disagrees.
Amended claim 1 recites “the first metal interconnect structure communicatively coupled to the second metal interconnect structure via a least part of the second dielectric material over the TWT”. Under BRI, Carothers teaches, indicated above in Fig. 1B, the first metal interconnect structure (130, 132) communicatively coupled to the second metal interconnect structure (130, 132, 134, 116) via at least part of the second dielectric material (of 104) over the TWT (108). Further, Carothers teaches, indicated above in Fig. 2B, the first metal interconnect structure (indicated) communicatively coupled to the second metal interconnect structure (indicated) via at least part of the second dielectric material (of 204) over the TWT (208). As the claim requires first & second metal interconnect structures “communicatively coupled” via at least part of the second dielectric material, it is clear to a skilled person in the art to recognize & utilize the teaching of Carothers to arrive the claimed invention. Similar reason/response also applied to claim 10, and Carothers teaches, under BRI, indicated above in Fig. 2B, the first circuit (in left 214) is configurable to transmit a signal (as functional/intended use) to the second circuit (in right 214) via the first metal interconnect structure (indicated), the second metal interconnect structure (indicated), and at least part of the second dielectric material (of 204) over the trench (208).
Hence, given a broadest reasonable interpretation, Carothers meets the claimed invention. Details included in the above rejection.
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 12/2/25