Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Request for Continued Examination
The request filed on 12/15/25 for a Request for Continued Examination (RCE) under 37 CFR 1.114 is acceptable and an RCE has been established. An action on the RCE follows.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 27, 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Patent Publication No. 2015/0001460) in view of YOON et al. (U.S. Patent Publication No. 2018/0090325) and further in view of JIANG et al. (U.S. Patent Publication No. 2023/0066393).
Referring to figures 3-38, Kim et al. teaches a system, comprising:
a processor operably coupled to an input device and an output device (see paragraph# 183, figure 39); and an electronic device (1130) operably coupled to the processor (see figure 39), the electronic device comprising: strings of memory cells vertically extending through a stack comprising vertically alternating sequences of insulative structures (125) and conductive structures (G) arranged in tiers (see figures 5, 7); and
a charge storage structure (135b) circumferentially surrounding at least some of the strings of memory cells, the charge storage structure (135) comprising a tunnel dielectric material (135a) vertically extending through the stack and discontinuous portions of a charge storage material in horizontal alignment with the tunnel dielectric material and a respective conductive structure (G) of the stack (see figures 5, 7).
However, the reference does not clearly teach the conductive contact structure in horizontal alignment with portions of a channel material, the channel material extending through the stack and charge storage material comprising HfZrOx (in claim 27).
YOON et al. teaches a semiconductor device having the conductive contact structure (126) in horizontal alignment with portions of a channel material (122), the channel material (122) extending through the stack (160/180, see figure 8d).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form the conductive contact structure in horizontal alignment with portions of a channel material, the channel material extending through the stack in Kim et al. as taught by YOON et al. because it is known in the semiconductor art to form a memory device having high integration and excellent electrical characteristics.
JIANG et al. teaches a memory device having HfO2, or HfZrOx as a charge storage material (see paragraph# 35, meeting claims 17, 29).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form HfZrOx as a charge storage material in Kim et al. as taught by JIANG et al. because choosing an optimum material for a layer is known in the semiconductor art to form less defects memory device.
Claim 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Patent Publication No. 2015/0001460) in view of YOON et al. (U.S. Patent Publication No. 2018/0090325) and further in view of JIANG et al. (U.S. Patent Publication No. 2023/0066393), as applied in claim(s) 27, 29 above in view of LUE et al. (U.S. Patent Publication No. (2015/0340371).
Referring to figures 3-38, Kim et al. teaches an electronic device, comprising:
a stack comprising tiers of alternating conductive structures (G) and insulative structures (125, see figure 3);
pillars vertically extending through the stack (G/125), the pillars (135a/PL/127) comprising a tunnel dielectric material (135a), a channel material (PL), and an insulative material (127) substantially surrounded by the channel material (see figures 5, 7); and
a memory material (135b) horizontally adjacent to the conductive structures (G) without being horizontally adjacent to the insulative structures (125, see figures 5b, 7).
However, the reference does not clearly teach the memory material comprises crystalline nanoparticles embedded within a high-k dielectric material comprising one or more of hafnium oxide, hafnium zirconium oxide, and zirconium oxide (in claim 30).
LUE teaches the memory material comprises crystalline nanoparticles embedded within a high-k dielectric material comprising one or more of hafnium oxide, hafnium zirconium oxide, and zirconium oxide (see paragraph# 162, meeting claim 30).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the memory material comprises crystalline nanoparticles embedded within a high-k dielectric material comprising one or more of hafnium oxide, hafnium zirconium oxide, and zirconium oxide in Kim et al. as taught by LUE et al. because it would provide high charge trapping efficiency (see paragraph# 162).
Claims 28, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Patent Publication No. 2015/0001460) in view of YOON et al. (U.S. Patent Publication No. 2018/0090325) and further in view of JIANG et al. (U.S. Patent Publication No. 2023/0066393), as applied in claim(s) 27, 29 above in view of RABKIN et al. (U.S. Patent Publication No. 2023/0164996).
Referring to figures 3-38, Kim et al. teaches an electronic device, comprising:
a stack comprising tiers of alternating conductive structures (G) and insulative structures (125, see figure 3);
pillars vertically extending through the stack (G/125), the pillars (135a/PL/127) comprising a tunnel dielectric material (135a), a channel material (PL), and an insulative material (127) substantially surrounded by the channel material (see figures 5, 7); and
a memory material (135b) horizontally adjacent to the conductive structures (G) without being horizontally adjacent to the insulative structures (125, see figures 5b, 7).
However, the reference does not clearly teach at least some memory cells of the strings of memory cells are configured as multi-level cells (MLC) (in claim 28), the electronic device comprises a 3D NAND Flash memory device comprising at least one memory array and a CMOS under array (CUA) region under the at least one memory array (in claim 31).
RABKIN et al. teaches a memory cells of the strings of memory cells are configured as multi-level cells (MLC) (see paragraphs# 30, meeting claim 28), the electronic device comprises a 3D NAND Flash memory device comprising at least one memory array (see paragraph# 120) and a CMOS under array (CUA) region under the at least one memory array (see paragraph# 41, meeting claim 31).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form memory cells of the strings of memory cells are configured as multi-level cells (MLC), the electronic device comprises a 3D NAND Flash memory device comprising at least one memory array and a CMOS under array (CUA) region under the at least one memory array in Kim et al. as taught by RABKIN et al. because it is known in the art to form a desired a three-dimensional memory device.
Allowable Subject Matter
Claims 1-5, 7-11, 13-18, 32 are allowed. None of the prior art teaches or suggests a memory material horizontally adjacent to the conductive structures without being horizontally adjacent to the insulative structures, the memory material comprising crystalline nanoparticles embedded within a high-k dielectric material comprising one or more of hafnium zirconium oxide and zirconium oxide (in claim 1); a second insulative material directly horizontally adjacent to the first insulative material, and a third insulative material directly horizontally adjacent to the second insulative material, a material composition of the second insulative material differing from a material composition of each of the first insulative material and the third insulative material, wherein the first insulative material comprises a high-k dielectric material, the second insulative material comprises a switching material, and the third insulative material comprises a dipole modulation material (in claim 8); a memory material comprising ruthenium nanoparticles in an oxide material comprising zirconium, the memory material separating vertically neighboring conductive structures, individual portions of the memory material laterally adjacent to the tunnel material and a respective conductive structure (in claim 14).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pairdirect.uspto.gov. Should you have questions on access to thy Private PAIR system, contact the Electronic Business center (EBC) at 866-217-9197 (toll-free).
/THANH T NGUYEN/Primary Examiner, Art Unit 2893
Prosecution Insights