DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 4/21/26.
Applicant’s amendment to claims 1 and 4 is acknowledged.
Applicant’s addition of new claim 21 is acknowledged.
Claim 18 is cancelled.
Claims 1-17, 19 and 20 are pending and claim 14 is withdrawn.
Claims 1-13, 15-17, 19 and 20 are subject to examination at this time.
Response to Arguments
Applicant's arguments filed 4/21/26 have been fully considered but they are not persuasive.
MPEP § 2125, Drawings as Prior Art, indicates:
” Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972)…When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). See MPEP § 2121.04 for more information on prior art drawings as “enabled disclosures.”
In figs. 2, 3B-3D and 5A-5B, one of ordinary skill in the art can clearly see in the drawings that the “all of the second-conductivity type voltage withstanding regions (21) have a same thickness in a depth direction…”
In fig. 3C, the p type layers (50) are deposited to form the second-conductivity type voltage withstanding regions (21). Takeuchi at para. [0075] discloses “This makes it possible to equalize the thicknesses of the p type layers 50 formed on the cell portion, the connection portion and the guard ring portion.” This disclosure teaches or suggests that it is important for the second-conductivity type voltage withstanding regions (21) to have a same thickness.
Assuming for the sake of argument that anisotropic etching process such as RIE (Reactive Ion Etching) may cause microloading (which is not conceded), one of ordinary skill in the art would tune the etching parameters or etch chemistry to address the microloading because Takeuchi teaches it is important to “equalize the thicknesses”.
Allowable Subject Matter
Claims 4 and 10 are allowed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In claim 21, there does not seem to be support for the limitation “the second-conductivity type voltage withstanding regions have an impurity concentration that is less than that of the second semiconductor region”.
In the specification at para. [0068], the second semiconductor region appears to be formed by ion implantation at the same time as the second-conductivity type voltage withstanding region. Thus, the second semiconductor region appears to have a same impurity concentration as the second-conductivity type voltage withstanding region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 11-13, 15-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al., US Publication No. 2019/0386094 A1 (from the IDS).
Takeuchi teaches:
1. A semiconductor device (see figs. 1-3 and 5) having an active region (e.g. cell portion) through which a main current flows and a termination region (e.g. guard ring portion) surrounding a periphery of the active region, the semiconductor device comprising:
a semiconductor substrate (1/2) containing a semiconductor (e.g. SiC) having a band gap wider than a band gap of silicon, the semiconductor substrate having a first main surface and a second main surface opposite to each other;
a first semiconductor region (2) of a first conductivity type (n-type), provided in the semiconductor substrate;
a second semiconductor region (3) of a second conductivity type (p-type), provided in the active region, between the first main surface of the semiconductor substrate and the first semiconductor region;
a device element structure (4/7/8) formed in the active region, and including a pn junction between the second semiconductor region (3) and the first semiconductor region (2);
a first electrode (9) electrically connected to the second semiconductor region (3);
a second electrode (11) provided on the second main surface of the semiconductor substrate; and
a field limiting ring structure (21) in which a plurality of second-conductivity-type voltage (p-type) withstanding regions (21) are selectively provided apart from one another in a direction parallel to the first main surface in the first semiconductor region, in surface regions of the semiconductor substrate at the first main surface thereof in the termination region, the second-conductivity-type voltage withstanding regions (21) each concentrically surrounding the periphery of the active region, an interval between an adjacent two second-conductivity-type voltage (21) withstanding regions in a radial direction of a concentric circle formed by the second-conductivity-type voltage withstanding regions increases in a direction away from the active region, wherein
…each of the second-conductivity-type voltage withstanding regions (21) having side surfaces and a bottom surface connecting the side surfaces, the side surfaces and the bottom surface being in direct contact with the first semiconductor region (2),
the first semiconductor region (21) reaches the first main surface of the semiconductor substrate (1/2) at portions between any adjacent two of the second-conductivity-type voltage withstanding regions (21), as viewed from a direction orthogonal to the first main surface of the semiconductor substrate, and… See Takeuchi at para. [0001] – [0136], figs. 1-9.
Regarding claim 1:
Takeuchi is silent regarding the impurity concentration and thickness of the second-conductivity-type voltage withstanding region (21).
However, Takeuchi teaches the p-type deep layer (5) has a depth of 1 µm or less, which overlaps the claimed range. See Takeuchi at para. [0039]. Also see the disclosure of 2 µm at para. [0040].
Takeuchi further teaches the p-type deep layer (5) has an impurity concentration of 1.0×1017/cm3 to 1.0×1019/cm3, which overlaps the claimed range. See Takeuchi at para. [0040].
It would have been obvious to one of ordinary skill in the art to form:
“the second-conductivity-type voltage withstanding regions have an impurity concentration that is less than 1x1018/cm3;
all of the second-conductivity type voltage withstanding regions have a same thickness in a depth direction that is in a range of 0.7 µm to 1.1 µm”
because
Takeuchi, in figs. 3B-3E teaches the second-conductivity-type voltage withstanding region (21) are formed at the same time as p-type deep layer (5); and
Takeuchi teaches or suggests that it is important for the second-conductivity type voltage withstanding regions (21) to have a same thickness in the disclosure
at para. [0075] “This makes it possible to equalize the thicknesses of the p type layers 50 formed on the cell portion, the connection portion and the guard ring portion.” (e.g. See fig. 3C where the p type layers (50) are deposited to form the second-conductivity type voltage withstanding regions (21).)
Takeuchi further teaches:
2. The semiconductor device according to claim 1, wherein the impurity concentration of the second-conductivity-type voltage withstanding regions is in a range of 3x1017/cm3 to 9x1017/cm3 (e.g. Takeuchi teaches the p-type deep layer (5) has an impurity concentration of 1.0×1017/cm3 to 1.0×10 19/cm3, which overlaps the claimed range. See Takeuchi at para. [0040]. Since the second-conductivity-type voltage withstanding region (21) are formed at the same time as p-type deep layer (5) in figs. 3B-3E, it would have been obvious to one of ordinary skill in the art the second-conductivity-type voltage withstanding region (21) have the same impurity concentration as the p-type deep layer (5).)
11. The semiconductor device according to claim 1, wherein the second- conductivity-type voltage withstanding regions (21) all have a same width that is a shortest length of the second-conductivity-type voltage withstanding regions in a direction parallel to the first main surface of the semiconductor substrate, fig. 5B.
12. The semiconductor device according to claim 1, wherein
each second-conductivity-type voltage withstanding region (21) has a width that is a shortest length of said each second-conductivity-type voltage withstanding region in a direction parallel to the first main surface of the semiconductor substrate, and
the width of a second and subsequent ones of the second-conductivity-type voltage withstanding regions (21) at least second from the active region is wider than the width of an innermost one of the second-conductivity-type voltage withstanding regions closest to the active region, fig. 2.
13. The semiconductor device according to claim 1, wherein the second- conductivity-type voltage withstanding regions (21) reach the first main surface of the semiconductor substrate (1/2), fig. 2.
15. The semiconductor device according to claim 1, wherein the second- conductivity-type voltage withstanding regions (21) each have, in a cross-sectional view thereof, a rectangular shape (e.g. rectangular shape in fig. 2) or a barrel-like shape having a width that is relatively wider at a center position in a depth direction.
16. The semiconductor device according to claim 1, wherein a portion of the first main surface of the semiconductor substrate in the termination region (e.g. guard ring portion) is free of a conductive film (e.g. layer 10 is insulation film), fig. 2.
17. The semiconductor device according to claim 1, wherein a portion of the first main surface of the semiconductor substrate in the termination region (e.g. guard ring portion) is covered by an insulating layer (10), fig. 2.
20. The semiconductor device according to claim 1, wherein the first main surface of the semiconductor substrate (1/2) is recessed (20) toward the second main surface of the semiconductor substrate in the termination region (e.g. guard ring portion) as compared to the active region (e.g. cell portion), fig. 2.
Claim(s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi, as applied to claim 1 above, and further in view of Endo et al., US Patent No. 2018/0151366 A1.
Regarding claim 3:
Takeuchi teaches all the limitations of claim 1 above, but does not expressly teach:
a second-conductivity-type high-concentration region selectively provided between the second semiconductor region and the first semiconductor region
In an analogous art, Endo teaches:
3. The semiconductor device according to claim 1, the comprising (see fig. 2)
a second-conductivity-type high-concentration region (30) selectively provided between the second semiconductor region (3) and the first semiconductor region (2b), and in contact with the second semiconductor region (3), the second-conductivity-type high-concentration region (30) surrounding the periphery of the active region (e.g. cell region in fig. 1; gate region 8/9 in fig. 2) and having an impurity concentration (e.g. p+ concentration) higher than an impurity concentration of the second semiconductor region (e.g. p concentration), wherein
the second-conductivity-type high-concentration region (30) is provided between the active region (e.g. cell region in fig. 1; gate region 8/9 in fig. 2) and the second-conductivity-type voltage withstanding regions (21) and faces the second- conductivity-type voltage withstanding regions (21) in a direction parallel to the first main surface of the semiconductor substrate, para. [0033] – [0052].
Regarding claim 5:
Endo further teaches:
5. The semiconductor device according to claim 3, wherein an innermost one of the second-conductivity-type voltage withstanding regions (21) is in contact with the second- conductivity-type high-concentration region (30), the innermost one being closest among the second-conductivity-type voltage withstanding regions to the active region, fig. 2.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Takeuchi with the teachings of Endo to provide coupling between “…the p-type deep layer 5 located in the cell region on the outer peripheral region side… to one p-type guard ring layer 21”. See Endo at para. [0049].
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi in view of Endo, as applied to claim 1 above, and further in view of Yamada et al., US Publication No. 2018/0308939 A1 (of record).
Regarding claims 6:
Takeuchi and Endo teach all the limitations of claims 1 and 3 above, but do not expressly teach specific numerical amounts for the intervals between the second-conductivity-type voltage withstanding region or specifically:
wherein a second interval between the innermost one of the second-conductivity-type voltage withstanding regions and a second one of the second-conductivity-type voltage withstanding regions is at most 2.1 µm, the second one being second among the second-conductivity-type voltage withstanding regions from the active region.
In an analogous art, Yamada teaches (see fig. 3) the interval (Lb1, Lb2, Lb3) between voltage withstanding regions (11, 12, 13) is a result effective variable to achieve a uniform electric field, maintain breakdown voltage and suppress occurrence of electrical discharge. See Yamada at para. [0054] – [0060].
It would have been obvious to one having ordinary skill in the art to form the second-conductivity-type voltage withstanding region to have the numerical intervals recited in claim 6, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Regarding claims 7-9:
Takeuchi and Endo teach all the limitations of claims 1 and 3 above, but do not expressly teach specific numerical amounts for the intervals between the second-conductivity-type voltage withstanding region or specifically:
wherein among the second- conductivity-type voltage withstanding regions, a third interval between a second one of the second-conductivity-type voltage withstanding regions and a third one of the second- conductivity-type voltage withstanding regions is at most 3.1 µm, the second one being second from the active region and the third one being third from the active region;
wherein the third interval is at most 1.0 µm;
wherein among the second- conductivity-type voltage withstanding regions, a fourth interval between the third one of the second-conductivity-type voltage withstanding regions and a fourth one of the second- conductivity-type voltage withstanding regions is at most 2.0 µm, the fourth one being fourth from the active region.
In an analogous art, Yamada teaches (see fig. 3) the interval (Lb1, Lb2, Lb3) between voltage withstanding regions (11, 12, 13) is a result effective variable to achieve a uniform electric field, maintain breakdown voltage and suppress occurrence of electrical discharge. See Yamada at para. [0054] – [0060].
It would have been obvious to one having ordinary skill in the art to form the second-conductivity-type voltage withstanding region to have the numerical intervals recited in claims 7-9, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the before the effective filling date of the claimed invention to modify the teachings of Takeuchi with the teachings of Yamada because “By forming the breakdown voltage structure to satisfy at least expression (2) or expression (4), electric field applied to the surface protecting film 8 on the front surface of the silicon carbide base 4 may be made uniform, while the electric field strength in the silicon carbide base 4 is set to be about equal to that in the conventional breakdown voltage structure and the breakdown voltage is maintained…and the occurrence of electrical discharge at the surface of the surface protecting film 8 and/or at the interface of the surface protecting film 8 and the gel may be suppressed.” See Yamada at para. [0056].
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi, as applied to claim 1 above, and further in view of Kobayashi et al., US Publication No. 2018/0040688 A1 (of record).
Regarding claim 19:
Takeuchi teaches all the limitations of claim 1 above, but does not expressly teach a channel stopper.
In an analogous art, Kobayashi teaches:
19. The semiconductor device according to claim 1, (see figs. 17-18) further comprising a channel stopper region (105) that is provided closer to a chip end than are the second- conductivity-type voltage withstanding regions (106, 107), the channel stopper region (104) having an upper surface that is exposed to the first main surface of the semiconductor substrate (101) and a lower surface (e.g. bottom surface forming interface with 101) that is farther from the first main surface of the semiconductor substrate (101) than is an upper surface (e.g. top surface forming interface with 105) of each second-conductivity-type voltage withstanding region (106, 107). See Kobayashi at para. [0026] – [0027].
It would have been obvious to a person of ordinary skill in the before the effective filling date of the claimed invention to modify the teachings of Takeuchi with the teachings of Kobayashi because a channel stopper is included in a conventional power semiconductor device having an edge termination region. See Kobayashi at para. [0026] – [0027]. Also see MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
15 June 2026
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