Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/21/25 has been entered.
Applicant's amendment/arguments filed on 11/21/25 as being acknowledged and entered. By this amendment claims 3 and 6 are canceled and claims 1-2, 4-5, and 7-19 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-2, 4, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Or-Bach et al. (US Patent 8,803,206).
Claim 1: Or-Bach teaches (Fig. 53) a method comprising: providing a supply (Col. 125-126) from a package substrate to power gate transistors (5376, 5351) in a device layer (5322) of a circuit structure, the power gate transistors coupled to circuitry (5335, 5383, 5381 etc.) operable to receive a gated supply from the power gate transistors, the circuity on a first side of the device layer (Col. 126), the first side opposite the package substrate, and the circuitry coupled directly to the carrier substrate (5395), the carrier substrate on a side of the circuitry opposite the device layer; wherein each of the power gate transistors comprises a three-dimensional channel body, and a gate electrode over a top and along sidewalls of the three-dimensional channel body, the gate electrode electrically coupled to an interconnect of the circuitry (Col. 36) by a conductive contact, the conductive contact directly between the gate electrode and the interconnect (Fig 26F, 29B, 29D (42B-C, 43A-B); and distributing the gated supply from the power gate transistors to the circuitry using a grid (5330) on a second side of the device layer, the second side opposite the first side, wherein the grid, the device layer, the circuitry and the carrier substrate are included in the same die. Or-Bach teaches the transistors in figure 53 can be finfets which reads on the gate electrode structure claimed. Or-Bach teaches in several instances, an interconnect directly connected to the gate electrode via a conductive contact. Additionally this is common in the art to connect the gate electrode to a variety of other circuitry within a chip or to an outside component.
Claim 2: Or-Bach teaches (Fig. 53) providing a supply to power gate transistors comprises coupling to the transistors from the second of the device layer.
Claim 4: Or-Bach teaches (Fig. 53) distributing the gated supply from the power gate transistors comprises coupling the transistors to the grid from the underside of the transistors.
Claim 5: Or-Bach teaches (Fig. 53) controlling the gated supply from a control line coupled to the transistors on the first side.
Claim(s) 7-19 are rejected under 35 U.S.C. 103 as being unpatentable over Bose et al (US PGPub 2014/0148961) in view of Or-Bach et al. (US Patent 8,803,206).
Claim 7: Bose teaches [0010, 0026-0027] (Fig. 4) a method of fabricating an apparatus, the method comprising: forming a circuit structure comprising a device stratum comprising a plurality of transistor devices, the device stratum (402) having a first side and a second side opposite the first side, the circuit structure comprising circuitry on the first side of the device stratum; and forming a gated supply grid (428/430) on the second side of the device stratum, wherein a drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid, wherein the drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid through a contact, the contact (412) on the second side of the device stratum and extending between the gated supply grid and the second side of the device stratum but not into the device stratum; and coupling the circuit structure to a package substrate, the circuity of the circuit structure on a side of the plurality of transistors opposite the package substrate. Bose does not teach wherein each of the plurality transistors comprises a three-dimensional channel body, and a gate electrode over a top and along sidewalls of the three-dimensional channel body the gate electrode electrically coupled to an interconnect of the circuitry (Col. 36) by a conductive contact, the conductive contact directly between the gate electrode and the interconnect, or describe the circuitry directly coupled to a carrier substrate, the carrier substrate on a sides of the circuitry opposite the device stratum; the gated supply grid, the device stratum, the circuitry, and the carrier substrate are included on the same die. Or-Bach teaches (Fig. 53, Cols. 36, 125-126) each of the plurality transistors comprises a three-dimensional channel body, and a gate electrode over a top and along sidewalls of the three-dimensional channel body, the gate electrode electrically coupled to an interconnect of the circuitry (Col. 36) by a conductive contact, the conductive contact directly between the gate electrode and the interconnect (Fig 26F, 29B, 29D (42B-C, 43A-B); and describes the circuitry directly coupled to a carrier substrate, the carrier substrate on a sides of the circuitry opposite the device stratum; the gated supply grid, the device stratum, the circuitry, and the carrier substrate are included on the same die as described in claim 1 to increase package efficiency (Col. 1-2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Bose to have specified the circuitry directly coupled to a carrier substrate, the carrier substrate on a sides of the circuitry opposite the device stratum; the gated supply grid, the device stratum, the circuitry, and the carrier substrate are included on the same die to increase package efficiency (Col. 1-2) as taught by Or-Bach. Or-Bach teaches the transistors in figure 53 can be finfets which reads on the gate electrode structure claimed. Or-Bach teaches in several instances, an interconnect directly connected to the gate electrode via a conductive contact. Additionally this is common in the art to connect the gate electrode to a variety of other circuitry within a chip or to an outside component.
Claim 8: Or-Bach teaches (Fig. 53) forming a supply grid on the second side of the device stratum, wherein a source of at least one of the plurality of transistor devices is coupled to the supply grid. The claim doesn’t require direct coupling so if the transistor is coupled to the grid, so is the source.
Claim 9: Or-Bach teaches (Fig. 53) (Col. 125-126) a control line on a first side of the device stratum, wherein the gate electrode of the at least one of the plurality of transistor devices is coupled to the control line. The claim doesn’t require direct coupling therefore the reference teaching control circuitry connecting to the device stratum reads on coupling.
Claim 10: Or-Bach teaches (Fig. 53) (Col. 125-126) the gate electrode of the at least one of the plurality of transistor devices is coupled to the control line through a gate contact projecting between the device and the control line and the drain of the device is coupled to the gated supply grid through a junction contact projecting between the device and the gated supply grid. The claim does not require the contact to be in physical or electrical contact so it could be any contact in the system since it could be coupled by being in the same overall IC package.
Claim 11: Or-Bach teaches (Fig. 53) (Col. 125-126) forming a contact point operable to couple the circuit structure to an external power source, the contact point coupled to the supply grid on the second side of the device stratum.
Claim 12: Or-Bach teaches (Fig. 53) (Col. 125-126) the gated supply grid comprises a power grid, the method further comprising forming a ground grid on the second side of the device stratum.
Claim 13: Or-Bach teaches the transistor devices comprises a non-planar transistor device comprising a fin and the gate electrode is disposed on the channel region of the fin to lower the contact resistance (Col. 28). The use of FinFets is well known in the art.
Claim 14: Bose teaches [0010, 0026-0027] (Fig. 4) a method of fabricating a system, the method comprising: providing a supply connection (412); and coupling a die (400) to the supply connection, the die comprising: (i) core logic circuitry (408) to receive one or more gated supplies, and (ii) a plurality of transistors (418) defining a device layer and coupled between the supply connection and the core logic circuitry to controllably provide the one or more gated supplies to the core logic circuitry, the core logic circuitry on a first side of the device layer, the first layer opposite the package substrate, each of the plurality of transistors comprising a gate electrode, wherein the gated supplies to the circuitry is routed (442) on a second side of the device layer, the second side opposite the first side, wherein a drain of at least one of the plurality of transistors is coupled to the gated supplies through a contact, the contact on the second side of the device stratum and extending between the gated supplies and the second side of the device layer but not into the device layer. Bose does not teach the plurality of transistors having a three-dimensional channel body, and a gate electrode over a top and along sidewalls of the three-dimensional channel body, the gate electrode electrically coupled to an interconnect of the core logic circuity by a conductive contact, the conductive contact directly between the gate electrode and the interconnect or describe the core logic circuitry coupled directly to a carrier substrate, the carrier substrate on a side of the core logic circuitry opposite the device layer. Or-Bach teaches (Fig. 53) (Col. 125-126) plurality of transistors having a three-dimensional channel body, and a gate electrode over a top and along sidewalls of the three-dimensional channel body, the gate electrode electrically coupled to an interconnect the core logic circuity (Col. 36) by a conductive contact, the conductive contact directly between the gate electrode and the interconnect (Fig 26F, 29B, 29D (42B-C, 43A-B), the core logic circuitry coupled directly to a carrier substrate, the carrier substrate on a side of the core logic circuitry opposite the device layer to increase package efficiency (Col. 1-2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Bose to have specified the core logic circuitry coupled directly to a carrier substrate, the carrier substrate on a side of the core logic circuitry opposite the device layer to increase package efficiency (Col. 1-2) as taught by Or-Bach. Or-Bach teaches the transistors in figure 53 can be finfets which reads on the gate electrode structure claimed. Or-Bach teaches in several instances, an interconnect directly connected to the gate electrode via a conductive contact. Additionally this is common in the art to connect the gate electrode to a variety of other circuitry within a chip or to an outside component.
Claim 15: Or-Bach teaches (Fig. 53) (Col. 125-126the one or more gated supplies are coupled to the plurality of transistors from the underside of the device layer.
Claim 16: Or-Bach teaches (Fig. 53) (Col. 125-126a supply connection to the power gate transistors comprises a grid on the underside of the device layer.
Claim 17: Or-Bach teaches (Fig. 53) (Col. 125-126distributing the gated supply from the power gate transistors comprises coupling the transistors to the grid from the underside of the device layer.
Claim 18: Or-Bach teaches (Fig. 53) (Col. 125-126controlling the gated supply from a control line coupled to the plurality of transistors on the first side of the device layer.
Claim19: Or-Bach teaches the transistor devices comprises a non-planar transistor device comprising a fin and the gate electrode is disposed on the channel region of the fin to lower the contact resistance (col. 28). The use of FinFets is well known in the art.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 3-5, and 7-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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