DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Jeun et al. (US 7449774).
With regard to claim 1, Jeun teaches, in Figs 1 and 2, a semiconductor device comprising: a first lead (40); a first semiconductor element (11) mounted on the first lead; and a sealing resin (60) that covers the first semiconductor element, wherein the first lead comprises: a first die pad (41) having a first main surface (upper surface in the figure) and a first back surface (lower surface in the figure) facing opposite sides to each other in a thickness direction; a second die pad (42) arranged side by side with the first die pad in a first direction orthogonal to the thickness direction, and located on a side of the first main surface with respect to the first die pad in the thickness direction; and a connecting portion (44) connected to the first die pad and the second die pad, wherein the first back surface is exposed from the sealing resin, wherein the second die pad has a second back surface (lower surface in the figure) facing a same side as the first back surface in the thickness direction, and wherein the second back surface is arranged at a position different from the first back surface in the thickness direction (see figures).
With regard to claim 2, Jeun teaches, in Figs 1 and 2, that the first semiconductor element is mounted on the first main surface (see figures).
With regard to claim 3, Jeun teaches, in Figs 1 and 2, that the second die pad further has a second main surface (upper surface in the figures) facing the same side as the first main surface in the thickness direction.
With regard to claim 4, Jeun teaches, in Figs 1 and 2, a first connecting member (50) connected to the first semiconductor element and the second main surface.
With regard to claim 5, Jeun teaches, in Figs 1 and 2, a second semiconductor element (31) mounted on the second main surface.
With regard to claim 6, Jeun teaches, in Figs 1 and 2, a second connecting member (another instance of 50) connected to the first semiconductor element and the second semiconductor element.
With regard to claim 7, Jeun teaches, in Figs 1 and 2, a bonding layer interposed between the second main surface and the second semiconductor element (not shown, but discussed at column 5, lines 5-15).
With regard to claim 8, Jeun teaches, in Figs 1 and 2, that the bonding layer is solder (column 5, lines 5-15).
With regard to claim 9, Jeun teaches, in Figs 1 and 2, that the first semiconductor element is a switching element, and the second semiconductor element is a drive element that drives the first semiconductor element (column 3, lines 1-30).
With regard to claim 10, Jeun teaches, in Figs 1 and 2, a metal layer arranged on the second main surface (column 5, lines 5-15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeun et al. (US 7449774) in view of Danno et al. (US 2017/0301643).
With regard to claim 11, Jeun teaches most of the limitations of the claim, as set forth above with regard to claim 10.
Jeun does not explicitly teach that the metal layer contains Ag.
Danno teaches that the metal layer contains Ag ([0226]) so that, “the reliability of the semiconductor device can be improved,” ([0010]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Jeun with the metal layer of Danno to improve reliability.
With regard to claim 12, Jeun teaches most of the limitations of the claim, as set forth above with regard to claim 10.
Jeun does not explicitly teach that the metal layer is contained in the second main surface when viewed in the thickness direction.
Danno teaches, in Fig 6, that the metal layer (BD2) is contained in the second main surface (top surface of DP2 in the figure) when viewed in the thickness direction so that, “the reliability of the semiconductor device can be improved,” ([0010]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Jeun with the metal layer of Danno to improve reliability.
With regard to claim 15, Jeun teaches most of the limitations of the claim, as set forth above with regard to claim 1.
Jeun does not explicitly teach a plurality of second leads, each of which has a terminal portion that protrudes from the sealing resin, wherein the terminal portion is arranged along the first direction.
Danno teaches, in Figs 4-6, a plurality of second leads (LD), each of which has a terminal portion that protrudes from the sealing resin (MR), wherein the terminal portion is arranged along the first direction so that, “the reliability of the semiconductor device can be improved,” ([0010]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Jeun with the lead geometry of Danno to improve reliability.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeun et al. (US 7449774).
With regard to claims 13 and 14, Jeun teach(es) most aspects of the instant invention (see above with regard to claim 3). However, Jeun does not explicitly teach an area of the first main surface is substantially the same as an area of the second main surface or that an area of the second main surface is half or less of an area of the first main surface. Nonetheless, the skilled artisan would know too that main surface areas would impact the suitability for desired circuit function (column 4, lines 25-30).
The specific claimed area, absent any criticality, is only considered to be the “optimum” area ratio disclosed by Jeun that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired suitability for desired circuit function, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the area of the first main surface is substantially the same as an area of the second main surface or that an area of the second main surface is half or less of an area of the first main surface is used, as already suggested by Jeun.
Since the applicant has not established the criticality (see next paragraph) of the area ratio stated and since these area ratios are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Jeun.
Please note that the specification contains no disclosure of either the critical nature of the claimed area ratio or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAJ R GUPTA whose telephone number is (571)270-5707. The examiner can normally be reached 9:30AM-4PM, 8PM-10PM.
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/RAJ R GUPTA/
Primary Examiner, Art Unit 2893