DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicants’ submission filed on 2 MAR 2026 has been entered.
Response To Final Office Action
The 28 JAN 2026 amendments to claims 1, 18, and 20 have been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2 MAR 2026 follows provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
New Grounds of Rejection
New grounds of rejection, prior art reference Chen et al. (US 20200006309) and Summerfelt et al. (US 20200203290), appear below.
Claim Rejections - 35 USC § 102
See previous Office action for a quotation of 35 U.S.C. 102.
Claims 1, 4, 5, 7, and 10-25, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20200006309; below, “Chen” – 2 MAR 2026 IDS noted reference).
RE 1, Chen, in FIGS. 1-22 and related text, e.g., paragraphs [0001] to [0068], discloses a packaged integrated circuit (IC), comprising:
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a semiconductor substrate having opposing first (touches 54) and second (interfaces 36A) surfaces (Giving the not-in-specification terms “first surface” and “second surface” their broadest reasonable interpretation (BRI) consistent with the specification, the noted top surface and bottom surface satisfy these elements because the top surface opposes the bottom surface. MPEP §§ 2111 and 2131.), the semiconductor substrate having a first portion (42A), a second portion (42B), and a through trench (46) between the first (42A) and second (42B) portions and extending from the first surface (top) to the second (bottom) surface of the semiconductor substrate, the through trench (46) including a dielectric material (56) that electrically isolates the first portion (42A) and the second portion (42B) of the semiconductor substrate;
a dielectric layer (52A, 52B) on the second (bottom) surface;
a metallization structure (e.g., 142 – MPEP §§ 2111 and 2131.) over the first (top) surface (FIG. 21); and
a dielectric structure (152 – MPEP §§ 2111 and 2131.) covering the metallization structure (142) and the through trench (46).
Thus, Chen anticipates this claim.
RE 4, Chen discloses the packaged IC of claim 1, wherein the first portion (42A, e.g., [0023]) includes a first device coupled to the metallization structure and configurable to receive a first voltage, the second potion (42B, e.g., [0023]) includes a second device coupled to the metallization structure (142) and configurable to receive a second voltage, and the first voltage and the second voltage have a difference in value of equal to or greater than 50% of a value of a smaller voltage of the first voltage and the second voltage. Regarding the underlined portions of claim 4, the court has held that a recitation of an element “capable of” performing a function is not a positive limitation but only requires the ability to so perform, see In re Schreiber, 44 USPQ2d 1429 (Fed. Cir. 1997).
RE 5, Chen discloses the packaged IC of claim 1, wherein the dielectric material (56) includes a polymer dielectric material, an inorganic dielectric material, or combinations thereof (e.g., [0033]).
RE 7, Chen discloses the packaged IC of claim 5, wherein the inorganic dielectric
material includes silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxynitrocarbide (SiONC), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al2O3 or AlOx), boron nitride (BN), boron carbon nitride (BCN), spin-on-glass (SOG), hydrogen silsesquioxane (HSQ), diamond, or combinations thereof (e.g., [0033]).
RE 10, Chen discloses the packaged IC of claim 1, further comprising a layer (54) on the dielectric material (56) and over the second (bottom) surface.
RE 11, Chen discloses the packaged IC of claim 10, wherein the layer (54) covers (e.g., inverted FIG. 21 – no preferred angle or absolute reference frame claimed) the dielectric material (56).
RE 12, Chen discloses the packaged IC of claim 10, wherein the layer (54) and the dielectric material (56) cover the second (bottom) surface (FIG. 21).
RE 13, Chen discloses the packaged IC of claim 12, wherein the dielectric material (56) covers part of the second (bottom) surface, a part of the layer (54) abuts the second (bottom) surface.
RE 14, Chen discloses the packaged IC of claim 10, wherein the layer (54) includes a metal layer, a second dielectric layer, a bonding layer, a diffusion barrier, a polarization dielectric layer, or combinations thereof (e.g., [0031]).
RE 15, Chen discloses the packaged IC of claim 8, further comprising metal structures (36A) on the second (bottom) surface, in which the dielectric layer (52A, 52B) is between adjacent metal structures (FIG. 21).
RE 16, Chen discloses the packaged IC of claim 10, wherein the through trench (46) is a first through trench, the dielectric material (56) is a first dielectric material, and the layer (54) includes a thermal conductive layer (conductivity spectrum/continuum)) having a second through trench (flanking 42A, 42B) connected with the first through trench (46), the second through trench (see FIG. 2) including a second dielectric material (portion of 56).
RE 17, Chen discloses the packaged IC of claim 16, wherein the dielectric layer (52A, 52B) is a first dielectric layer, and the thermal conductive layer (conductivity spectrum/continuum) includes a second dielectric layer, a metal layer, a diffusion barrier, a polarization dielectric layer, or combinations thereof ([0031]).
RE 18, Chen, in FIGS. 1-22 and related text, e.g., paragraphs [0001] to [0068], discloses a packaged IC, comprising:
a semiconductor substrate having opposing first (touches 54) and second (interfaces 36A) surfaces (Giving the not-in-specification terms “first surface” and “second surface” their BRI, the noted top surface and bottom surface satisfy these elements because the top surface opposes the bottom surface. MPEP §§ 2111 and 2131.), the semiconductor substrate having a first portion (42A) and a second portion (42B), and a through trench (46. Giving the not-in-specification term “through trench” its BRI, 46 satisfies this element because 46 passes vertically between 42A and 42B. MPEP §§ 2111 and 2131.) between the first (42A) and second (42B) portions and extending from the first surface (top) to the second (bottom) surface of the semiconductor substrate, the through trench (46) including a dielectric material (56) that electrically isolates the first portion (42A) and the second portion (42B) of the semiconductor substrate;
a metallization structure (e.g., 142. Giving the not-in-specification term “metallization structure” its BRI, 142 satisfies this element because 142 includes a metal. MPEP §§ 2111 and 2131.) over the first (top) surface; and
a structure (150) on the second (bottom) surface and covering the through trench (46).
Thus, Chen anticipates this claim.
RE 19, Chen discloses the packaged IC of claim 18, wherein the through trench (46) is a first through trench, the semiconductor substrate includes a second through trench (flanking 42A, 42B – MPEP §§ 2111 and 2131 and FIG. 2.) including the dielectric material (56), and the structure (150) includes a first dielectric portion (middle 152) covering the first through trench (46), a second dielectric portion (edge 152) covering the second through trench (flanking 46, FIG. 2), and a metal portion (154) laterally between the first and second dielectric portions; and
wherein the packaged IC includes: a package substrate (20), and a die attach layer (34) coupled between the metal portion (154) and the package substrate (20).
RE 20, Chen, in FIGS. 1-22 and related text, e.g., paragraphs [0001] to [0068], discloses a packaged IC, comprising:
a semiconductor substrate having opposing first (touches 54) and second (interfaces 36A) surfaces (MPEP §§ 2111 and 2131.), the semiconductor substrate having a first portion (42A) and a second portion (42B), and a through trench (46) laterally between the first (42A) and second (42B) portions and extending from the first (top) surface to the second (bottom) surface of the semiconductor substrate, the through trench (46) including a dielectric material (56) that electrically isolates the first portion (42A) and the second portion (42B) of the semiconductor substrate;
a metallization structure (e.g., 142. MPEP §§ 2111 and 2131.) and contact pads on the first (top) surface (metal pads in RDLs 154);
a package substrate (20);
metal interconnects (132) vertically between the contact pads and the package substrate (20); and
a layer (34) on the second (bottom) surface and covering the through trench (46) and the dielectric material (56).
Thus, Chen anticipates this claim.
RE 21, Chen discloses the packaged IC of claim 20, wherein the layer (34) includes a dielectric layer (e.g., [0020]).
RE 22, Chen discloses the packaged IC of claim 19, wherein the structure (150) includes a first layer (same-plane atoms – MPEP §§ 2111 and 2131.) covering two opposing lateral sides and a top side of the first dielectric portion (middle 152), and a second layer (same-plane atoms) covering two opposing lateral sides and a top side of the second dielectric portion (edge 152).
RE 23, Chen discloses the packaged IC of claim 1, wherein the through trench (46) is a first through trench, the semiconductor substrate includes a second through trench (flanking 42A, 42B – FIG. 2), and the dielectric layer (34) includes a first portion covering the first through trench (46) and a second portion covering the second through trench (flanking 42A, 42B), the second portion being spaced from the first portion (FIG. 21).
RE 24, Chen discloses the packaged IC of claim 1, further comprising:
metal pads (metal pads in RDLs 154) on the metallization structure (142);
a package substrate (20); and
metal interconnects (132) coupled between the metal pads (metal pads in RDLs 154) and the package substrate (20).
RE 25, Chen discloses the packaged IC of claim 1, further comprising a package substrate (20) and a die attach layer (e.g., 34) between the dielectric layer (52A, 52B) and the package substrate (20).
Claim Rejections - 35 USC § 103
See previous Office action for a quotation of 35 U.S.C. 103.
Claims 2, 8, and 9 are rejected under 35 U.S.C. 103 as obvious over Chen. At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known device” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G).
RE 2, Chen is silent regarding the packaged IC of claim 1, wherein the dielectric material (56) in the through trench has an aspect ratio of 1:10 to 1:2. However, the claim range of 1:10 to 1:2 is considered to be an obvious matter of finding an optimum workable range for some chosen design requirement utilizing the disclosure of Chen. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955). Finally, any difference in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co. Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
RE 8, Chen is silent regarding the packaged IC of claim 1, wherein the dielectric material (56) extends out of the through trench (46) and joins the dielectric layer (52A, 52B). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify the device of Chen wherein the dielectric material extends out of the through trench and joins the dielectric layer, as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
RE 9, Chen discloses the packaged IC of claim 1, wherein the through trench (46) is a first through trench, the dielectric material (56) is a first dielectric material ([0033]), and the packaged IC includes a second through trench (flanking 42A, 42B) through the dielectric material (56) and connected with the first through trench (46), the second through trench including a second dielectric material (see below for: having an aspect ratio of equal to or greater than 1:10). The claim range of equal to or greater than 1:10 is considered to be an obvious matter of finding an optimum workable range … utilizing the disclosure of Chen. Furthermore, it has been held that where the general conditions of a claim are disclosed …, discovering the optimum or workable ranges involves only routine skill …. In re Aller, 105 USPQ 233 (CCPA 1955). Finally, any difference in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co. Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Claim 3 is rejected under 35 U.S.C. 103 as obvious over Chen with evidence from and/or in view of Lin et al. (US 20210013300; below, “Lin” – previously cited). MPEP § 2143(A)-(G).
RE 3, Chen discloses the packaged IC of claim 1, wherein the dielectric material (56) covers side surfaces of the through trench. Chen is silent regarding a gap in the through trench.
Lin, in Fig. 6 and related text, teaches a dielectric material covers side surfaces of a trench (270) and forms a gap (290) in the trench. (e.g., [0035], Fig. 6).
Chen and Lin are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify Chen as taught by Lin. This is because: 1. air has a low dielectric constant and the presence of one or more air gaps could improve dielectric properties (Lin [0035]); and 2. all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
Claim 6 is rejected under 35 U.S.C. 103 as obvious over Chen with evidence from and/or in view of Summerfelt et al. (US 20200203290; below, “Summerfelt” – 18 SEP 2025 IDS noted reference). MPEP § 2143(A)-(G).
RE 6, Chen is silent regarding the packaged IC of claim 5, wherein the polymer dielectric material includes parylene-F, parylene-HTC, parylene-AF4, parylene C, parylene D, polytetrafluoroethylene (PTFE), polyimide, poly(p-phenylene-2,6-benzobisoxazole) (PBO), benzocyclobutene (BCB), Teflon, or combinations thereof.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to use the claimed materials since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960). As evidence, see Summerfelt’s [0021].
Claims 1, 2, 4-25 are rejected under 35 U.S.C. 103 as obvious over PODDAR et al. (US 20190206741; below, “PODDAR” – previously cited) with evidence from and/or in view of Summerfelt. MPEP § 2143(A)-(G).
RE 1, PODDAR, in FIG. 7 and related text, e.g., paragraphs [0016] to [0035], discloses a packaged integrated circuit (IC) (700), comprising:
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a semiconductor substrate (701, 730) having opposing first (top surface with bond pads) and second (interfaces 702) surfaces (Giving the not-in-specification terms “first surface” and “second surface” their broadest reasonable interpretation (BRI) consistent with the specification, 701’s top surface and bottom surface satisfy these elements because the top surface opposes the bottom surface. MPEP §§ 2111 and 2131.), the semiconductor substrate (701, 730) having a first portion (710), a second portion (720), and a through trench (750) between the first (710) and second (720) portions and extending from the first surface (top) to the second (bottom) surface of the semiconductor substrate, the through trench (750) including a dielectric material (e.g., [0032]) that (see Summerfelt for: electrically isolates) the first portion (710) and the second portion (720) of the semiconductor substrate (701, 730);
a dielectric layer (740 lower – MPEP §§ 2111 and 2131.) on the second (bottom) surface;
a metallization structure (e.g., 722 – MPEP §§ 2111 and 2131.) over the first (top) surface (FIG. 7, [0033]); and
a dielectric structure (740 upper – MPEP §§ 2111 and 2131.) covering the metallization structure (722) and the through trench (750).
PODDAR discloses using a die attach layer to attach die to a lead frame (e.g., [0032], [0034]). PODDAR is silent regarding the die attach layer electrically isolating the first portion (710) and the second portion (720) of the semiconductor substrate (701, 730).
Summerfelt, in Abstract, FIGS. 1A to 8K, paragraphs [0001] to [0086], e.g., [0018], [0031], [0035], teaches a dielectric material (e.g., 109, 809) that electrically isolates.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify the device of PODDAR as taught by Summerfelt. This is because: 1. die attach polymers are less expensive than other die attach layers, e.g., gold-silicon eutectic alloys; and 2. all the claimed elements were known in the prior art and one skilled … could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
RE 2, modified PODDAR is silent regarding the packaged IC of claim 1, wherein the dielectric material in the through trench has an aspect ratio of 1:10 to 1:2. However, the claim range of 1:10 to 1:2 is considered to be an obvious matter of finding an optimum workable range for some chosen design requirement utilizing the disclosure of PODDAR. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955). Finally, any difference in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co. Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
RE 4, modified PODDAR discloses the packaged IC of claim 1, wherein the first portion (710, e.g., FET operating in a voltage-controlled resistor mode) includes a first device coupled to the metallization structure and configurable to receive a first voltage, the second potion (720, e.g., FET operating in a voltage-controlled resistor mode) includes a second device coupled to the metallization structure (722) and configurable to receive a second voltage, and the first voltage and the second voltage have a difference in value of equal to or greater than 50% of a value of a smaller voltage of the first voltage and the second voltage. Regarding the underlined portions of claim 4, the court has held that a recitation of an element “capable of” performing a function is not a positive limitation but only requires the ability to so perform, see In re Schreiber, 44 USPQ2d 1429 (Fed. Cir. 1997).
RE 5, modified PODDAR discloses the packaged IC of claim 1, wherein the dielectric material includes a polymer dielectric material (Summerfelt’s [0033]), an inorganic dielectric material, or combinations thereof (e.g., [0034]).
RE 6, modified PODDAR discloses the packaged IC of claim 5, wherein the polymer dielectric material includes parylene-F, parylene-HTC, parylene-AF4, parylene C, parylene D, polytetrafluoroethylene (PTFE), polyimide, poly(p-phenylene-2,6-benzobisoxazole) (PBO), benzocyclobutene (BCB), Teflon, or combinations thereof (Summerfelt’s [0021]).
RE 7, modified PODDAR discloses the packaged IC of claim 5, wherein the inorganic dielectric material includes silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon oxynitrocarbide (SiONC), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al2O3 or AlOx), boron nitride (BN), boron carbon nitride (BCN), spin-on-glass (SOG), hydrogen silsesquioxane (HSQ), diamond, or combinations thereof (e.g., PODDAR’s [0026] – “ceramic slurry”; Summerfelt’s [0021]).
RE 8, modified PODDAR discloses the packaged IC of claim 1, wherein the dielectric material extends out of the through trench (750) and joins the dielectric layer (740 lower). See PODDAR’s [0034] (dielectric material formation dependent) and Summerfelt’s 109, 809.
RE 9, modified PODDAR discloses the packaged IC of claim 1, wherein the through trench (750) is a first through trench, the dielectric material is a first dielectric material ([0034]), and the packaged IC includes a second through trench (flanked by 730 and 701) through the dielectric material ([0034]) and connected with the first through trench (750), the second through trench (flanked by 730 and 701) including a second dielectric material (see below for: having an aspect ratio of equal to or greater than 1:10). The claim range of equal to or greater than 1:10 is considered to be an obvious matter of finding an optimum workable range … utilizing the disclosure of PODDAR. Furthermore, it has been held that where the general conditions of a claim are disclosed …, discovering the optimum or workable ranges involves only routine skill …. In re Aller, 105 USPQ 233 (CCPA 1955). Finally, any difference in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co. Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
RE 10, modified PODDAR discloses the packaged IC of claim 1, further comprising a layer (740: layer have a same atomic plane) on the dielectric material and over the second (bottom) surface.
RE 11, modified PODDAR discloses the packaged IC of claim 10, wherein the layer (740: layer have a same atomic plane – MPEP §§ 2111 and 2131.) covers the dielectric material (FIG. 7).
RE 12, modified PODDAR discloses the packaged IC of claim 10, wherein the layer (740: layer have a same atomic plane) and the dielectric material cover the second (bottom) surface (Summerfelt’s 109, 809).
RE 13, modified PODDAR discloses the packaged IC of claim 12, wherein the dielectric material covers (depending on dielectric material formation – [0034]) part of the second (bottom) surface, a part of the layer (740: layer have a same atomic plane – MPEP §§ 2111 and 2131.) abuts the second (bottom) surface (Summerfelt’s 109, 809).
RE 14, modified PODDAR discloses the packaged IC of claim 10, wherein the layer (740: layer have a same atomic plane – MPEP §§ 2111 and 2131.) includes a metal layer, a second dielectric layer, a bonding layer, a diffusion barrier, a polarization dielectric layer, or combinations thereof ([0034]).
RE 15, modified PODDAR discloses the packaged IC of claim 8, further comprising metal structures (702) on the second (bottom) surface, in which the dielectric layer is between adjacent metal structures (702 – FIG. 7).
RE 16, modified PODDAR discloses the packaged IC of claim 10, wherein the through trench (750) is a first through trench, the dielectric material is a first dielectric material ([0034]), and the layer (740: layer have a same atomic plane) includes a thermal conductive layer (conductivity spectrum/continuum)) having a second through trench (flanked by 730 and 701) connected with the first through trench (750), the second through trench (flanked by 730 and 701) including a second dielectric material (portion of 740 between 730 and 701).
RE 17, modified PODDAR discloses the packaged IC of claim 16, wherein the dielectric layer (740 lower – MPEP §§ 2111 and 2131.) is a first dielectric layer, and the thermal conductive layer (conductivity spectrum/continuum) includes a second dielectric layer (portion of 740 between 730 and 701), a metal layer, a diffusion barrier, a polarization dielectric layer, or combinations thereof ([0034]).
RE 18, PODDAR, in FIG. 7 and related text, e.g., paragraphs [0016] to [0035], discloses a packaged IC (700), comprising:
a semiconductor substrate (701, 730) having opposing first (top surface with bond pads) and second (interfaces 702) surfaces (Giving the not-in-specification terms “first surface” and “second surface” their BRI, 701’s top surface and bottom surface satisfy these elements because the top surface opposes the bottom surface. MPEP §§ 2111 and 2131.), the semiconductor substrate (701, 730) having a first portion (710) and a second portion (720), and a through trench (750. Giving the not-in-specification term “through trench” its BRI, 750 satisfies this element because 750 passes vertically between 710 and 720. MPEP §§ 2111 and 2131.) between the first (710) and second (720) portions and extending from the first surface (top) to the second (bottom) surface of the semiconductor substrate, the through trench (750) including a dielectric material ([0032]) that (see Summerfelt for: electrically isolates) the first portion (710) and the second portion (720) of the semiconductor substrate (701, 730);
a metallization structure (e.g., 721. Giving the not-in-specification term “metallization structure” its BRI, wire bond 721 satisfies this element because 721 includes a metal. MPEP §§ 2111 and 2131.) over the first (top) surface; and
a structure (740) on the second (bottom) surface and covering the through trench (750).
PODDAR discloses using a die attach layer to attach die to a lead frame (e.g.,
[0032], [0034]). PODDAR is silent regarding the die attach layer electrically isolating the first portion (710) and the second portion (720) of the semiconductor substrate (701, 730).
Summerfelt, in Abstract, FIGS. 1A to 8K, paragraphs [0001] to [0086], e.g., [0018], [0031], [0035], teaches a dielectric material (e.g., 109, 809) that electrically isolates.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify the device of PODDAR as taught by Summerfelt. This is because: 1. die attach polymers provide good thermal performance, i.e., polymer efficiently transfers heat from die to package; and 2. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 19, modified PODDAR discloses the packaged IC of claim 18, wherein the through trench (750) is a first through trench, the semiconductor substrate (701, 730) includes a second through trench (flanked by 730 and 701 – MPEP §§ 2111 and 2131.) including the dielectric material ([0034]), and the structure (740) includes a first dielectric portion (underneath 710 and 720) covering the first through trench (750), a second dielectric portion (underneath 722) covering the second through trench (flanked by 730 and 701), and a metal portion (722) laterally between the first and second dielectric portions; and
wherein the packaged IC includes: a package substrate (703, 731, 732), and a
die attach layer ([0032]) coupled between the metal portion (722) and the package
substrate (703, 731, 732).
RE 20, PODDAR, in FIG. 7 and related text, e.g., paragraphs [0016] to [0035], discloses a packaged IC (700), comprising:
a semiconductor substrate (701, 730) having opposing first (top surface with bond pads) and second (interfaces 702) surfaces (MPEP §§ 2111 and 2131.), the semiconductor substrate (701, 730) having a first portion (710) and a second portion (720), and a through trench (750) laterally between the first (710) and second (720) portions and extending from the first (top) surface to the second (bottom) surface of the semiconductor substrate, the through trench (750) including a dielectric material ([0032]) that (see Summerfelt for: electrically isolates) the first portion (710) and the second portion (720) of the semiconductor substrate (701, 730);
a metallization structure (e.g., 722. MPEP §§ 2111 and 2131.) and contact pads on the first (top) surface (FIG. 7, [0033]);
a package substrate (703, 731, 732);
metal interconnects (721, 723) vertically between the contact pads and the package substrate (703, 731, 732); and
a layer (740 – MPEP §§ 2111 and 2131.) on the second (bottom) surface and covering the through trench (750) and the dielectric material.
PODDAR discloses using a die attach layer to attach die to a lead frame (e.g., [0032], [0034]). PODDAR is silent regarding the die attach layer electrically isolating the first portion (710) and the second portion (720) of the semiconductor substrate (701, 730).
Summerfelt, in Abstract, FIGS. 1A to 8K, paragraphs [0001] to [0086], e.g.,
[0018], [0031], [0035], teaches a dielectric material (e.g., 109, 809) that electrically isolates.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify the device of PODDAR as taught by Summerfelt. This is because: 1. die attach polymers are cost-effective and provide efficient thermal performance; and 2. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 21, modified PODDAR discloses the packaged IC of claim 20, wherein the layer (740) includes a dielectric layer ([0034]).
RE 22, modified PODDAR discloses the packaged IC of claim 19, wherein the structure (740) includes a first layer (atoms surrounding 710 and 720 – MPEP §§ 2111 and 2131.) covering two opposing lateral sides and a top side of the first dielectric portion (underneath 710 and 720), and a second layer (atoms surrounding 722 – MPEP §§ 2111 and 2131.) covering two opposing lateral sides and a top side of the second dielectric portion (underneath 722).
RE 23, modified PODDAR discloses the packaged IC of claim 1, wherein the through trench (750) is a first through trench, the semiconductor substrate (701, 730) includes a second through trench (flanked by 730 and 701), and the dielectric layer includes a first portion covering the first through trench (750) and a second portion covering the second through trench (flanked by 730 and 701), the second portion being spaced from the first portion (FIG. 7).
RE 24, modified PODDAR discloses the packaged IC of claim 1, further
comprising:
metal pads (FIG. 7, [0033]) on the metallization structure (e.g., 722);
a package substrate (703, 731, 732); and
metal interconnects (721, 723) coupled between the metal pads and the package substrate (703, 731, 732).
RE 25, modified PODDAR discloses the packaged IC of claim 1, further comprising a package substrate (703, 731, 732) and a die attach layer ([0032]) between the dielectric layer (740 lower) and the package substrate (703, 731, 732).
Claim 3 is rejected under 35 U.S.C. 103 as obvious over PODDAR with evidence from and/or in view of Summerfelt with further evidence from and/or in further view of Lin. MPEP § 2143(A)-(G).
RE 3, modified PODDAR is silent regarding the packaged IC of claim 1, wherein the dielectric material covers side surfaces of the through trench and forms a gap in the through trench.
Lin, in Fig. 6 and related text, teaches a dielectric material covers side surfaces of a trench (270) and forms a gap (290) in the trench. (e.g., [0035], Fig. 6).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify PODDAR with evidence from and/or in view of Summerfelt as taught by Lin. This is because: 1. air has a low dielectric constant and the presence of one or more air gaps could improve dielectric properties (Lin [0035]); and 2. all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
Claims 1-25 are rejected.
Response to Applicant’s Amendments and/or Arguments
Applicants’ rebuttal arguments filed 28 JAN 2025 (REM pages 7 to 10) have been fully considered, but are found to be unpersuasive in light of the arguments and positions outlined supra. Additionally, the new ground of rejection was necessary due to the applicant’s amendments. Applicant’s arguments regarding patentability have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/WALTER H SWANSON/Primary Examiner, Art Unit 2815