DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Invention I, identified as encompassing claims 1-10, 15- 17, and 20 is acknowledged.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 3 and 5-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
5. Claim 3 recites “the semiconductor layer includes a third portion between the first portion and the second portion in the first direction, the third portion having a fifth width in the second direction that is greater than the second width and the third width”
The current claim depends ultimately on claims 1 which requires “the second pitch is greater than the first pitch and the third pitch”.
It is indefinite as to how the cited limitations are simultaneously met. See Applicant’s elected Invention I represented in Fig. 22 the width of element W120J is greater than a width above or below for the semiconductor layer; however, this would mean the first portion is above the element 151 and the second portion is below the element 151 in which case the second pitch would not be greater than the first pitch and the third pitch.
6. Claim 5 recites “wherein the semiconductor layer has a third portion between the first and second portions in the first direction, the third portion has a width in the second direction that is greater than the maximum widths of the first and second portions in the second direction”
The current claim depends ultimately on claims 1 which requires “the second pitch is greater than the first pitch and the third pitch”.
It is indefinite as to how the cited limitations are simultaneously met. See Applicant’s elected Invention I represented in Fig. 22 the width of element W120J is greater than a width above or below for the semiconductor layer; however, this would mean the first portion is above the element 151 and the second portion is below the element 151 in which case the second pitch would not be greater than the first pitch and the third pitch.
All claims depending on the current claim incorporate the same issues.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 1, 9-10, 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US 2020/0279859 A1), hereinafter as U1, in view of Koval et al. (US 2017/0186765 A1), hereinafter as K1
8. Regarding Claim 1, U1 discloses a semiconductor memory device (Figs. 1-24C, in particular Figs. 2A, 3, 4A and [0038] “semiconductor memory device 1”), comprising:
a plurality of first conductive layers (plurality of first upper portion elements FL, see [0051] “first layers FL are constituted by conducting layers”) stacked on a substrate along a first direction (vertical z-direction perpendicular to an upper surface of the substrate in a cross sectional view) at a first pitch (see Fig. 3 first vertical pitch);
a plurality of second conductive layers (plurality of second portion of elements FL below the plurality of first conductive layers) stacked on the substrate along the first direction at a second pitch (see Fig. 3 second vertical pitch), the plurality of second conductive layers being between the substrate and the plurality of first conductive layers in the first direction (see Fig. 3);
a plurality of third conductive layers (plurality of third portion of elements FL below the plurality of second conductive layers) stacked on the substrate along the first direction at a third pitch, the plurality of third conductive layers being between the substrate and the plurality of second conductive layers in the first direction (see Fig. 3); and
a semiconductor layer (layer of element CN, see [0053] “channel layer CN is an amorphous silicon layer, a polysilicon layer or the like” ) extending in the first direction through the first conductive layers, the second conductive layers, and the third conductive layers (see Fig. 3), wherein
the semiconductor layer has a first portion (first portion selected at a height of the first and second conductive layers) facing the first conductive layers and the second conductive layers and a second portion facing the third conductive layers (second portion selected at a height of the third conductive layers).
U1 does not disclose the second pitch is greater than the first pitch and the third pitch.
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K1 discloses (see “Labeled Fig. 2a” above) the second pitch is greater than the first pitch and the third pitch (see “Labeled Fig. 2a” above, the labeled element “Second Pitch” is greater than the labeled “First Pitch” and “Third Pitch”).
The increasing pitch from top to bottom for each storage cell as taught by K1 is incorporated as an increasing pitch from top to bottom for each storage cell of U1 (see U1 “Labeled Fig. 3” below).
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It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with U1 because the combination for accommodation of lower structure storage cell reliability in cell stacks (see K1 [0013-0014]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known thicknesses and pitch of an alternating conductor insulator stack of a memory cell for another to obtain predictable results in a similar memory device for which the alternative options are provided as selectable (see K1 Figs. 4a-f).
9. Regarding Claim 9, U1, K1 disclose the semiconductor memory device according to claim 1, wherein
each of the first conductive layers has a first thickness in the first direction (see K1 “Labeled Fig. 2a” and U1 “Labeled Fig. 3”), each of the second conductive layers has a second thickness in the first direction (see K1 “Labeled Fig. 2a” and U1 “Labeled Fig. 3”), and
the second thickness is greater than the first thickness (see K1 “Labeled Fig. 2a” and U1 “Labeled Fig. 3”),.
10. Regarding Claim 10, U1, K1 disclose the semiconductor memory device according to claim 9, wherein
each of the third conductive layers has a third thickness (see K1 “Labeled Fig. 2a” and U1 “Labeled Fig. 3”) in the first direction, and
the second thickness is greater than the third thickness (see K1 “Labeled Fig. 2a” and U1 “Labeled Fig. 3”).
11. Regarding Claim 16, U1 discloses a semiconductor memory device (Figs. 1-24C, in particular Figs. 2A, 3, 4A and [0038] “semiconductor memory device 1”), comprising:
a plurality of first conductive layers (plurality of first upper portion elements FL, see [0051] “first layers FL are constituted by conducting layers”) stacked on a substrate along a first direction (vertical z-direction perpendicular to an upper surface of the substrate in a cross sectional view) at a first pitch (see Fig. 3 first vertical pitch);
a plurality of second conductive layers (plurality of second portion of elements FL below the plurality of first conductive layers) stacked on the substrate along the first direction at a second pitch (see Fig. 3 second vertical pitch), the plurality of second conductive layers being between the substrate and the plurality of first conductive layers in the first direction (see Fig. 3);
a plurality of third conductive layers (plurality of third portion of elements FL below the plurality of second conductive layers) stacked on the substrate along the first direction, the plurality of third conductive layers being between the substrate and the plurality of second conductive layers in the first direction (see Fig. 3); and
a memory pillar (pillar of element PL, see [0053] “pillars PL each include a memory layer ME and a channel layer CN” ) extending in the first direction through the first conductive layers, the second conductive layers and the third conductive layers, wherein
the memory pillar (layer of element CN, see [0053] “channel layer CN is an amorphous silicon layer, a polysilicon layer or the like” ) has a first portion (first portion selected at a height of the first and second conductive layers) facing the first conductive layers and the second conductive layers, a second portion facing the third conductive layers (second portion selected at a height of the third conductive layers), and a joint portion (joint portion selected at a height of between the first and second portions) between the first and second portions in the first direction,
the first portion of the memory pillar narrows in width from a first end that is farthest from the joint portion in the first direction to a second end that is nearest the joint portion in the first direction (see Fig. 3 the width of the element PL of the first portion, selected to be above element Bi, narrows in width from a topmost surface towards the element Bi).
U1 does not explicitly disclose the second pitch is different from the first pitch.
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K1 discloses (see “3rd Labeled Fig. 2a” above) the second pitch is different from the first pitch (see “3rd Labeled Fig. 2a” above, the labeled element “Second Pitch” is different from the labeled “First Pitch” and “Third Pitch”).
The increasing pitch from top to bottom for each storage cell as taught by K1 is incorporated as an increasing pitch from top to bottom for each storage cell of U1 (see U1 “3rd Labeled Fig. 3” below).
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It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with U1 because the combination for accommodation of lower structure storage cell reliability in cell stacks (see K1 [0013-0014]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known thicknesses and pitch of an alternating conductor insulator stack of a memory cell for another to obtain predictable results in a similar memory device for which the alternative options are provided as selectable (see K1 Figs. 4a-f).
12. Regarding Claim 17, U1, K1 disclose the semiconductor memory device according to claim 16, wherein
the second portion of the memory pillar narrows in width from a third end (upper end of the second portion) nearest the joint portion in the first direction to a fourth end farthest from the joint portion (lower end of the second portion) in the first direction (see U1 “3rd Labeled Fig. 3” above), and
the plurality of third conductive layers are stacked at a third pitch that is different from the second pitch (see K1 “3rd Labeled Fig. 2a” and U1 “3rd Labeled Fig. 3” above).
13. Regarding Claim 20, U1, K1 disclose the semiconductor memory device according to claim 16, wherein
each of the first conductive layers has a first thickness in the first direction,
each of the second conductive layers has a second thickness in the first direction, and
the second thickness is greater than the first thickness
(see U1 Fig. 2A and “3rd Labeled Fig. 3” above).
14. Claims 1 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US 2020/0279859 A1), hereinafter as U1, in view of Koval et al. (US 2017/0186765 A1), hereinafter as K1
15. Regarding Claim 1, U1 discloses a semiconductor memory device (Figs. 1-24C, in particular Figs. 2A, 3, 4A and [0038] “semiconductor memory device 1”), comprising:
a plurality of first conductive layers (plurality of first upper portion elements FL, see [0051] “first layers FL are constituted by conducting layers”) stacked on a substrate along a first direction (vertical z-direction perpendicular to an upper surface of the substrate in a cross sectional view) at a first pitch (see Fig. 3 first vertical pitch);
a plurality of second conductive layers (plurality of second portion of elements FL below the plurality of first conductive layers) stacked on the substrate along the first direction at a second pitch (see Fig. 3 second vertical pitch), the plurality of second conductive layers being between the substrate and the plurality of first conductive layers in the first direction (see Fig. 3);
a plurality of third conductive layers (plurality of third portion of elements FL below the plurality of second conductive layers) stacked on the substrate along the first direction at a third pitch, the plurality of third conductive layers being between the substrate and the plurality of second conductive layers in the first direction (see Fig. 3); and
a semiconductor layer (layer of element CN, see [0053] “channel layer CN is an amorphous silicon layer, a polysilicon layer or the like” ) extending in the first direction through the first conductive layers, the second conductive layers, and the third conductive layers (see Fig. 3), wherein
the semiconductor layer has a first portion (first portion selected at a height of the first and second conductive layers) facing the first conductive layers and the second conductive layers and a second portion facing the third conductive layers (second portion selected at a height of the third conductive layers).
U1 does not disclose the second pitch is greater than the first pitch and the third pitch.
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K1 discloses (see “2nd Labeled Fig. 2a” above) the second pitch is greater than the first pitch and the third pitch (see “2nd Labeled Fig. 2a” above, the labeled element “Second Pitch” is greater than the labeled “First Pitch” and “Third Pitch”).
The increasing pitch from top to bottom for each storage cell as taught by K1 is incorporated as an increasing pitch from top to bottom for each storage cell of U1 (see U1 “2nd Labeled Fig. 3” below).
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It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with U1 because the combination for accommodation of lower structure storage cell reliability in cell stacks (see K1 [0013-0014]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known thicknesses and pitch of an alternating conductor insulator stack of a memory cell for another to obtain predictable results in a similar memory device for which the alternative options are provided as selectable (see K1 Figs. 4a-f).
16. Regarding Claim 15, U1, K1 disclose the semiconductor memory device according to claim 1, wherein the first pitch is equal to the third pitch (see K1 “2nd Labeled Fig. 2a” above and U1 “2nd Labeled Fig. 3” above).
17. Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US 2020/0279859 A1), hereinafter as U1, in view of Koval et al. (US 2017/0186765 A1), hereinafter as K1, in view of Matsumoto et al. (US 2020/0251490 A1), hereinafter as M1
18. Regarding Claim 2, U1, K1 disclose the semiconductor memory device according to claim 1, (see U1 Fig. 3)
a first end of the first portion (upper end of the first portion) of the semiconductor layer farthest from the substrate in the first direction has a first width in a second direction (second lateral direction in the cross sectional view) intersecting the first direction (see Fig. 3),
a second end of the first portion (lower end of the first portion) of the semiconductor layer nearest the substrate in the first direction has a second width in the second direction (see Fig. 3),
a third end of the second portion (upper end of the second portion) of the semiconductor layer nearest the second conductive layers in the first direction has a third width in the second direction (see Fig. 3),
a fourth end of the second portion (lower end of the second portion) nearest the substrate in the first direction has a fourth width in the second direction (see Fig. 3),
U1, K1 do not disclose the first width is greater than the second width, and the third width is greater the fourth width.
M1 discloses a width of the semiconductor layer decreases from top to bottom corresponding to each of the stacked memory cells (see Fig. 5).
The width decrease of the semiconductor layer as taught by M1 is incorporated as a width decrease of the semiconductor layer of U1,K1, wherein the combination discloses the first width is greater than the second width, and the third width is greater the fourth width.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with U1 because the combination is simple substitution of one known semiconductor layer sidewall shape for another in a similar device to obtain predictable results (see U1 the semiconductor layer has straight sidewalls but the pillar has slanted sidewalls, and see M1 both the semiconductor layer and the pillar has slanted sidewalls).
19. Regarding Claim 4, U1, K1 disclose the semiconductor memory device according to claim 1,
U1, K1 do not explicitly disclose the first portion of the semiconductor layer tapers in width in a second direction substantially parallel as distance from the substrate decreases along the first direction, and the second portion of the semiconductor layers tapers in width in the second direction as distance from the substrate decreases along the first direction.
M1 discloses a width of the semiconductor layer decreases from top to bottom corresponding to each of the stacked memory cells (see Fig. 5).
The width decrease of the semiconductor layer as taught by M1 is incorporated as a width decrease of the semiconductor layer of U1,K1, wherein the combination discloses the first portion of the semiconductor layer tapers in width in a second direction substantially parallel as distance from the substrate decreases along the first direction, and the second portion of the semiconductor layers tapers in width in the second direction as distance from the substrate decreases along the first direction.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with U1 because the combination is simple substitution of one known semiconductor layer sidewall shape for another in a similar device to obtain predictable results (see U1 the semiconductor layer has straight sidewalls but the pillar has slanted sidewalls, and see M1 both the semiconductor layer and the pillar has slanted sidewalls).
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818