DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 7-8, 11-13, 15-21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Foster (Patent No. US 7,245,007 B1) in view of Im (PG Pub. No. US 2015/0357269 A1).
Regarding claim 1, Foster teaches a method, comprising:
coupling conductive leads (col. 5 line 46: 16) and a conductive pad (col. 5 line 41: die pad 18) of an assembly (2) to a dielectric material of the assembly (fig. 1B & col. 6 lines 14-17: 16 and 18 coupled to molded dielectric 14/20), the conductive pad extending through a thickness of the dielectric material and providing a first external surface of the assembly (fig. 1C: 18 extends through at least a portion of the thickness of 14/20 to provide at least one external surface), each of the conductive leads including a first surface and a second surface (fig. 1B: 16 includes at least top and bottom surfaces), the second surface providing a second external surface of the assembly (fig. 1C: top surface 46 and/or bottom surface 50 of 16 provide external surfaces); and
coupling terminals of a packaged semiconductor device of the assembly (col. 13 lines 2-3 & fig. 9B: unlabeled leads of semiconductor package 58) to the first surfaces of at least some of the conductive leads via a conductive material (col. 6 lines 6-10 & fig. 9A: leads of package 58 coupled to surface 50 via unlabeled conductive material).
Foster further teaches the assembly comprises the conductive pad is configured to dissipate heat (col. 5 lines 60-63: 18 configured to dissipate heat).
Foster does not teach the method comprises coupling a thermal pad of the packaged semiconductor device to a third surface of the conductive pad opposing the first external surface.
Im teaches a method including coupling a thermal pad (¶ 0058: 201v) of a packaged semiconductor device (fig. 1B: upper package 200, similar to 58 of Foster) to an exposed surface of a conductive pad (figs. 7A-7B, 9: 201v coupled to exposed surface of lead plate LP in region R1, similar to 18 of Foster).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Foster to include coupling the conductive pad to a thermal pad of the packaged semiconductor device, as a means to improve the thermal release characteristics of the packaged semiconductor device, improving the reliability of the semiconductor package (Im, ¶ 0112).
Regarding claim 3, Foster in view of Im teaches the method of claim 1, wherein coupling conductive leads to a dielectric material includes attaching leads having a head portion (Foster, col. 6 line 2: leads 16 include elongated portions 46) extending into the dielectric material (Foster, fig. 1C: 46 extends into 14/20), a foot portion (Foster, col. 6 line 6: leads 16 include bottom portion 50) extending away from the dielectric material and including the second surface (Foster, fig. 1C: 50 extends away from 14/20 to provide an external bottom surface), and a middle portion between and angled from the head and foot portions (Foster, middle portion of 16 between 46 and 50 includes a right angle).
Regarding claims 4-5, Foster in view of Im teaches the method of claim 1, including attaching leads to a dielectric material (Foster, fig. 1C: 16 attached to 14/20).
Foster in view of Im as applied to claim 1 above does not teach the leads are S-shaped or Z-shaped.
However, Foster teaches additional embodiments (figs. 1E-1F, 2D, 4A-4B among others) wherein leads 16 are configured to include S-shaped or Z-shaped portions.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the leads of Foster in view of Im to include S-shapes or Z-shapes, as a means to position exposed portion of leads 16 closer toward the peripheral edge of die pad 18 (Foster, col. 7 lines 10-15), reducing the size of the assembly, and/or providing a surface suitable for a solder connection (Foster, col. 7 lines 22-24).
Furthermore, modifying Foster in view of Im to include the features of “attaching S-shaped leads to the dielectric material” (as recited in claim 4) and/or “attaching S-shaped leads to the dielectric material” (as recited in claim 5) would have involved a mere change in the shape of a component. Absent persuasive evidence that the particular shape of the claimed conductive lead is significant, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 7, Foster in view of Im teaches the method of claim 1, wherein coupling terminals of a packaged semiconductor device to the first surfaces of at least some of the conductive leads via a conductive material includes placing the packaged semiconductor device entirely on the conductive leads and the dielectric material (Foster, fig. 9A: 58 placed entirely on 16 and 14).
Regarding claim 8, Foster in view of Im teaches the method of claim 1, wherein the conductive leads include two opposing sets of conductive leads (Foster, fig. 1A: opposing sets of leads 16), and wherein coupling terminals of a packaged semiconductor device to the first surfaces of at least some of the conductive leads via a conductive material includes placing the packaged semiconductor device between portions of the two opposing sets of conductive leads (Foster, fig. 9A: 58 placed between portions of opposing sets of leads 16).
Regarding claim 11, Foster in view of Im teaches the method of claim 1, wherein the conductive material includes at least one of solder joint or conductive epoxy (Foster, col. 6 lines 6-8: 58 mounted on 16 via solder joint connection 50).
Regarding claim 12, Foster in view of Im teaches the method of claim 1, wherein the dielectric material is a pre-mold dielectric material (Foster, col. 5 line 40: 14 comprises transfer molded epoxy mold compound).
Regarding claim 13, Foster in view of Im teaches the method of claim 1, wherein the dielectric material includes at least one of: plastic, epoxy, or resin (Foster, col. 5 line 44: 14 comprises epoxy).
Regarding claim 15, Foster in view of Im teaches the method of claim 1, wherein the packaged semiconductor device includes a surface mount package (Foster, fig. 9B: 58 mounted on a surface of 2, meeting the broadest reasonable interpretation of “surface mount package”).
Regarding claim 16, Foster teaches an apparatus comprising:
an assembly (fig. 10B) including:
a dielectric material (col. 6 line 15: 14);
conductive leads (col. 5 line 64: 16) coupled to the dielectric material (figs. 1E, 10B: 16 coupled to 18), each of the conductive leads having a first surface and a second surface (fig. 10B: 16 includes top and bottom surfaces), the second surface providing a first external surface of the assembly (figs. 1E: 16 includes top surface external to dielectric 14 and package body 36, and bottom surface 50 external to dielectric 14);
a conductive pad (col. 5 lines 60-63 and col. 9 lines 5-6: pad 18, including thermal and/or electrical conductivity) and coupled to the dielectric material (fig. 1E: 50 coupled to 14), the conductive pad extending through a thickness of the dielectric material and providing a second external surface of the assembly (fig. 1E: 50 extends through 14 to provide a surface external to 14); and
a packaged semiconductor device (col. 12 lines 66-67) having terminals (col. 13, lines 2-3: 58 includes non-labeled leads), the terminals being mounted on the first surfaces of at least some of the conductive leads via a conductive material (col. 13 lines 2-4 & fig. 10B: leads of 58 mounted on surfaces 50 of 16).
Foster does not teach the packaged semiconductor device comprises a thermal pad, and the thermal pad being mounted on a third surface of the conductive pad opposing the second external surface.
Im teaches a method including coupling a thermal pad (¶ 0058: 201v) of a packaged semiconductor device (fig. 1B: upper package 200, similar to 58 of Foster) to an exposed surface of a conductive pad (figs. 7A-7B, 9: 201v coupled to exposed surface of lead plate LP in region R1, similar to 18 of Foster).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the assembly of Foster to include a thermal pad of the packaged semiconductor device mounted on a surface of the conductive pad, as a means to improve the thermal release characteristics of the packaged semiconductor device, improving the reliability of the semiconductor package (Im, ¶ 0112).
Regarding claim 17, Foster in view of Im teaches the apparatus of claim 16, wherein each of the conductive leads has at least one of:
a C-shape, an S-shape, or a Z-shape (Foster, fig. 1E: 16 includes an S-shape and/or a Z-shape).
Regarding claim 18, Foster in view of Im teaches the apparatus of claim 16, wherein the conductive leads include two opposing sets of conductive leads (Foster, figs. 1A, 1C among others: opposing sets of leads 16), and the packaged semiconductor device is between the two opposing sets of conductive leads (Foster, fig. 10B: 58 arranged between opposing sets of 16).
Regarding claim 19, Foster in view of Im teaches the apparatus of claim 16, wherein the packaged semiconductor device is entirely on the conductive leads and the dielectric material (Foster, fig. 10B: 58 disposed entirely on 16 and 14).
Regarding claim 20, Foster in view of Im teaches the apparatus of claim 16, wherein the packaged semiconductor device includes a surface mount package (Foster, fig. 10B: 58 mounted on a surface of interposer 2, meeting the broadest reasonable interpretation of “surface mount package”).
Regarding claim 21, Foster in view of Im teaches the apparatus of claim 16, wherein the second surface includes a circuit board mounting surface (Foster, fig. 4B: surface of 16 capable of mounting on PCB 28, thereby meeting the broadest reasonable interpretation of “a circuit board mounting surface”).
Regarding claim 23, Foster in view of Im teaches the apparatus of claim 16, wherein the packaged semiconductor device includes a surface mount package (Foster, fig. 10B: 58 mounted on a surface of 2, meeting the broadest reasonable interpretation of “surface mount package”).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Foster in view of Im as applied to claim 1 above, and further in view of Ananiev (PG Pub. No. US 2015/0194374 A1).
Regarding claim 2, Foster in view of Im teaches the method of claim 1, including attaching conductive leads to dielectric material (Foster, figs. 1E, 10B: 16 attached to 14).
Foster in view of Im does not teach wherein coupling conductive leads further comprises attaching C-shaped conductive leads to the dielectric material.
Ananiev teaches a package device (fig. 1) including conductive leads (¶ 0053: 122, similar to 16 of Foster), wherein the conductive leads comprise C-shaped leads (¶ 0055 & fig. 1: 122 comprise C-shape).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the conductive leads of Foster in view of Im with a C-shape, as a means to increase the thermal service life of the electronic device (Ananiev, ¶ 0059).
Furthermore, arriving at the claimed feature of "attaching C-shaped conductive leads" would have involved a mere change in the shape of a component. Absent persuasive evidence that the particular shape of the claimed conductive leads is significant, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Foster in view of Im as applied to claim 1 above, and further in view of Chien (PG Pub. No. US 2011/0001229 A1).
Regarding claim 6, Foster in view of Im teaches the method of claim 1, wherein the packaged semiconductor device includes a first packaged semiconductor device (Foster, col. 12 lines 66-67: 58), wherein coupling terminals of a packaged semiconductor device to the first surfaces of at least some of the conductive leads via a conductive material includes mounting the terminals of the first packaged semiconductor device on the first surfaces of a first subset of the conductive leads (Foster, fig. 9A: terminals of 58 coupled to surfaces of at least a subset of 16).
Foster in view of Im does not teach wherein the method further comprises mounting terminals of a second packaged device on the first surfaces of a second subset of the conductive leads.
Chien teaches mounting a plurality of packaged semiconductor devices (¶ 0065 & fig. 1: plurality of 190, similar to 58 of Foster) on a plurality of subsets of conductive leads (figs. 1-2: each 190 mounted on a subset of 112a and/or 120).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Foster in view of Im with the plurality of packages of Chien, as a means to integrate multi chips into a system (Chien, ¶ 0007), increasing package functionality.
Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St Regis Paper Co. v. Bemis Co., 193 USPQ 8. In the instant case, modifying the method of Foster to include a second packaged semiconductor device mounted on surfaces of a second subset of conductive leads represents a mere duplication of the essential working parts disclosed by Foster.
Claims 14 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Foster in view of Im as applied to claims 1 and 16 above, and further in view of Karnezos (PG Pub. No. US 2005/0133916 A1).
Regarding claims 14 and 22, Foster in view of Im teaches the method of claim 1 and the apparatus of claim 16, wherein the packaged semiconductor device includes at least one of:
a quad flat package, or a small outline package (Foster, col. 8 lines 31-34 & col. 12 lines 66-67: semiconductor package 58, including QFP or TSOP among others).
Foster in view of Im does not teach the packaged semiconductor device includes at least one of a quad flat no-lead package, or a small outline no-lead package.
Karnezos teaches a packaged semiconductor device (¶ 0098: 902) mounted on surfaces of at least some conductive leads (fig. 9: 902 at least indirectly mounted on leads of carrier 12), wherein the packaged semiconductor device includes a quad flat no-lead package (¶ 0103: in at least one embodiment, 902 comprises a QFN package).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the packaged semiconductor device of Foster in view of Im as a QFN package, as a means to optimize integration density, design flexibility, reduce manufacturing costs, and/or improve performance (Karnezos, ¶¶ 0115-0116).
Response to Arguments
Applicant’s arguments, see page 6 lines 8-15, filed 12/1/2025, with respect to the formal claim objections of claims 3 and 6-8 and 35 USC § 112(b) rejections of claims 16-23 have been fully considered and are persuasive. Accordingly, the formal claim objections and 35 USC § 112(b) rejections have been withdrawn.
Applicant’s arguments with respect to the 35 USC § 103 rejections of claims 1-8 and 11-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/ Examiner, Art Unit 2818