Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/21/2025 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending. Claims 1-20 have been examined. Claims 1-4, 7-12, and 15-20 have been rejected. Claims 5-6 and 13-14 have been objected to.
Response to Arguments
Applicant's arguments filed 12/21/2025, see pp. 9-10, 12 – 13 ¶ 1, have been fully considered but they are not persuasive.
The Applicant argues that Li does not mention circuit blocks nor determine that certain circuit blocks will be modeled circuit blocks on p. 375 left col. last 2 paragraphs and p. 376 left col. ¶ 1, see pp. 9-10. The Examiner respectfully disagrees. On p. 375 left col. last 2 paragraphs, Li teaches full-chip analysis to evaluate the circuit performance using the extracted timing models associated with modules. Li, on p. 367 left col. last paragraph and right col. ¶ 2, teaches a hierarchical design comprising functional blocks called modules. Each functional block corresponds to a circuit block implemented with transistors and/or logic gates. In addition, Li teaches generating timing models for two modules in Fig. 7 on p. 375. Teaching of generating timing models for two modules means these two modules are determined to be modeled contained in a top-level circuit.
Regarding the Applicant’s argument that the last two paragraphs on p. 375 left col. concern a mathematical treatment of statistical gate delays, mathematical decomposition of random variables using PCA. These arguments are not pertinent to say that Li does not mention circuit blocks nor determine that certain circuit blocks will be modeled circuit blocks, which have been discussed above because the mathematical analyses of static timing analysis with respect to math, not related to Li’s teachings of circuit blocks and determination of certain circuit blocks to be modeled circuit blocks.
Regarding claim 2, the Applicant argues that Li does not teach “receiving an auxiliary specification associated with the circuit design; and selecting the one or more modeled circuit blocks based on the auxiliary specification,” see p. 12 ¶ 2-3, because the Li does not teach circuit blocks but concerns with building mathematical models for statistical timing analysis. As address above, Li does teach circuit blocks, so Li does teach this limitation discussed in the claim rejection section.
The Applicant, moreover, argues that claims 3-4 depending on claim 2 provide further details which also are not taught in the cited references. The Examiner respectfully disagrees. Li teaches these claims as discussed in the claim rejection section. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
The Applicant also argues that Kim does not teach selecting circuit blocks based on a weighted aggregate of the parameters in claim 5, see p. 12 last paragraph – p. 13 ¶ 1. Applicant’s arguments have been fully considered and are persuasive. The 35 USC 103 rejections of claims 5-6 and 13-14 have been withdrawn.
Applicant’s arguments with respect to claim 1 and similarly independent claims 11 and 19, see section B. p. 10 last paragraph – p. 12. ¶ 1, have been considered but are moot because the new ground of rejection relies on a new reference in addition to previous references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7, 11-12, 15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (On Timing Model Extraction and Hierarchical Statistical Timing Analysis) in view of McBride (US 7,031,889), and Foltin et al. (US 6996515).
As per claim 1, Li teaches a method comprising:
receiving a circuit design comprising a plurality of circuit blocks (p. 367, right col. ¶ 2; Li teaches pre-designed functional blocks also called modules being performed timing analysis; this teaching reads onto this limitation);
determining, by a processor, one or more of the circuit blocks as modeled circuit blocks contained in a top-level circuit (p. 367 left col. last paragraph and right col. ¶ 2, p. 375, left col. last 2 paragraphs; Li teaches generating timing models for two modules in Fig. 7; a module as taught by Li corresponds to a circuit block contained in top-level circuit; these teachings read onto determining step as recited in this limitation);
selecting a subset of one or more of the modeled circuit blocks as simplified reduced modeled (SRM) circuit blocks (p. 376 left col. ¶ 1; Li teaches in generating timing models for a module, unimportant components may be discarded; this teaching means the remaining un-discarded components are identified as a subset of modeled circuit blocks as simplified reduced modeled (SRM) circuit blocks because this part of the limitation does not clarify what subset of one or more of the modeled circuit blocks is; hence, under BRI Li’s teaching reads onto this limitation); and
performing the static verification of the circuit design (p. 367 Abstract & right col. ¶ 2, p. 377 left col. ¶ 3; Li teaches performing static timing analysis/verification on the circuit design).
Li does not teach:
generating simplified reduced models for the SRM circuit blocks, wherein a simplified reduced model of an SRM circuit block includes circuit details of a first subset of circuit components of the SRM circuit block for performing static verification of the circuit design and excludes circuit details of a second subset of circuit components of the SRM circuit block; and
performing the static verification of the circuit design by (a) performing static verification of the SRM circuit blocks and (b) performing static verification of the top-level circuit using the simplified reduced models of the SRM circuit blocks, wherein performing the static verification comprises performing a functional simulation of the circuit design.
However, Foltin teaches:
generating simplified reduced models for the SRM circuit blocks, wherein a simplified reduced model of an SRM circuit block includes circuit details of a first subset of circuit components of the SRM circuit block for performing static verification of the circuit design and excludes circuit details of a second subset of circuit components of the SRM circuit block (col. 6 lines 31-59; Foltin teaches a hierarchical design with timing abstraction model supporting multiple levels and blocks and extracting timing model for one or more blocks, which is limited to most critical paths, a path from an input port to a setup/hold check node or between input and output ports; this teaching indicates that these one or more circuit blocks in critical paths are selected for timing analysis and timing model extraction; the teaching of limiting to critical paths means one or more circuit blocks in these critical paths are simplified to include only needed circuit components and exclude not-needed circuit components for the static timing analysis and read onto this limitation); and
performing the static verification of the circuit design by (a) performing static verification of the SRM circuit blocks and (b) performing static verification of the top-level circuit using the simplified reduced models of the SRM circuit blocks (col. 6 lines 31-59; Foltin teaches performing static verification of the circuit design on critical paths at multiple levels of hierarchy and limits timing analysis to most critical paths; this teaching reads onto this limitation).
Li and Foltin are analogous art because they are in the same field of static timing analysis of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Li and Foltin. One of ordinary skill in the art would have been motivated to make such a combination because Foltin’s teachings would have simplified the output from the timing analysis and shortened a designer’s time to analyze STA, Static Timing Analysis results (Foltin, col. 6 lines 59-61).
Li and Foltin do not teach:
performing a functional simulation of the circuit design.
Howewever, McBride teaches:
performing a functional simulation of the circuit design (col. 1 lines 27-29; McBride teaches designs are simulated to verify functionality).
Li, Foltin, and McBride are analogous art because they are in the same field of static timing analysis of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Li, Foltin, and McBride. One of ordinary skill in the art would have been motivated to make such a combination because McBride’s teachings would have ensured that performance goals are satisfied (McBride, col. 1 lines 27-29).
As per claim 2, Li, Foltin, and McBride in combination teach the method of claim 1, Li further teaches wherein selecting the one or more modeled circuit blocks comprises:
receiving an auxiliary specification associated with the circuit design (p. 368 right col. ¶ 6; Li teaches types of constraints in extract timing models; these constraints are considered an auxiliary specification associated with the circuit design received); and
selecting the one or more modeled circuit blocks based on the auxiliary specification (p. 375 left col. last two paragraphs; 370 right col. ¶ 1-3; Li teaches timing constraints associated with critical timing paths, corresponding to auxiliary specification, and extraction of timing models associated with critical timing paths; this teaching reads onto this limitation).
As per claim 4, Li, Foltin, and McBride in combination teach the method of claim 2, Li further teaches wherein selecting the one or more modeled circuit blocks based on the auxiliary specification comprises:
receiving implicit guidance from the auxiliary specification that specifies a plurality of constructs, each construct specifying a path of a circuit block, wherein receiving implicit guidance comprises matching paths of different constructs from the plurality of constructs that correspond to a particular modeled circuit block (p. 367, right col. ¶ 2; Li teaches a design with internal timing constraints from interfacing logic for timing paths; these constraints are considered implicit guidance from the auxiliary specification as recited).
As per claim 7, Li, Foltin, and McBride in combination teach the method of claim 1, Li further teaches further comprising:
determining constraints associated with the simplified reduces models of the modeled circuit blocks, wherein performing static verification of the circuit design further uses the constraints (p. 368 right col. last paragraph; Li teaches statistical interfacing constraints between internal flip-flops included for full chip analysis).
As per claim 11, Li teaches a non-transitory computer readable medium comprising stored instructions, which when executed by one or more computer processors, cause the one or more computer processors to (p. 377 left col. ¶ 1): (below limitations have already been discussed in claim 1 as being taught by the combination of Li, Foltin, and McBride. They are, therefore, rejected for the same reasons)
receive a circuit design comprising a plurality of circuit blocks;
select a subset of one or more of the modeled circuit blocks as simplified reduced modeled (SRM) circuit blocks;
generate simplified reduced models for the SRM circuit blocks, wherein a simplified reduced model of an SRM circuit block includes circuit details of a first subset of circuit components of the SRM circuit block for performing static verification of the circuit design and excludes circuit details of a second subset of circuit components of the SRM circuit block; and
perform static verification of the circuit design using the simplified reduced models of the SRM circuit blocks, wherein performing the static verification comprises performing a functional simulation of the circuit design.
As per claim 12, these limitations have already been discussed in claim 2. They are, hence, rejected for the same reasons.
As per claim 15, these limitations have already been discussed in claim 7. They are, hence, rejected for the same reasons.
As per claim 19, these limitations have already been discussed in claim 11. They are, hence, rejected for the same reasons.
As per claim 20, these limitations have already been discussed in claim 2. They are, hence, rejected for the same reasons.
Claims 3, 9, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (On Timing Model Extraction and Hierarchical Statistical Timing Analysis) in view of Foltin et al. (US 6996515) and McBride (US 7,031,889) as applied to claims 1, 2 and 11 above, and further in view of Cadence (Hierarchical Timing Analysis: Pros, Cons, and a New Approach).
As per claim 3, Li, Foltin, and McBride in combination teach the method of claim 2,
Li, Foltin, and McBride do not teach:
wherein selecting the one or more modeled circuit blocks based on the auxiliary specification comprises:
receiving explicit guidance from the auxiliary specification based on constructs that explicitly specify circuit blocks as input and specify constraints for the specified circuit blocks.
However, Cadence teaches:
receiving explicit guidance from the auxiliary specification based on constructs that explicitly specify circuit blocks as input and specify constraints for the specified circuit blocks (p. 2 ¶ 2, p. 9 ¶ 1, last two paragraphs; Cadence teaches Tempus tool with ability to dynamically abstract only those portions of the design that a user wants to analyze associated with certain constraints; this teaching reads onto this limitation).
Li, Foltin, McBride, and Cadence are analogous art because they are in the same field of static timing analysis of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Li, Foltin, McBride, and Cadence. One of ordinary skill in the art would have been motivated to make such a combination because Cadence’s would have dramatically improved runtime and capacity (Cadence, p. 8 ¶ 5).
As per claim 9, Li, Foltin, and McBride in combination teach the method of claim 1,
Li, Foltin, and McBride do not teach:
wherein the determining one or more of the circuit blocks as modeled circuit blocks is performed based on a top down traversal of circuit blocks of the circuit design.
However, Cadence teaches:
the determining one or more of the circuit blocks as modeled circuit blocks is performed based on a top down traversal of circuit blocks of the circuit design (p. 2 ¶ 2, p. 8 ¶ 5, p. 9 ¶ 1 Figure 5; Cadence teaches its Tempus tool performing timing extraction model for individual subsets of the design once top-level scope is provided; this teaching indicates that one or more of the circuit blocks is performed based on a top down traversal of circuit blocks of the circuit design).
Li, Foltin, McBride, and Cadence are analogous art because they are in the same field of static timing analysis of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Li, Foltin, McBride, and Cadence. One of ordinary skill in the art would have been motivated to make such a combination because Cadence’s would have dramatically improved runtime and capacity (Cadence, p. 8 ¶ 5).
As per claim 17, these limitations have already been discussed in claim 9. They are, hence, rejected for the same reasons.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (On Timing Model Extraction and Hierarchical Statistical Timing Analysis) in view of Foltin et al. (US 6996515) and McBride (US 7,031,889) as applied to claims 7 and 15 above, and further in view of Jyu et al. (US 5880967).
As per claim 8, Li, Foltin, and McBride in combination teach the method of claim 7, wherein the determining constraints associated with the one or more modeled circuit blocks.
Li, Foltin, and McBride do not teach:
receiving one or more commands for performing operations related to circuit design, the operations associated with one or more of power constraints, design constraints, and area constraints;
extracting a parameter of the command; and
generating a constraint based on the parameter.
However, Jyu teaches:
receiving one or more commands for performing operations related to circuit design, the operations associated with one or more of power constraints, design constraints, and area constraints (col. 9 line 59-67 & col. 10 lines 52-55; Jyu teaches commands to perform operations related to circuit design comprising configuration file including design constraints and goals);
extracting a parameter of the command (col. 6 lines 6-16; Jyu teaches configuration file specifying runtime options and commands, as discussed in limitation above; these teachings mean included constraints in the command are extracted for the tool to perform operations); and
generating a constraint based on the parameter (col. 6 lines 6-16; Jyu teaches configuration file specifying runtime options and commands, as discussed in limitation above; these teachings mean included constraints with parameters in the command are extracted for the tool to perform operations).
Li, Foltin, McBride, and Jyu are analogous art because they are in the same field of static timing analysis of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Li, Foltin, McBride, and Jyu. One of ordinary skill in the art would have been motivated to make such a combination because Jyu’s would have provided a method for minimizing sign delay and power consumption (Jyu, Abstract).
As per claim 16, these limitations have already been discussed in claim 8. They are, hence, rejected for the same reasons.
Claims 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (On Timing Model Extraction and Hierarchical Statistical Timing Analysis) in view of Foltin et al. (US 6996515) and McBride (US 7,031,889) as applied to claims 1 and 11 above, and further in view of Kulshreshtha et al. (US 10037394).
As per claim 10, Li, Foltin, and McBride in combination teach the method of claim 1,
Li, Foltin, and McBride do not teach:
wherein generating simplified reduced models for the modeled circuit blocks is performed in parallel on a plurality of processors.
However, Kulshreshtha teaches:
generating models for the modeled circuit blocks is performed in parallel on a plurality of processors (col. 2 lines 16-25).
Li, Foltin, McBride, and Kulshreshtha are analogous art because they are in the same field of static timing analysis of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Li, Foltin, McBride, and Kulshreshtha for generating simplified reduced models for the modeled circuit blocks is performed in parallel on a plurality of processors. One of ordinary skill in the art would have been motivated to make such a combination because Kulshreshtha’s would have helped reduce time to execute the recited method.
As per claim 18, these limitations have already been discussed in claim 10. They are, hence, rejected for the same reasons.
Allowable Subject Matter
Claims 5-6 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As per claim 5, Li, Foltin, and McBride in combination teach the method of claim 1, Li further teaches wherein selecting the one or more modeled circuit blocks comprises:
receiving parameters describing the circuit blocks in the circuit design (p. 367 right col. ¶ 2; Li teaches timing constraints for blocks, corresponding to parameters describing the circuit blocks in the circuit design);
Li, Foltin, and McBride do not teach:
determining a weighted aggregate of the parameters; and
selecting the one or more modeled circuit blocks based on the weighted aggregate of the parameters;
in combination with other limitations as recited in the claim.
Claim 13 recites limitations analogous to those in claim 5 including the limitations indicated allowable. Claim 13 is allowable for the same reasons.
Claims 6 and 14 depend on claims 5 and 13, respectively. They are allowable for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Cuong Van Luu whose telephone number is 571-272-8572. The examiner can normally be reached on Monday - Friday from 8:30 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rehana Perveen, can be reached at telephone number (571)272-3676, the fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CUONG V LUU/Examiner, Art Unit 2189
/REHANA PERVEEN/Supervisory Patent Examiner, Art Unit 2189