DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Examiner withdraws the specification objection based upon Applicant’s statement filed on December 11, 2025.
Claim Rejections - 35 USC § 112(a)
Examiner withdraws the 35 USC § 112(a) based upon Applicant’s arguments dated December 11, 2025.
Response to Arguments
In regards to claim 1,
Applicant’s amendments to claim 1 have made the claim allowable. See Allowable Subject Matter below.
In regards to claim 26,
Applicant's amendments filed December 11, 2025 have been fully considered and have overcome the previous grounds of rejection. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of prior art below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 26-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchiko (US 2014/0167144 A1) (“Tsuchiko”), in view of Harrison, Linden, "An introduction to depletion-mode MOSFETs", https://www.aldinc.com/pdf/IntroDepletionModeMOSFET.pdf, Nov. 19, 2014 (Year: 2014) (“Linden”), in view of Baliga (US 5,637,898) (“Baliga)
Regarding the combination:
Tsuchiko teaches a lateral DMOS. Linden in figure 2 teaches that a lateral DMOS is an obvious variant of a vertical DMOS. Linden teaches in a vertical structure the substrate will service as a drain region as the drain in on the bottom of the substrate. Thus, one of ordinary skill in the art using routine skill in the art would know that they could move the drain from a lateral position to a vertical position in order to get a higher breakdown voltage, lower on-resistance, and higher current capabilities.
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The combination of Tsuchiko and Linden would result in the one using all the elements from 56 upward of Tsuchiko and replacing the n-BL layer of Tsuchiko with N+ layer of Linden and moving the drain (84) of Tsuchiko to the drain location of Linden.
Examiner will now match the claim limitations with the combination as described above.
Regarding claim 26, the combination of Tsuchiko in at least figure 3, and Linden in at least figure 2 teach:
a semiconductor substrate (Linden N+) of a first conductivity type (n-type),
the substrate (Linden N+) serving as a drain region in the MOSFET device (Linden N+ so serves as the drain region);
an epitaxial region (Tsuchiko 56) of the first conductivity type (n-type) disposed on an upper surface of the substrate (Linden N+);
a plurality of body regions (Tsuchiko 58) of a second conductivity type (p-type) formed in the epitaxial region (Tsuchiko 56),
the second conductivity type (p-type) being opposite in polarity to the first conductivity type (n-type),
the body regions (Tsuchiko 58) being disposed proximate an upper surface of the epitaxial region (top surface of Tsuchiko 56) and spaced laterally from one another (they are so spaced);
a plurality of source regions (Tsuchiko 66) of the first conductivity type (n-type),
each of the source regions (Tsuchiko 66) being disposed in a corresponding one of the body (Tsuchiko 58) regions proximate an upper surface of the body region (they are so disposed);
a gate structure (Tsuchiko G/78) comprising a plurality of planar gates (Tsuchiko G) and a trench gate (Tsuchiko 78),
each of the planar gates (Tsuchiko G) being disposed on the upper surface of the epitaxial region (Tsuchiko 56) and overlapping at least a portion of a corresponding body region (Tsuchiko 58),
the trench gate (Tsuchiko 78) being formed at least partially through the epitaxial region (Tsuchiko 58) and between the body regions (Tsuchiko 58); and
a dielectric layer (Tsuchiko 76) disposed between the trench gate (Tsuchiko 78) and the epitaxial region (Tsuchiko 56),
Tsuchiko does not explicitly teach:
the dielectric layer including a first portion defining a bottom wall of the trench gate and extending partially up a sidewall of the trench gate, and a second portion extending up the sidewall of the trench gate toward the upper surface of the epitaxial region,
the first portion having a first thickness on the sidewall of the trench gate in a direction parallel to the upper surface of the substrate, and
the second portion having a second thickness on the sidewall of the trench gate in the direction,
the first thickness being greater than the second thickness such that a horizontal width of a lower portion of the trench gate is less than a horizontal width of an upper portion of the trench gate.
Baliga teaches at least in figure 3:
the dielectric layer (124) including a first portion (T1) defining a bottom wall of the trench gate (126) and extending partially up a sidewall of the trench gate (T1 so partially extends up 126), and
a second portion (T2) extending up the sidewall of the trench gate (126) toward the upper surface of the epitaxial region (112),
the first portion (T1) having a first thickness on the sidewall of the trench gate in a direction parallel to the upper surface of the substrate (this is shown in figure 3), and
the second portion (T2) having a second thickness on the sidewall of the trench gate in the direction (this is shown in figure 3),
the first thickness being greater than the second thickness such that a horizontal width of a lower portion of the trench gate is less than a horizontal width of an upper portion of the trench gate (T1 is thicker than T2).
It would have been obvious to one of ordinary skill in the art to modify the trench gate and trench gate insulator of Tsuchiko in order to “inhibit the occurrence of high electric field crowding at the bottom corners of the trench and to provide a substantially uniform potential gradient along the trench sidewall”. Col. 8 at lines 15-18.
Regarding claim 27, the prior art does not teach:
wherein a lower portion of the trench gate is at least partially surrounded by the first portion of the dielectric layer, and an upper portion of the trench gate is at least partially surrounded by the second portion of the dielectric layer,
the upper portion of the trench gate having a first width in the direction that is greater than a second width in the direction of the lower portion of the trench gate.
Baliga teaches at least in figure 3:
wherein a lower portion of the trench gate (bottom of 126) is at least partially surrounded by the first portion of the dielectric layer (T1), and
an upper portion of the trench gate (top part of 126) is at least partially surrounded by the second portion of the dielectric layer (t2),
the upper portion of the trench gate having a first width in the direction that is greater than a second width in the direction of the lower portion of the trench gate (the upper part of 126 is wider than the lower part of 126).
It would have been obvious to one of ordinary skill in the art to have the claimed shape of gate electrode as it will maintain the threshold voltage of the device while inhibiting the occurrence of high electric field crowding the bottom corners of the trench. Col. 8 at lines 15-30.
Regarding claim 28, Baliga teaches at least in figure 3
wherein the first thickness is in a range of 50 to 500 nanometers (Col. 8 at lines 5-40, where the thickness of upper 126 can be 450 nm).
Regarding claim 29, Baliga teaches at least in figure 3
wherein the second thickness is in a range of 10 to 50 nanometers (Col. 8 at lines 5-40, where the thickness of lower 126 can be 300 nm; however, it would have been obvious for one of ordinary skill in the art to try different thicknesses/widths of the gate electrode to optimize electric field and provide an optimal potential gradient on the sidewalls of the gate electrod
Allowable Subject Matter
Claims 1-11, and 21-25 are allowed.
The following is an examiner’s statement of reasons for allowance: See below.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding claim 1, the combination of Tsuchiko in at least figure 3, and Linden in at least figure 2 teach:
a semiconductor substrate (Linden N+) of a first conductivity type (n-type),
the substrate (Linda N+) serving as a drain region in the MOSFET device (Linden N+ so serves as a drain region);
an epitaxial region (Tsuchiko 56) of the first conductivity type (n-type) disposed on an upper surface of the substrate (Linden N+);
a plurality of body regions (Tsuchiko 58) of a second conductivity type (p-type) formed in the epitaxial region (Tsuchiko 56),
the second conductivity type (p-type) being opposite in polarity to the first conductivity type (n-type),
the body regions (Tsuchiko 58) being disposed proximate an upper surface of the epitaxial region (top surface of Tsuchiko 56) and spaced laterally from one another (they are so spaced);
a plurality of source regions (Tsuchiko 66) of the first conductivity type (n-type),
each of the source regions (Tsuchiko 66) being disposed in a corresponding one of the body regions (Tsuchiko 58) proximate an upper surface of the body region (they are so disposed); and
a gate structure (Tsuchiko G/78) comprising a plurality of planar gates (Tsuchiko G) and a trench gate (Tsuchiko 78),
each of the planar gates (Tsuchiko G) being disposed on the upper surface of the epitaxial region (Tsuchiko 56) and overlapping at least a portion of a corresponding body region (Tsuchiko 58),
the trench gate (Tsuchiko 78) being formed at least partially through the epitaxial region (Tsuchiko 56) and between the body regions (Tsuchiko 58),
Tsuchiko and Linden do not teach:
an upper surface of the trench gate (Tsuchiko 78) extending on the upper surface of the epitaxial region in a first direction parallel to the upper surface of the substrate,
the upper portion of the trench gate being vertically non-overlapping with respect to the plurality of body regions.
This is because the prior art does not show the trench gate extends on the upper surface of the substrate.
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898