DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 20 March 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-7, 10-12, 21, and 23-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20200203253 (Neal et al).
As to Claim 1, Neal teaches a microelectronic assembly (Fig 16), comprising:
an integrated circuit die (180); and
a package substrate comprising a core, a first redistribution layer on a first side of the core, and a second RDL on a second side of the core (110/150/160, respectively),
wherein:
the first side of the core is opposite the second side of the core (150 and 160 on opposite sides of 110),
the IC die is coupled to a surface of the package substrate, the surface being parallel to the core (180 coupled to top of 150 parallel to 110),
each of the first RDL and second RDL comprises one or more layers of a dielectric material, with conductive traces adjacent to the one or more layers of the dielectric material and conductive vias through the one or more layers of the dielectric material (150/160 disclosed as being build-up structures with conductive routes 158/168 shown therein ¶0044),
the core is a monolithic block of a material that is one of glass, ceramic, or metal (110 disclosed as being a single structure ¶0040, and can be, e.g., glass ¶0038),
the core includes a hollow channel embedded between the first side of the core and the second side of the core (channels 118 between top and bottom of 110),
all walls of the hollow channel are materially-continuous portions of the material of the monolithic block (materials of 110 disclosed as being single structure ¶0040),
the core further includes a conductive via extending from the first side of the core to the second side of the core (170)
a portion of the conductive via at the first side of the core is conductively coupled to at least one of the conductive traces or conductive vias of the first RDL (170 connected to dashed line above), and
a portion of the conductive via at the second side of the core is conductively coupled to at least one of the conductive traces or conductive vias of the second RDL (170 connected to dashed line below).
As to Claim 2, Neal teaches the microelectronic assembly of claim 1, wherein the channel comprises a plurality of turns in a plane parallel to the surface of the package substrate (Fig 2 shows perpendicular turns in channels 118 relative to top view of Fig 1).
As to Claim 6, Neal teaches the microelectronic assembly of claim 1 wherein a portion of the channel crosses another portion of the channel in a plane parallel to the surface of the package substrate (Fig 2 shows vertical portions crossing horizontal portions of channels 118)
As to Claim 7, Neal teaches the microelectronic assembly of claim 1 wherein the channel comprises forked portion in a plane parallel to the surface of the package substrate (paths shown in Fig 2 reasonably constitute “forked portions”)
As to Claim 10, Neal teaches a component of a microelectronic assembly, the component comprising:
a core comprising a monolithic panel of glass having a first surface, a second surface opposite the first surface, and a channel embedded between the first surface and the second surface (110 may be glass ¶0038 with channel 118 between top and bottom surfaces), wherein the channel has a coolant therein (coolant 120); and
redistribution layers on either side of the core (150/160), the redistribution layers comprising:
one or more layers of a dielectric material (150/160 comprise build-up layers ¶0044),
conductive traces adjacent to the one or more layers (158/168), and
conductive vias through the one or more layers coupled to the conductive traces (170), wherein:
the coolant is one of a liquid material and a gaseous material (120 may comprise water ¶0039).
As to Claim 11, Neal teaches the component of claim 10, wherein the component comprises a package substrate coupled to an IC die on a surface (180 on top of package comprising 150+160+110) and to a PCB on an opposing surface (contacts 164 on bottom side of 160 may connect to a motherboard or other similar components ¶0046), the core being parallel to the surface and the opposing surface (110 parallel to both these surfaces)
As to Claim 12, Neal teaches the component of claim 10, wherein the component comprises a PCB coupled to a package substrate on a surface parallel to the core (contacts 164 may couple to a motherboard or other similar components ¶0046).
As to Claim 21, Neal teaches the microelectronic assembly of claim 1, wherein:
the core includes a plurality of hollow channels and a plurality of conductive vias extending from the first side of the core to the second side of the core (118 and 170, respectively),
the channel is one of the plurality of channels (118 are plural),
the conductive via is one of the plurality of conductive vias (170 are plural), and
in a cross-sectional side view of the core, conductive vias of the plurality of conductive vias alternate with channels of the plurality of channels (view of Fig 16 shows in the middle 118 with neighboring 170 alternating).
As to Claim 23, Neal teaches the microelectronic assembly of claim 1, wherein:
the IC die is conductively coupled to at least one of the conductive traces or conductive vias of the first RDL (180 coupled to 158),
the microelectronic assembly further includes an electronic component (164 may connect to a further component ¶0046),
the electronic component is conductively coupled to at least one of the conductive traces or conductive vias of the second RDL (164 coupled to 168), and
the electronic component includes one of another IC die, a circuit board, or an interposer (additional component may include a motherboard or other similar component ¶0046).
As to Claim 24, Neal teaches the component of claim 10, wherein:
the core has a first side and a second side opposite the first side (top and bottom of 110 respectively),
the core further includes a conductive via extending from the first side of the core to the second side of the core (170 extends as described),
the redistribution layers on either side of the core include first redistribution layers on the first side of the core and second redistribution layers on the second side of the core (150/160 each include build-up layers and conductive lines therein ¶0044),
a portion of the conductive via at the first side of the core is conductively coupled to at least one of the conductive traces or conductive vias of the first redistribution layers (170 coupled to 158), and
a portion of the conductive via at the second side of the core is conductively coupled to at least one of the conductive traces or conductive vias of the second redistribution layers (170 coupled to 168).
As to Claim 25, Neal teaches a component of a microelectronic assembly (Fig 16), the component comprising:
A core comprising a materially-continuous block of a core material that is glass, ceramic, or metal, wherein the core includes a hollow channel within a core thickness (110 may be a single material ¶0040, the material being glass ¶0038 including channel 118 therein); and
Redistribution layers on either side of the core (150/160), the redistribution layers comprising:
One or more layers of a dielectric material (150/160 comprise build-up layers ¶0044;
Conductive traces adjacent to the one or more layers (portions of 158/168 horizontal in view of Fig 16);
Conductive vias through the one or more layers coupled to the conductive traces (portions of 158/168 vertical in view of Fig 16).
As to Claim 26, Neal teaches the component of claim 25, wherein:
the core has a first side and a second side opposite the first side (top and bottom of 110),
the core further includes a conductive via extending from the first side of the core to the second side of the core (170),
the redistribution layers on either side of the core include first redistribution layers on the first side of the core and second redistribution layers on the second side of the core (150/160 comprise build-up layers ¶0044),
a portion of the conductive via at the first side of the core is conductively coupled to at least one of the conductive traces or conductive vias of the first redistribution layers (158 coupled to 170), and
a portion of the conductive via at the second side of the core is conductively coupled to at least one of the conductive traces or conductive vias of the second redistribution layers (168 coupled to 170).
As to Claim 27, Neal teaches the component of claim 25, wherein all walls of the hollow channel are portions of the materially-continuous block of the core material (walls also comprise the glass material of the core)
As to Claim 28, Neal teaches the component of claim 25, wherein no portion of walls of the hollow channel include conductive interconnect features or solder features (channels comprise glass which do not include conductive interconnect or solder features)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neal as applied to claim 1 above, and further in view of US 20220256692 (Weis).
As to Claim 3, Neal teaches the microelectronic assembly of claim 2 but fails to explicitly disclose the channel being joined end to end within the package substrate. Rather, Neal Fig 16 discloses ends of the channel being on a top surface of the package substrate.
Weis teaches an assembly similar to that of Neal, wherein a cooling assembly comprises coolant channels which are joined end-to-end within that assembly (Weis discloses a device where the fluid path may constitute a closed circular path, i.e., is joined end to end within the assembly ¶0013).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the assembly having general coolant channels taught by Neal with the end-to-end joined channel taught by Weis in order to mitigate the possibility of coolant leaks by including no coolant openings.
As to Claim 5, Neal teaches the microelectronic assembly of claim 1 but fails to explicitly disclose the channel being sealed within the package substrate. Weis, as described in the claim 3 rejection above and for the same reasons, discloses a cooling assembly wherein the coolant channel is sealed within (see claim 3 rejection).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neal as applied to claim 2 above, and further in view of US 20180211900 (Gutala et al).
As to Claim 4, Neal teaches the microelectronic assembly of claim 2 but fails to explicitly disclose an additional IC die or details thereof.
Gutala teaches an assembly similar to that of Neal, specifically including multiple die (Gutala Fig 1, dies 103-105) and coolant channels disposed adjacent to those die (channels in fluid routing device 102) and further teaching modifying the density of channels over individual die to customize the cooling needs of those die (e.g. channels more densely packed over 103 than over 105; ¶0024).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the assembly taught by Neal with the inclusion of plural IC die and modifying the density of channels near those die taught by Gutala in order to remove the need for each die having their own assembly, as well as being able to tailor cooling needs based on the types of die used.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neal as applied to claim 1 above, and further in view of US 20200281096 (Shioga et al).
As to Claim 8, Neal teaches the microelectronic assembly of claim 1, but fails to explicitly teach wherein the channel is coupled to an external cooling circuit. Neal only explicitly teaches the channel being open to environments outside of the assembly.
Shioga teaches an assembly similar to that of Neal and specifically teaches a coolant channel (Shioga Fig 6, 26) being coupled to an external cooling circuit (26 coupled to condenser 32).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the assembly containing coolant channels taught by Neal with the connection of coolant channels to an external cooling circuit taught by Shioga in order to further reduce the temperature of the coolant, improving cooling efficiency.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neal and Shioga as applied to claim 8 above, and further in view of US Patent 11,221,184 (Weed et al).
As to Claim 9, the combination of Neal and Shioga teaches the microelectronic assembly of claim 8, but fails to explicitly disclose wherein the external cooling circuit comprises a heat sink.
Weed teaches an assembly similar to that of Neal and Shioga, and specifically teaches the addition of a heat sink onto the condenser of an external cooling circuit (Weed Fig 1B; Col. 3 lines 45-46).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the assembly including an external cooling circuit taught by Neal and Shioga with the inclusion of a heat sink onto a condenser taught by Weed in order to even further improve the cooling efficiency of the assembly.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neal.
As to Claim 22, Neal teaches the microelectronic assembly of claim 1, but fails to explicitly teach relative dimensions of the channel and the IC die along a direction parallel to a surface of the package substrate. While examiner notes that the channels 118 appear to be smaller along the horizontal direction of Fig 16 than the die 180 along that direction, Neal does not explicitly disclose such a relationship. However, examiner argues that it would have been obvious to one of ordinary skill in the art at the time of filing that the channels taught by Neal may have the claimed relationship.
Further, the claimed invention would have been obvious as courts have held that mere changes in size or proportion of features are not sufficient to patentably distinguish over the prior art (see MPEP §2144.04.IV.A).
Response to Arguments
Applicant’s arguments filed 10 February 2026, with respect to rejections relying on Karhade as primary prior art have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of prior.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corbyn D Mellinger whose telephone number is (703)756-5683. The examiner can normally be reached M-F 8-5 Eastern.
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/Corbyn D Mellinger/ Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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