DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 22, 2025 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 9, and 11-12 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2018/0047656 A1 to Mkhitarian et al. (“Mkhitarian”). As to claim 1, Mkhitarian discloses a semiconductor device comprising: a substrate (102); a first source finger (right 108 at 210) provided on the substrate (102); a first gate finger (right 110) provided adjacent to the first source finger (right 108 at 210) in a width direction (Y) of the first source finger (right 108 at 210), and on the substrate (102) along the first source finger (right 108 at 210); a first drain finger (right 112 at 208) provided on the substrate (102) and sandwiching the first gate finger (right 110) between the first source finger (right 108 at 210) and the first drain finger (right 112 at 208); a second source finger (left 108 at 210) provided on a region of the substrate (102) located in an extension direction (X) of the first source finger (right 108 at 210) from the first source finger (right 108 at 210), and extending in the extension direction (X); a second gate finger (left 110) provided adjacent to the second source finger (left 108 at 210) in the width direction (Y) of the second source finger (left 108 at 210), on a region of the substrate (102) located in the extension direction (X) from the first gate finger (right 110), and along the second source finger (left 108 at 210); a second drain finger (left 112) provided on the substrate (102) and sandwiching the second gate finger (left 110) between the second source finger (left 108 at 210) and the second drain finger (left 112); and a first gate wiring (208 Y shape) provided on the substrate (102), the first gate wiring (208 Y shape) having a first region (to tip of right 110) at a tip of the first gate wiring (208 Y shape) and a second region (tapered 212 to 210) extending in the width direction (Y), the first region (to tip of right 110) connected to a first end of the first gate finger (right 110), not connected to the second gate finger (left 110), and the second region (tapered 212 to 210) extending in the width direction (Y); wherein a width of the first gate wiring (208 Y shape) in the extension direction (X) at the first region (to tip of right 110) where the first gate finger (right 110) connects to the first gate wiring (208 Y shape) is smaller than a width of the first gate wiring (208 Y shape) in the extension direction (X) at the second region (tapered 212 to 210) located between the first source finger (right 108 at 210) and the second source finger (left 108 at 210), and an end of the first region (to tip of right 110) near the second gate finger (left 110) in the extension direction (X) is located closer to the second gate finger (left 110) than an end of the second region (tapered 212 to 210) near the second gate finger (left 110) in the extension direction (X); wherein the second gate finger (left 110) is provided on same axis as the first gate finger (right 110), a distance between the first gate finger (right 110) and the second gate finger (left 110) is smaller than the width of the second region (tapered 212 to 210) at the first gate wiring (208 Y shape) in the extension direction (X); and wherein a tip of the second gate finger (left 110) is located in an extension of the second region (tapered 212 to 210) of the first gate wiring (208 Y shape) (See Fig. 1, Fig. 2C, ¶ 0029, ¶ 0032, ¶ 0035, ¶ 0047-¶ 0050) (Notes: the limitation “region” is defined as an extensive, continuous part of a surface, space, or body by Dictionary.com. Further, the first region has a smaller width than the second region between the first and second source fingers because of the longer second region of the Y shape. Furthermore, the end of the first region that is overlapping the second gate finger in the extension direction is closer than the end of the second region that is not overlapping with the second gate finger in the extension direction). As to claim 4, Mkhitarian discloses further comprising: a gate bus bar (204) provided on the substrate (102) and to which the second gate finger (left 110) is connected; and a second gate wiring (left 208 to 204) connecting the first gate wiring (208 Y shape) to the gate bus bar (204) and extending in the extension direction (X) (See Fig. 2C). As to claim 5, Mkhitarian further discloses wherein the second gate wiring (left 208 to 204) and the second gate finger (left 110) sandwich the second source finger (left 108 at 210) (See Fig. 2C). As to claim 9, Mkhitarian further discloses wherein the substrate (102) includes a first active region (right) in which a semiconductor layer inside the substrate (102) is activated, a second active region (left) in which the semiconductor layer inside the substrate (102) is activated, the first active region (right) and the second active region (left) being separated from each other, and an inactive region (at 212) provided between the first active region (right) and the second active region (left) and in which the semiconductor layer is deactivated, the first source finger (right 108 at 210), the first gate finger (right 110), and the first drain finger (right 112 at 208) are provided on the first active region (right), the second source finger (left 108 at 210), the second gate finger (left 110), and the second drain finger (left 112) are provided on the second active region (left), and the first gate wiring (208 Y shape) is provided on the inactive region (See Fig. 2C, ¶ 0032) (Notes: the first and second active regions are “activated” by allowing current flow between source and drain, whereas the inactive region is “deactivated” in the semiconductor without having the current flow between the source and the drain).
As to claim 11, Mkhitarian further discloses wherein the tip of the second gate finger (left 110) is located in a region of the substrate (102) bound within an axis of the first gate finger (right 110) extending in the extension direction (X) and an axis of the second region (tapered 212 to 210) of the first gate wire (208 Y shape) extending in the width direction (Y) (See Fig. 2C). As to claim 12, Mkhitarian further discloses wherein the tip of the second gate finger (left 110) is located in a region of the substrate (102) bound within an axis of the first gate finger (right 110) extending in the extension direction (X), a first axis of the second region (tapered 212 to 210) of the first gate wire (208 Y shape) extending in the width direction (Y), and a second axis of the second region (tapered 212 to 210) of the first gate wire (208 Y shape) extending in the width direction (Y), wherein the first and second axes of the second region (tapered 212 to 210) of the first gate wire (208 Y shape) define a maximum width (longer Y shape) of the first gate wire (208 Y shape) in the extension direction (X) (See Fig. 2C).
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815