DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 7, 9, 13, and 17-19 have been amended.
Claims 2-6 and 12 have been cancelled.
Claim 21 has been added.
Claims 1, 7-11, and 13-21 have been examined.
Information Disclosure Statement
The applicant's submission of the Information Disclosure Statement dated August 22, 2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. A copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 19 recites, in several places, “the computation system.” There is insufficient antecedent basis for this limitation in the claim.
Claims 20 and 21 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 8, 10, 11, 13, 14, and 16-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 6,751,583 by Clarke et al. (hereinafter referred to as “Clarke”).
Regarding claim 1, Clarke discloses:
a method for computation, the method comprising: performing a first computation using a first system, wherein the first computation comprises a time driven simulation of an application operation (Clarke discloses, at Figure 1, a processor simulator, which is a first system that performs first computations based on a first type of computation basis. Clarke also discloses, at col. 9, lines 55-61, simulating a user program, which discloses application operations. Clarke discloses, at col. 11, lines 45-53, the processor simulator and hardware simulator use different time frames. As disclosed at col. 12, lines 15-17, the processor simulator uses instruction timing, i.e., time driven simulation.);
performing a second computation using a second system, wherein the second computation comprises an event driven simulation of a device operation (Clarke discloses, at Figure 1, a hardware simulator, which is a second system that performs second computations based on a second type of computation basis. Clarke also discloses, at col. 9, lines 44-48, simulating circuitry, which discloses device operations. Clarke discloses, at col. 11, lines 45-53, the processor simulator and hardware simulator use different time frames. As disclosed at col. 12, lines 53-58, the hardware simulator uses simulation time, i.e., event driven simulation.);
determining, by the second system, a first progress of the first computation (Clarke discloses, at col. 12, lines 32-40, determining when events are performed by the processor simulator, which discloses determining a first progress of the first computation. As disclosed at col 12, line 62- col. 13, line 14, the processor simulator sends information to the hardware simulator, e.g., an event queue in the hardware simulator, which discloses the hardware simulator, i.e., the second system, determining the first progress of the processor simulator, i.e., the first system.);
determining, by the second system, a second progress of the second computation (Clarke discloses, at col. 12, lines 53-58, the hardware simulator provides a simulation time frame, which discloses the second system determining progress a second computation.); and
modifying, by the second system, based on the first progress and the second progress, a speed of the first computation (Clarke discloses, at col. 12, line 42-col. 13 line 21, synchronizing the processor simulator to the hardware simulation time, which discloses modifying the first computation based on the first progress and the second progress. Clark also discloses, Id., the synchronizing uses a suspend and resume mechanism that involves operations by both the processor simulator and the hardware simulator, i.e., the first and second systems, which disclose the modifying being by the second system and speed of the first computation being modified.).
Regarding claim 7, Clarke discloses the elements of claim 1, as discussed above. Clarke also discloses:
the second computation is performed based on a request from the first computation (Clarke discloses, at col. 12, lines 9-41, communicating event information from the processor simulator to the hardware simulator, which discloses a request to perform the second computation, i.e., an aspect of the co-simulation.); and
the second computation is performed, at least in part, in parallel with the first computation (Clarke discloses, at Figure 1 and related description, the processor simulator and the hardware simulator are both running, which discloses parallel computations.).
Regarding claim 8, Clarke discloses the elements of claim 7, as discussed above. Clarke also discloses:
notifying the first computation, by the second computation, based on a status of the request (Clarke discloses, at col. 13, lines 28-32, the hardware simulator notifying the processor simulator of a result.).
Regarding claim 10, Clarke discloses the elements of claim 1, as discussed above. Clarke also discloses:
wherein the performing the first computation comprises performing the first computation using a performance scale factor (Clarke discloses, at col. 12, lines 9-41, adding delay, which discloses using a performance scaling factor. As disclosed at col. 12, lines 42-43, this is because the processor simulator typically operates much faster than the hardware simulator.).
Regarding claim 11, Clarke discloses the elements of claim 1, as discussed above. Clarke also discloses:
wherein the performing the first computation comprises simulating a clock (Clarke discloses, at col. 10, lines 22-32, simulating timing information, i.e., a clock.).
Regarding claim 13, Clarke discloses:
a system comprising: a first computation system configured to perform a first computation, wherein the first computation comprises a time driven simulation of an application operation (Clarke discloses, at Figure 1, a processor simulator, which is a first system that performs first computations based on a first type of computation basis. Clarke also discloses, at col. 9, lines 55-61, simulating a user program, which discloses application operations. Clarke discloses, at col. 11, lines 45-53, the processor simulator and hardware simulator use different time frames. As disclosed at col. 12, lines 15-17, the processor simulator uses instruction timing, i.e., time driven simulation.);
a second computation system configured to perform a second computation, wherein the second computation comprises an event driven simulation of a device computation (Clarke discloses, at Figure 1, a hardware simulator, which is a second system that performs second computations based on a second type of computation basis. Clarke also discloses, at col. 9, lines 44-48, simulating circuitry, which discloses device operations. Clarke discloses, at col. 11, lines 45-53, the processor simulator and hardware simulator use different time frames. As disclosed at col. 12, lines 53-58, the hardware simulator uses simulation time, i.e., event driven simulation.);
determine, by the second computation system, a first progress of the first computation (Clarke discloses, at col. 12, lines 32-40, determining when events are performed by the processor simulator, which discloses determining a first progress of the first computation. As disclosed at col 12, line 62- col. 13, line 14, the processor simulator sends information to the hardware simulator, e.g., an event queue in the hardware simulator, which discloses the hardware simulator, i.e., the second system, determining the first progress of the processor simulator, i.e., the first system.);
determine, by the second computation system, second progress of the second computation (Clarke discloses, at col. 12, lines 53-58, the hardware simulator provides a simulation time frame, which discloses the second system determining progress a second computation.); and
wherein the second computation system is configured to modify, based on the first progress and the second progress, a speed of the first computation (Clarke discloses, at col. 12, line 42-col. 13 line 21, synchronizing the processor simulator to the hardware simulation time, which discloses modifying the first computation based on the first progress and the second progress. Clark also discloses, Id., the synchronizing uses a suspend and resume mechanism that involves operations by both the processor simulator and the hardware simulator, i.e., the first and second systems, which disclose the modifying being by the second system and speed of the first computation being modified.).
Regarding claim 14, Clarke discloses the elements of claim 13, as discussed above. Clarke also discloses:
wherein the first computation system comprises an emulator (Clarke discloses, at col. 3, lines 33-45, using an emulator.); and
the second computation system comprises a device simulator (Clarke discloses, at col. 9, lines 44-48, simulating circuitry, which discloses a device simulation.).
Regarding claim 16, Clarke discloses the elements of claim 13, as discussed above. Clarke also discloses:
wherein the first computation system comprises a proxy configured to: communicate with the second computation system; and send a request to the second computation system (Clarke discloses, at Figure 1, the processor simulator includes a communication mechanism to send messages to the hardware simulator.).
Regarding claim 17, Clarke discloses the elements of claim 13, as discussed above. Clarke also discloses:
the second computation system comprises a flow generator configured to communicate with the first computation system (Clarke discloses, at Figure 1 and related description, the hardware simulator includes a communication mechanism to communicate with the processor simulator.).
Regarding claim 18, Clarke discloses the elements of claim 17, as discussed above. Clarke also discloses:
the second computation system is configured to perform the second computation based on a request from the first computation system (Clarke discloses, at col. 12, lines 9-41, communicating event information from the processor simulator to the hardware simulator, which discloses a request to perform the second computation, i.e., an aspect of the co-simulation.); and
the second computation is performed, at least in part, in parallel with the first computation (Clarke discloses, at Figure 1 and related description, the processor simulator and the hardware simulator are both running, which discloses parallel computations.).
Regarding claim 19, Clarke discloses:
a system comprising: a processor configured to perform a first computation, wherein the first computation comprises a time driven simulation of an application operation (Clarke discloses, at Figure 1, a processor simulator, which is a first system that performs first computations based on a first type of computation basis. Clarke also discloses, at col. 9, lines 55-61, simulating a user program, which discloses application operations. Clarke discloses, at col. 11, lines 45-53, the processor simulator and hardware simulator use different time frames. As disclosed at col. 12, lines 15-17, the processor simulator uses instruction timing, i.e., time driven simulation.); and
a coordination system configured perform, by the computation system, a first determination of a progress of the first computation (Clarke discloses, at col. 12, lines 32-40, determining when events are performed by the processor simulator, which discloses determining a first progress of the first computation. As disclosed at col 12, line 62- col. 13, line 14, the processor simulator sends information to the hardware simulator, e.g., an event queue in the hardware simulator, which discloses the hardware simulator, i.e., the second system, determining the first progress of the processor simulator, i.e., the first system.);
perform, by the computation system, a second determination of a progress of a second computation, wherein the second computation comprises an event driven simulation of a device operation performed on a computation system (Clarke discloses, at col. 12, lines 53-58, the hardware simulator provides a simulation time frame, which discloses the second system determining progress a second computation. Clarke discloses, at Figure 1, a hardware simulator, which is a second system that performs second computations based on a second type of computation basis. Clarke also discloses, at col. 9, lines 44-48, simulating circuitry, which discloses device operations. Clarke discloses, at col. 11, lines 45-53, the processor simulator and hardware simulator use different time frames. As disclosed at col. 12, lines 53-58, the hardware simulator uses simulation time, i.e., event driven simulation.); and
perform a modification operation, based on the first progress and the second progress, wherein the modification operation is controlled by the computation system and comprises modifying a speed of the first computation (Clarke discloses, at col. 12, line 42-col. 13 line 21, synchronizing the processor simulator to the hardware simulation time, which discloses modifying the first computation based on the first progress and the second progress. Clark also discloses, Id., the synchronizing uses a suspend and resume mechanism that involves operations by both the processor simulator and the hardware simulator, i.e., the first and second systems, which disclose the modifying being by the second system and speed of the first computation being modified.).
Regarding claim 20, Clarke discloses the elements of claim 19, as discussed above. Clarke also discloses:
wherein: the first computation comprises a synthesized clock; the second computation comprises an event; and the coordination system comprises a ticker configured to coordinate the synthesized clock with the event (Clarke discloses, at col. 11, lines 45-53, the processor simulator and hardware simulator use different time frames and synchronizing the times, which discloses a ticker, i.e., counter as disclosed also at col. 18, lines 19-27. As disclosed at col. 12, lines 15-17, the processor simulator uses instruction timing, i.e., clock basis, and at col. 12, lines 53-58, the hardware simulator uses simulation time, i.e., event basis.).
Regarding claim 21, Clarke discloses the elements of claim 19, as discussed above. Clarke also discloses:
the second computation system is configured to perform the second computation based on a request from the first computation system (Clarke discloses, at col. 12, lines 9-41, communicating event information from the processor simulator to the hardware simulator, which discloses a request to perform the second computation, i.e., an aspect of the co-simulation.); and
the second computation is performed, at least in part, in parallel with the first computation (Clarke discloses, at Figure 1 and related description, the processor simulator and the hardware simulator are both running, which discloses parallel computations.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Clarke.
Regarding claim 9, Clarke discloses the elements of claim 7, as discussed above. Clarke does not explicitly disclose wherein the aforementioned request is transferred from the first computation to the second computation, at least in part, using a shared memory.
However, Clarke discloses:
shared memory (Clarke discloses, at col. 15, lines 14-15, shared memory.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Clarke to use the shared memory in transferring the request from the first computation to the second computation because using shared memory is one well-known way to efficiently transfer information between entities.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Clarke in view of US Patent No. 7,013,456 by Van Dyke et al. (hereinafter referred to as “Van Dyke”).
Regarding claim 15, Clarke discloses the elements of claim 14, as discussed above. Clarke does not explicitly disclose wherein: the emulator comprises a software emulator; and the device simulator comprises a hardware virtual machine configured to operate the software emulator.
However, in the same field of endeavor (e.g., emulation) Van Dyke discloses:
a software emulator and a hardware virtual machine (Van Dyke discloses, at col. 17, lines 35-40, a software emulator. Van Dyke also discloses, at col. 20, lines 43-46, a virtual machine.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Clarke to utilize software emulation and hardware virtual machines, as disclosed by Van Dyke, because these are known tools to enable testing and access to instructions and functionality from various instruction sets and computers. See Van Dyke, col. 1, line 65-col. 2, line 4.
Response to Arguments
On pages 8-9 of the response filed November 26, 2025 (“response”), the Applicant argues, “An example embodiment of the method recited in amended claim 1 is described with respect to Figs. 5 and 6 in which the ticker 548 at the event driven simulator 522 may keep track of the progress 660 of the emulator 502 and/or the progress 662 of the event driven simulator 522 and modify the speed of the emulator 502 based on the first progress and the second progress. (See, e.g., paragraphs [0070] through [0072].) In contrast, Clarke appears to disclose a system in which neither the processor simulator 107 nor the hardware simulator 103 illustrated in Figs. 1 and 2 may keep track of the progress of both simulators. Instead, Clarke appears to disclose simulators 107 and 103 that are unaware of the progress of other simulators, other than being notified when the other simulator is requesting a task or has completed a task. (See, e.g., column 13, lines 22-46.) As best understood by Applicant's Representative, during the interview, the Examiner noted that column 13, line 27 of Clarke appears to mention synchronization of the processor simulator is 107 and the hardware simulator 103. However, this passage of Clarke appears to indicate that the processor simulator is 107 and the hardware are synchronized when there is no work for the hardware simulator 103 to perform. (See, e.g., column 13, lines 36-39:"the processor Simulator is already in time Synchronization with the hardware simulator and does not have any internal events that need to be processed.")”
Though fully considered, the Examiner respectfully disagrees. The Applicant’s arguments note that the hardware simulator is notified when the processor is requesting a task or has completed a task. These are indicia of progress and disclose the claimed determining progress of the first computation. As the second computation is run on the second system, it is implicit that the second system determines progress of the second computation. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 9-10 of the response the Applicant argues, “Without acquiescing in the grounds of rejection, claim 7 is amended to recite, inter alia, that "the second computation is performed based on a request from the first computation; and the second computation is performed, at least in part, in parallel with the first computation" (emphasis added, deletions omitted). An example embodiment of the method recited in amended claim 1 is described with respect to Figs. 5 and 6. Referring to Fig. 5, the second computation at event driven simulator 522 may be performed based on a request 520a from the first computation at emulator 502. (See, e.g., paragraphs [0058] and [0064].) Referring to Fig. 6, the second computation 662 may be performed, at least in part, in parallel with the first computation 660 (e.g., between the beginning of Epoch 0 and time tl). (See, e.g., paragraphs [0070] through [0072].) Thus, in the method recited in claim 7, a second computation may be performed in parallel with a first simulation from which it received a request. In contrast, Clarke appears to disclose a system in which the processor simulator 107 is suspended while the hardware simulator 103 processes event information received from the processor simulator 107. (Column 13, lines 22-34.) Clarke does not appear to disclose hardware simulator 103 operating in parallel with a processor simulator 107 from which it received event information.”
Though fully considered, the Examiner respectfully disagrees. As disclosed, e.g., at col. 11, lines 45-53, the hardware simulator and processor simulator each have their own definition of time, and the two synchronize when ever they need to communicate. This discloses that both simulators are operating at the same time, which discloses the claimed parallel computations. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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