Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election with traverse of Embodiment of Figs. 1-3 (Claim 1-8 and 15-19) in the reply filed on 12/08/2025 is acknowledged.
The traversal is on the ground(s) that:
Examination can be made without a burden, as the identified species include similar limitations.
These reasons are not found persuasive because:
Restriction by species require the distinction if they are patentably independent or distinct (see MPEP § 806.04) as a burden. Each species require different and separate search strategies for their distinctiveness. Each patentable distinct species invention may have similar features, but do not share everything in common, therefore it is a burden to locate each different distinct features in each set of distinct claimed invention, a serious searching burden on the examiner. Thus, separate searches are required.
The requirement is still deemed proper and is therefore made FINAL.
Claim 20 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/08/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/04/2022 and 03/29/2022. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US 2012/0056316) in view of Chen et al. (US 20180122780) and Su et al. (US 2017/013335).
As for claims 1-3 and 15-17, Pagaila et al. disclose in Figs. 3a-6 and the related text a packaged Integrated Circuit (IC) comprising:
a fanout layer 182/184 including conductive lines (horizontal portion of 182) and conductive vias (vertical portion of 182);
a processor 124a [0042] having a first (lower) surface residing substantially adjacent a first surface of the fanout layer (Fig. 6);
a Redistribution Layer (RDL) 164 having a first (lower) surface coupled to a second (upper) surface of the processor (Fig. 6);
a memory 124b [0042] coupled to a second (upper) surface of the RDL, wherein a first (right) portion of the memory is disposed outside of a footprint of the processor and a second (left) portion of the memory is disposed within the footprint of the processor (Fig. 6);
an (first) encapsulant 170 surrounding a portion of the memory, the RDL, and the processor, the encapsulant 170 contacting the fanout layer on a first (lower) side and having an exposed second (upper) side;
a first plurality of conductive posts 166 (electrically) coupled between the fanout layer 182/184 and the RDL 164 through a portion of the encapsulant disposed beneath the first portion of the memory proximate a first side of the processor (Fig. 6); and
a (first) plurality of Through Mold Vias (TMVs) 144c/170 extending between the fanout layer and the exposed second side of the encapsulant (Fig. 6) or extend from the fanout layer through the first encapsulant (Fig. 6).
Pagaila et al. do not disclose a second plurality of conductive posts coupled between the fanout layer and conductive features of the RDL through a portion of the encapsulant that is proximate a second side of the processor, the conductive features of the RDL coupled to power inputs of the second portion of the memory, wherein the second plurality of conductive posts are further coupled between the fanout layer and conductive features of the RDL through a portion of the encapsulant that is proximate at least a third side of the processor; and a third plurality of conductive posts (left 624) coupled between the fanout layer and the RDL through a portion of the encapsulant that is proximate the first side of the processor, the third plurality of conductive posts coupled, via the RDL, to power inputs of the first portion of the memory.
Su et al. teach in Figs. 2-3 and the related text a second plurality of conductive posts (outer 222) coupled between the fanout layer 212/220 and conductive features of the RDL (middle 220) through a portion of the encapsulant 208s/208b that is proximate a second side of the chip (processor) 204, the conductive features of the RDL (middle 220) (electrically) coupled to power inputs of the second (right) portion of the chip (memory) 202, wherein the second plurality of conductive posts (outer 222) are further coupled between the fanout layer 212/220 and conductive features of the RDL (middle 220) through a portion of the encapsulant 208a/208b that is proximate at least a third side of the processor 202 (Fig. 2-3); and a third plurality of conductive posts (inner 222) coupled between the fanout layer and the RDL 212/220 through a portion of the encapsulant 208a/208b that is proximate the first (upper) side of the chip (processor) 202, the third plurality of conductive posts (inner 222) coupled, via the RDL (middle 220), to power inputs of the first (left) portion of the memory 204 (Fig. 2-3).
Chen et al. teach in Fig. 2A-2H and the related text a second plurality of conductive posts 210 coupled between the fanout layer 260 and conductive features 248a of the 180/190 through a portion of the encapsulant 250 that is proximate a second side of the chip (processor), the conductive features 138 of the RDL 138/139 (electrically) coupled to power inputs of the second (right) portion of the chip (memory) 202, wherein the second plurality of conductive posts 210 are further coupled between the fanout layer 260 and conductive features of the RDL 38/39 through a portion of the encapsulant 250 that is proximate at least a third side of the chip (processor) 34 (Fig. 2H).
Su teach in Fig 13 and the related text a third plurality of conductive posts 32 coupled between the fanout layer 50/52 and the RDL 92/94 through a portion of the encapsulant 48 that is proximate the first (upper) side of the chip (processor) 34, the third plurality of conductive posts 32 coupled, via the RDL, to power inputs of the first (left) portion of the chip (memory) 234 (Fig. 13).
Pagaila et al., Chen et al. and Su are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pagaila et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Pagaila et al., to include the limitations as taught by Su et al. and Chen et al. in order to improve interconnections.
The limitation of “the first plurality of conductive posts providing data communication links between the processor and the memory via the fanout layer and the RDL” has not been given patentable weight because it is considered to be intended use and/or functional language. This type of description does not affect the structure of the final device. It is respectfully noted that intended use and/or other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Pagaila et al. teach the (first) plurality of conductive posts having the same structure as claimed invention, therefore it is capable to have the first plurality of conductive posts providing data communication links between the processor and the memory via the fanout layer and the RDL.
As for claims 4 and 16, Pagaila et al. and Chen et al. disclosed the packaged IC of claim 1, Pagaila et al. further disclose the processor is one or more of a graphics processing unit, a communications processor, or an application specific processor [0033].
As for claims 5 and 18, Pagaila et al. and Chen et al. disclosed the packaged IC of claim 1, Pagaila et al. further disclose a dummy silicon substrate (upper 124a) disposed adjacent the memory (Fig. 3b, [0041]).
As for claim 6, Pagaila et al. and Chen et al. disclosed the packaged IC of claim 1, Pagaila et al. further comprising: a ball grid array 186 coupled to the plurality of TMVs 150; and Package on Package (POP) memory coupled to the ball grid array (Fig. 6).
As for claim 7, Pagaila et al. and Chen et al. disclosed the packaged IC of claim 6, Pagaila et al. further disclose wherein the memory is a high bandwidth memory relative to the POP memory.
As for claim 8, Pagaila et al. and Chen et al. disclosed the packaged IC of claim 6, Pagaila et al. further disclose a PCB ball grid array 186 coupled to a second surface of the fanout layer (Fig. 6).
As for claim 19, Pagaila et al. and Chen et al. disclosed the packaged IC of claim 15, Pagaila et al. further disclose a ball grid array 186 coupled to the second plurality of TMVs 150; and Package on Package (POP) memory coupled to the ball grid array (Fig. 6).
Conclusion
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811