DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on October 17, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4, 6-9, 14, and 17-23 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2015/0014641 A1 to Jung et al. (“Jung”) in view of U.S. Patent Application Publication No. 2008/0197778 A1 to Kubota (“Kubota”), and U.S. Patent Application Publication No. 2013/0009162 A1 to Kang (“Kang”). As to claim 1, although Jung discloses a display device, comprising: a substrate (110) on which a display area (at 1) and a non-display area (outside 1) are defined; a switching thin film transistor (T2) on the substrate (110), the switching thin film transistor (T2) comprising a first gate electrode (125b), a first source electrode (176b) and a first drain electrode (177b); a driving thin film transistor (T1, T6) on the substrate (110), the driving thin film transistor (T1, T6) comprising a second gate electrode (125a, 125f), a second source electrode (176a, 176f) and a second drain electrode (177a, 177f); a cathode electrode (270) covering a plurality of pixel areas (1) in the display area (at 1); a passivation layer (160); a light emitting diode (70) comprising an anode electrode (at 81, 191), a light emission layer (370) and the cathode electrode (270) in a portion of the display area (at 1); and a bank (180, 350) disposed on the anode electrode (at 81, 191) and exposing at least a portion of the anode electrode (at 81, 191), wherein: the cathode electrode (270) extends from the display area (at 1) to the non-display area (outside 1); the light emission layer (370) overlaps the second gate electrode (125a, 125f), the second source electrode (176a, 176f) and the second drain electrode (177a, 177f) of the driving thin film transistor (T1, T6); the bank (180, 350) overlaps the second gate electrode (125a, 125f), the second source electrode (176a, 176f) and the second drain electrode (177a, 177f) of the driving thin film transistor (T1, T6); at least a portion (corner portion) of the bank (180, 350) is disposed between the anode electrode (at 81, 191) and the cathode electrode (270); the anode electrode (at 81, 191) is disposed at a height (in contact with 177f at 72) above the substrate (110); at least a part (directly below 191 above 72) of the bank (180, 350) disposed above the height (in contact with 177f at 72) overlaps the first gate electrode (125b), the first source electrode (176b), and the first drain electrode (177b) of the switching thin film transistor (T2); and the switching film transistor (T2) is not directly electrically connected to the anode electrode (at 81, 191) (See Fig. 1, Fig. 2, Fig. 3, Fig. 4, ¶ 0006, ¶ 0038, ¶ 0039, ¶ 0041, ¶ 0047, ¶ 0059, ¶ 0062, ¶ 0063, ¶ 0064, ¶ 0069, ¶ 0075, ¶ 0078, ¶ 0084, ¶ 0087, ¶ 0088, ¶ 0089, ¶ 0090, ¶ 0093) (Notes: the non-display area without the light emitting diode surrounds the display area is known, where the common cathode electrode is shared amongst the plurality of pixel areas and covers the display area and the non-display area as taught by Kubota. Further, the driving thin film transistor “drives/controls” the light emitting diode. Lastly, the bank is interpreted as an insulating layer that isolates and separates adjacent elements, where the limitation “portion” is defined as a part of any whole, either separated from or integrated with it by Dictionary.com such that a corner portion of 350 in contact with 191 and 370 is between the anode electrode and the cathode electrode and the limitation “part” is defined as a portion or division of a whole that is separate or distinct; piece, fragment, fraction, or section; constituent by Dictionary.com, where the portion and the part are different areas of the bank such that the at least the part of the bank above the height overlaps the switching thin film transistor), Jung does not further disclose a gate driving integrated circuit in the non-display area for supplying scan signals to gate lines; a ground line on an outermost side of the substrate and outwardly from the gate driving integrated circuit so as to surround the substrate; the passivation layer over the ground line; and the cathode electrode overlaps with at least a portion of the gate driving integrated circuit; the cathode electrode is electrically connected directly to the ground line through a contact hole in the passivation layer; the cathode electrode directly covers all of the contact hole where the ground line is exposed; the cathode electrode is a transparent electrode. However, Kubota does disclose a gate driving integrated circuit (40, 50, 100A) in the non-display area (B) for supplying scan signals to gate lines (¶ 0045, ¶ 0049); a ground line (140, POWER SUPPLY) on an outermost side of the substrate (10) and outwardly from the gate driving integrated circuit (40, 50, 100A) so as to surround the substrate (10); the passivation layer (34) over the ground line (140, POWER SUPPLY); and the cathode electrode (72, 150b) overlaps with at least a portion of the gate driving integrated circuit (40, 50, 100A); the cathode electrode (72, 150b) is electrically connected directly to the ground line (140, POWER SUPPLY) through a contact hole in the passivation layer (34); the cathode electrode (72, 150b) directly covers all of the contact hole where the ground line (140, POWER SUPPLY) is exposed; the cathode electrode (72) is a transparent electrode (72) (See Fig. 1, Fig. 2, Fig. 3, Fig. 4, ¶ 0042-¶ 0053, ¶ 0059) and Kang also teaches the cathode electrode (63) is electrically connected directly to the ground line (64) through a contact hole in the passivation layer (58); the cathode electrode (63) directly covers all of the contact hole where the ground line (64) is exposed; the cathode electrode (63) is a transparent electrode (63) (See Fig. 1-Fig. 4, ¶ 0032, ¶ 0035, ¶ 0036, ¶ 0040, ¶ 0045, ¶ 0052, ¶ 0054-¶ 0056). In view of the teachings of Jung and Kubota and Kang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Jung to have a gate driving integrated circuit in the non-display area for supplying scan signals to gate lines; a ground line on an outermost side of the substrate and outwardly from the gate driving integrated circuit so as to surround the substrate; the passivation layer over the ground line; and the cathode electrode overlaps with at least a portion of the gate driving integrated circuit; the cathode electrode is electrically connected directly to the ground line through a contact hole in the passivation layer; the cathode electrode directly covers all of the contact hole where the ground line is exposed; the cathode electrode is a transparent electrode because the gate driving integrated circuit in the non-display area selects the light emitting diode to turn on with a corresponding luminance and the ground line supplies power of ground level to the cathode (See Jung ¶ 0047 and Kubota ¶ 0045, ¶ 0046). As to claim 4, Jung in view of Kubota and Kang further discloses wherein the ground line (140, POWER SUPPLY/64) is formed at a same layer and formed of a same material as the first and second source electrodes (176b, 176a, 176f/63/56) or the first and second drain electrodes (177b, 177a, 177f/61/57) (See Kubota ¶ 0052 and Kang ¶ 0056) such that the manufacturing process is simplified. As to claim 6, Jung in view of Kubota further discloses wherein a distance between the gate driving integrated circuit (40, 50, 100A) and the switching thin film transistor (T2/68) is shorter than a distance between the gate driving integrated circuit (40, 50, 100A) and the driving thin film transistor (T1, T6/60) (See Jung Fig. 3 and Kubota Fig. 1, Fig. 2, Fig. 4) (Notes: the switching thin film transistor is closer to the gate driving integrated circuit). As to claim 7, Jung and Kubota further disclose wherein the cathode electrode (270/72) overlaps with at least a portion of the display area (at 1/A) and a portion of the non-display area (outside 1/B) so as to be electrically connected to the ground line (140, POWER SUPPLY) on the outermost side of the substrate (110/10) (See Jung Fig. 3 and Kubota Fig. 4 ¶ 0047). As to claim 8, Jung and Kubota further disclose wherein the cathode electrode (270/72) overlaps with the display area (at 1/A) and the non-display area (outside 1/B) so as to be electrically connected to the ground line (140, POWER SUPPLY) on the outermost side of the substrate (110/10) (See Jung Fig. 3 and Kubota Fig. 4, ¶ 0047). As to claim 9, Jung further discloses wherein each of the switching thin film transistor (T2) and the driving thin film transistor (T1, T6) comprises an oxide semiconductor layer (131) (See ¶ 0059). As to claim 14, Jung in view of Kubota further discloses wherein each of the switching thin film transistor (T2/68) and the driving thin film transistor (T6/60) has a top gate structure (See Jung Fig. 4 and Kubota Fig. 4) (Notes: simultaneously formed transistors having the same top gate structures). As to claim 17, Jung in view of Kubota and Kang further discloses comprising: a planar layer (35/59), wherein: the light emitting diode (70) is configured to be driven by the driving thin film transistor (T1, T6/60); the light emission layer (370/62) overlaps the first gate electrode (125b), the first source electrode (176b) and the first drain electrode (177b) of the switching thin film transistor (T2/68); in the display area (at 1/A), the cathode electrode (270/72/63) is disposed directly over the light emission layer (370/74/62), the light emission layer (370/74/62) is disposed over the planar layer (35/59), and the planar layer (35/59) is disposed over the switching thin film transistor (T2/68) and the driving thin film transistor (T1, T6/60); and in the non-display area (outside 1/B), the cathode electrode (270/72/63) is disposed over the planar layer (35/59), and the planar layer (35/59) is disposed over the gate driving integrated circuit (40, 50, 100A) (See Jung Fig. 4, Kubota Fig. 4, ¶ 0047, ¶ 0048, ¶ 0053, ¶ 0054, and Kang Fig. 3, ¶ 0040, ¶ 0045). As to claim 18, Jung further discloses wherein: the bank (180, 350) surrounds the light emitting diode (70) in the display area (at 1); and in the display area (at 1), the cathode electrode (270) is disposed over the light emission layer (370), and the light emission layer (370) is disposed over the bank (180, 350) (See Jung Fig. 4) (Note: the bank is around and surrounds the light emitting diode). As to claim 19, although Jung discloses a display device, comprising: a substrate (110) on which a display area (at 1) and a non-display area (outside 1) are defined; a switching thin film transistor (T2) on the substrate (110), the switching thin film transistor (T2) comprising a first gate electrode (125b), a first source electrode (176b) and a first drain electrode (177b); a driving thin film transistor (T1, T6) on the substrate (110), the driving thin film transistor (T1, T6) comprising a second gate electrode (125a, 125f), a second source electrode (176a, 176f) and a second drain electrode (177a, 177f); a cathode electrode (270) covering a plurality of pixel areas (1) in the display area (at 1); a passivation layer (160); a light emitting diode (70) comprising an anode electrode (at 81, 191), a light emission layer (370) and the cathode electrode (270) in a portion of the display area (at 1); and a bank (180, 350) disposed on the anode electrode (at 81, 191) and exposing at least a portion of the anode electrode (at 81, 191), wherein: the cathode electrode (270) extends from the display area (at 1) to the non-display area (outside 1); the light emission layer (370) is disposed over the bank (180, 350); the light emission layer (370) overlaps the second gate electrode (125a, 125f), the second source electrode (176a, 176f) and the second drain electrode (177a, 177f) of the driving thin film transistor (T1, T6); the anode electrode (at 81, 191) is disposed at a height (in contact with 177f at 72) above the substrate (110); at least a part (directly below 191 above 72) of the bank (180, 350) disposed above the height (in contact with 177f at 72) overlaps the first gate electrode (125b), the first source electrode (176b), and the first drain electrode (177b) of the switching thin film transistor (T2); and the switching film transistor (T2) is not directly electrically connected to the anode electrode (at 81, 191) (See Fig. 1, Fig. 2, Fig. 3, Fig. 4, ¶ 0006, ¶ 0038, ¶ 0039, ¶ 0041, ¶ 0047, ¶ 0059, ¶ 0062, ¶ 0063, ¶ 0064, ¶ 0069, ¶ 0075, ¶ 0078, ¶ 0084, ¶ 0087, ¶ 0088, ¶ 0089, ¶ 0090, ¶ 0093) (Notes: the non-display area without the light emitting diode surrounds the display area is known, where the common cathode electrode is shared amongst the plurality of pixel areas and covers the display and the non-display area as taught by Kubota. Further, the driving thin film transistor “drives/controls” the light emitting diode. Lastly, the bank is interpreted as an insulating layer that isolates and separates adjacent elements, wherein the limitation “part” is defined as a portion or division of a whole that is separate or distinct; piece, fragment, fraction, or section; constituent by Dictionary.com, such that the at least the part of the bank above the height overlaps the switching thin film transistor), Jung does not further disclose a gate driving integrated circuit in the non-display area for supplying scan signals to gate lines; a ground line on an outermost side of the substrate and outwardly from the gate driving integrated circuit so as to surround the substrate; the passivation layer over the ground line; and the cathode electrode overlaps with at least a portion of the gate driving integrated circuit; the cathode electrode is electrically connected directly to the ground line through a contact hole in the passivation layer; the cathode electrode directly covers all of the contact hole where the ground line is exposed. However, Kubota does disclose a gate driving integrated circuit (40, 50, 100A) in the non-display area (B) for supplying scan signals to gate lines (¶ 0045, ¶ 0049); a ground line (140, POWER SUPPLY) on an outermost side of the substrate (10) and outwardly from the gate driving integrated circuit (40, 50, 100A) so as to surround the substrate (10); the passivation layer (34) over the ground line (140, POWER SUPPLY); and the cathode electrode (72, 150b) overlaps with at least a portion of the gate driving integrated circuit (40, 50, 100A); the cathode electrode (72, 150b) is electrically connected directly to the ground line (140, POWER SUPPLY) through a contact hole in the passivation layer (34); the cathode electrode (72, 150b) directly covers all of the contact hole where the ground line (140, POWER SUPPLY) is exposed (See Fig. 1, Fig. 2, Fig. 3, Fig. 4, ¶ 0042-¶ 0053) and Kang also teaches the cathode electrode (63) is electrically connected directly to the ground line (64) through a contact hole in the passivation layer (58); the cathode electrode (63) directly covers all of the contact hole where the ground line (64) is exposed (See Fig. 1-Fig. 4, ¶ 0032, ¶ 0035, ¶ 0036, ¶ 0040, ¶ 0045, ¶ 0052, ¶ 0054-¶ 0056). In view of the teachings of Jung, Kubota, and Kang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Jung to have a gate driving integrated circuit in the non-display area for supplying scan signals to gate lines; a ground line on an outermost side of the substrate and outwardly from the gate driving integrated circuit so as to surround the substrate; the passivation layer over the ground line; and the cathode electrode overlaps with at least a portion of the gate driving integrated circuit; the cathode electrode is electrically connected directly to the ground line through a contact hole in the passivation layer; the cathode electrode directly covers all of the contact hole where the ground line is exposed because the gate driving integrated circuit in the non-display area selects the light emitting diode to turn on with a corresponding luminance and the ground line supplies power of ground level to the cathode electrode (See Jung ¶ 0047 and Kubota ¶ 0045, ¶ 0046). As to claim 20, although Jung discloses a display device, comprising: a substrate (110) on which a display area (at 1) and a non-display area (outside 1) are defined; a switching thin film transistor (T2) on the substrate (110), the switching thin film transistor (T2) comprising a first gate electrode (125b), a first source electrode (176b) and a first drain electrode (177b); a driving thin film transistor (T1, T6) on the substrate (110), the driving thin film transistor (T1, T6) comprising a second gate electrode (125a, 125f), a second source electrode (176a, 176f) and a second drain electrode (177a, 177f); a cathode electrode (270) covering a plurality of pixel areas (1) in the display area (at 1); a passivation layer (160); a light emitting diode (70) comprising an anode electrode (at 81, 191), a light emission layer (370) and the cathode electrode (270) in a portion of the display area (at 1); and a bank (180, 350) disposed on the anode electrode (at 81, 191) and exposing at least a portion of the anode electrode (at 81, 191), wherein: the cathode electrode (270) extends from the display area (at 1) to the non-display area (outside 1); the cathode electrode (270) includes no layer formed at a same time as the anode electrode (at 81, 191); the light emission layer (370) overlaps the second gate electrode (125a, 125f), the second source electrode (176a, 176f) and the second drain electrode (177a, 177f) of the driving thin film transistor (T1, T6); the bank (180, 350) overlaps the second gate electrode (125a, 125f), the second source electrode (176a, 176f) and the second drain electrode (177a, 177f) of the driving thin film transistor (T1, T6); at least a portion (corner portion) of the bank (180, 350) is disposed between the anode electrode (at 81, 191) and the cathode electrode (270); the anode electrode (at 81, 191) is disposed at a height (in contact with 177f at 72) above the substrate (110); at least a part (directly below 191 above 72) of the bank (180, 350) disposed above the height (in contact with 177f at 72) overlaps the first gate electrode (125b), the first source electrode (176b), and the first drain electrode (177b) of the switching thin film transistor (T2); and the switching film transistor (T2) is not directly electrically connected to the anode electrode (at 81, 191) (See Fig. 1, Fig. 2, Fig. 3, Fig. 4, ¶ 0006, ¶ 0038, ¶ 0039, ¶ 0041, ¶ 0047, ¶ 0059, ¶ 0062, ¶ 0063, ¶ 0064, ¶ 0069, ¶ 0075, ¶ 0078, ¶ 0084, ¶ 0087, ¶ 0088, ¶ 0089, ¶ 0090, ¶ 0093) (Notes: the non-display area without the light emitting diode surrounds the display area is known, where the common cathode electrode is shared amongst the plurality of pixel areas and covers the display and the non-display area as taught by Kubota. Further, the driving thin film transistor “drives/controls” the light emitting diode. . Lastly, the bank is interpreted as an insulating layer that isolates and separates adjacent elements, where the limitation “portion” is defined as a part of any whole, either separated from or integrated with it by Dictionary.com such that a corner portion of 350 in contact with 191 and 370 is between the anode electrode and the cathode electrode and the limitation “part” is defined as a portion or division of a whole that is separate or distinct; piece, fragment, fraction, or section; constituent by Dictionary.com, where the portion and the part are different areas of the bank such that the at least the part of the bank above the height overlaps the switching thin film transistor), Jung does not further disclose a gate driving integrated circuit in the non-display area for supplying scan signals to gate lines; a ground line on an outermost side of the substrate and outwardly from the gate driving integrated circuit so as to surround the substrate; the passivation layer over the ground line; and the cathode electrode overlaps with at least a portion of the gate driving integrated circuit; the cathode electrode is electrically connected directly to the ground line through a contact hole in the passivation layer; the cathode electrode directly covers all of the contact hole where the ground line is exposed. However, Kubota does disclose a gate driving integrated circuit (40, 50, 100A) in the non-display area (B) for supplying scan signals to gate lines (¶ 0045, ¶ 0049); a ground line (140, POWER SUPPLY) on an outermost side of the substrate (10) and outwardly from the gate driving integrated circuit (40, 50, 100A) so as to surround the substrate (10); the passivation layer (34) over the ground line (140, POWER SUPPLY); and the cathode electrode (72, 150b) overlaps with at least a portion of the gate driving integrated circuit (40, 50, 100A); the cathode electrode (72, 150b) is electrically connected directly to the ground line (140, POWER SUPPLY) through a contact hole in the passivation layer (34); the cathode electrode (72, 150b) directly covers all of the contact hole where the ground line (140, POWER SUPPLY) is exposed (See Fig. 1, Fig. 2, Fig. 3, Fig. 4, ¶ 0042-¶ 0053) and Kang also teaches the cathode electrode (63) is electrically connected directly to the ground line (64) through a contact hole in the passivation layer (58); the cathode electrode (63) directly covers all of the contact hole where the ground line (64) is exposed (See Fig. 1-Fig. 4, ¶ 0032, ¶ 0035, ¶ 0036, ¶ 0040, ¶ 0045, ¶ 0052, ¶ 0054-¶ 0056). In view of the teachings of Jung, Kubota, and Kang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Jung to have a gate driving integrated circuit in the non-display area for supplying scan signals to gate lines; a ground line on an outermost side of the substrate and outwardly from the gate driving integrated circuit so as to surround the substrate; the passivation layer over the ground line; and the cathode electrode overlaps with at least a portion of the gate driving integrated circuit; the cathode electrode is electrically connected directly to the ground line through a contact hole in the passivation layer; the cathode electrode directly covers all of the contact hole where the ground line is exposed because the gate driving integrated circuit in the non-display area selects the light emitting diode to turn on with a corresponding luminance and the ground line supplies power of ground level to the cathode electrode (See Jung ¶ 0047 and Kubota ¶ 0045, ¶ 0046). As to claim 21, Jung further discloses wherein: the light emission layer (370) overlaps the first gate electrode (125b), the first source electrode (176b) and the first drain electrode (177b) of the switching thin film transistor (T2); and the cathode electrode (270) overlaps the light emission layer (370), the second gate electrode (125a, 125f), the second source electrode (176a, 176f) and the second drain electrode (177a, 177f) of the driving thin film transistor (T1, T6), and the first gate electrode (125b), the first source electrode (176b) and the first drain electrode (177b) of the switching thin film transistor (T2) (See Fig. 4). As to claim 22, Jung further discloses wherein the bank (180, 350) is adjacent to the light emitting diode (70); the bank (180, 350) has a side-end surface (in contact with 81) at an end of the bank (180, 350); the side-end surface (in contact with 81) of the bank (180, 350) is in the display area (at 1) and faces toward the non-display area (outside 1); the bank (180, 350) overlaps the second gate electrode (125a, 125f), the second source electrode (176a, 176f) and the second drain electrode (177a, 177f) of the driving thin film transistor (T1, T6), and the first gate electrode (125b), the first source electrode (176b) and the first drain electrode (177b) of the switching thin film transistor (T2); the light emission layer (370) overlaps the bank (180, 350) and overlaps the first gate electrode (125b), the first source electrode (176b) and the first drain electrode (177b) of the switching thin film transistor (T2); and the light emission layer (370) covers the side-end surface (in contact with 81) of the bank (180, 350) (See Fig. 4). As to claim 23, Jung further discloses wherein the light emission layer (370) and the bank (180, 350) are in direct contact with each other (See Fig. 4).
Response to Amendment
FIG. 11 of the Drawings shows the recess of the anode electrode filled by the bank that appears to be structurally different from FIG. 4 of Jung et al.
Further, the light emission layer overlaps the switching and driving TFTs, whereas the anode electrode only partially overlaps the driving TFT without overlapping the switching TFT.
Response to Arguments
Applicant's arguments with respect to claims 1, 19, and 20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Prior art made of record is considered pertinent to Applicants’ disclosure; Choi (US 2013/0069853 A1). Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815