Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
This office action is in response to the communication filed on 01/08/2026.
Claims 1-25 are currently pending in the present application. Claims 1, 13 and 20 have been amended.
The amendment to the abstract has overcome the previous objection to the Specification.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4,10-15,18-22 and 25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Manipatruni et al. (US 20200134419 A1; hereinafter “Manipatruni”).
In re claim 1, Liu’663 discloses an apparatus (figs. 1-2, 7) comprising:
a first integrated circuit component 110 (¶27);
a second integrated circuit component 130 (¶27); and
an electrical interconnect 125 coupling the first integrated circuit component 110 and the second integrated circuit component 130 (¶27),
wherein the interconnect 125 comprises a repeater circuit, the repeater circuit comprising one or more spintronic logic devices 701 through 706 included in 121, 122 whose output signal is based on a spin-orbit effect of one or more materials of the device (¶25-42, 95).
In re claim 2, Liu’663 discloses the apparatus of claim 1 (figs. 1-2), wherein states of the spintronic logic devices 200 included in 121, 122 are encoded through a magnetization of one or more ferromagnetic materials 207 of the devices (¶32-33).
In re claim 3, Liu’663 discloses the apparatus of claim 1, wherein the spintronic logic devices are magnetoelectric spin orbit (MESO) logic devices (¶25-42).
In re claim 4, Liu’663 discloses the apparatus of claim 1 (figs. 1-2), wherein each spintronic logic device comprises:
an electrically conductive layer 211A (¶29);
a ferromagnetic layer 201 (¶74);
a magnetoelectric layer 206b (¶29) disposed at least partially between the electrically conductive layer 211A and the ferromagnetic layer 201;
a spin orbit coupling (SOC) material 204A (“a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt.”; ¶39); and
a non-magnetic electrical conductor 202A (¶75) at least partially between the SOC material 204A and the ferromagnetic layer 201.
In re claim 10, Liu’663 discloses the apparatus of claim 1 (figs. 10, 14, 25), wherein the interconnect 125 comprises plurality of spintronic logic devices 121, 122 (¶27).
In re claim 11, Liu’663 discloses the apparatus of claim 10 (figs. 1-2),
wherein the interconnect 125 comprises a plurality of n- channel transistors (e.g., each logic devices 121, 122 an include MESO logic 200 and MESO devices described below with reference to FIG. 2A through FIG. 8E and the MESO logic 200 comprises n- channel transistor M1) (¶27, 43),
each n-channel transistor M1- connected to a respective spintronic logic device 121, 122 to provide a supply current IDRIVE to the spintronic logic device (¶50).
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Manipatruni et al. (WO 2019139575 A1; hereinafter “Manipatruni”).
In re claim 1, Manipatruni discloses an apparatus 1600 (figs. 4A, 10) comprising:
a first integrated circuit component 1660 (¶123);
a second integrated circuit component 1640 (¶120); and
an electrical interconnect 400 embedded in the processor 1 1610 (¶116) coupling the first integrated circuit component 1660 and the second integrated circuit component 1640,
wherein the interconnect 400 comprises a repeater circuit, the repeater circuit comprising one or more spintronic logic devices whose output signal is based on a spin-orbit effect of one or more materials of the device (¶99).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu’663 as applied to claim 1 above, and further in view of Mathuriya et al. (US 11694940 B1; hereinafter “Mathuriya”).
In re claim 12, Liu’663 discloses the apparatus of claim 1 outlined above.
Liu’663 discloses each of functional units 110 and 130 can be designed to perform a specific function (¶27) but does not expressly disclose wherein the first integrated circuit component is a processor core, and the second integrated circuit component is a cache or graphics processing circuitry.
In the same field of endeavor, Mathuriya discloses an apparatus (fig. 7A) wherein the first integrated circuit component is a processor core 304, and the second integrated circuit component 701 is a cache or graphics processing circuitry (“The zoomed version of memory die 701 includes stack of memory dies including die 701 which may include memory (such as cache) and controller circuitries (e.g., row/column controllers and decoders, read and write drivers, sense amplifiers etc.). In some embodiments, circuits for controller die 701 are implemented as ferroelectric or paraelectric logic (e.g., majority, minority, and/or threshold gates)”; C. 19, L. 9-25).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Mathuriya into the apparatus of Liu’663 to implement a system-on-chip with higher bandwidth (C. 19, L. 4-32).
Claim(s) 13-15, 18-22 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu’663 in view of Mathuriya et al. (US 11694940 B1; hereinafter “Mathuriya”).
In re claim 13, Liu’663 discloses a processor 100 (figs. 1-2) comprising:
a first integrated circuit component 110 (¶27);
a second integrated circuit component 130 (¶27); and
an interconnect 125 coupling the first integrated circuit component 110 and the second integrated circuit component 130 (¶27),
the interconnect 125 comprising a plurality of repeater circuits 701 through 706, each repeater circuit comprising a spintronic logic device 701 through 706 included in 121, 122 whose output signal is based on a spin-orbit effect of one or more materials of the device (¶25-42, 95).
Liu’663 further discloses each of functional units 110 and 130 can be designed to perform a specific function (¶27) but does not expressly disclose wherein the first integrated circuit component is a processor core, and the second integrated circuit component is a cache or graphics processing circuitry.
In the same field of endeavor, Mathuriya discloses an apparatus (fig. 7A) wherein the first integrated circuit component is a processor core 304, and the second integrated circuit component 701 is a cache or graphics processing circuitry (“The zoomed version of memory die 701 includes stack of memory dies including die 701 which may include memory (such as cache) and controller circuitries (e.g., row/column controllers and decoders, read and write drivers, sense amplifiers etc.). In some embodiments, circuits for controller die 701 are implemented as ferroelectric or paraelectric logic (e.g., majority, minority, and/or threshold gates)”; C. 19, L. 9-25).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Mathuriya into the apparatus of Liu’663 to implement a system-on-chip with higher bandwidth (C. 19, L. 4-32).
In re claim 14, Liu’663 as modified by Mathuriya discloses the processor of claim 13 outlined above.
Liu’663 further discloses in figs. 1-2, wherein states of the spintronic logic devices 200 included in 121, 122 are encoded through a magnetization of one or more ferromagnetic materials 207 of the devices (¶32-33).
In re claim 15, Liu’663 as modified by Mathuriya discloses the processor of claim 13 outlined above.
Liu’663 further discloses in figs. 1-2, wherein the spintronic logic devices are magnetoelectric spin orbit (MESO) logic devices (¶25-42).
In re claim 18, Liu’663 as modified by Mathuriya discloses the processor of claim 13 outlined above.
Liu’663 further discloses in figs. 1-2, wherein the interconnect 125 comprises a plurality of n- channel transistors (e.g., each logic devices 121, 122 an include MESO logic 200 and MESO devices described below with reference to FIG. 2A through FIG. 8E and the MESO logic 200 comprises n- channel transistor M1) (¶27, 43),
each n-channel transistor M1- connected to a respective spintronic logic device 121, 122 to provide a supply current IDRIVE to the spintronic logic device (¶50).
In re claim 19, Liu’663 as modified by Mathuriya discloses the processor of claim 13, further comprising one or more of graphics processing circuitry, input-output (IO) circuitry, memory controller circuitry, and display controller circuitry coupled to the interconnect (Liu’663: 930 in fig. 9; ¶113).
In re claim 20, Liu’663 as modified by Mathuriya discloses all the limitations, same as claims 13 and 19 above.
In re claim 21, same as claim 14 above.
In re claim 22, same as claim 15 above.
In re claim 25, same as claim 18 above.
Allowable Subject Matter
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, closest prior art of record, alone or in combination, does not expressly disclose all the limitations of each of the spintronic logic devices including an electrically conductive layer; a first ferromagnetic layer; a second ferromagnetic layer; a magnetoelectric layer disposed at least partially between the electrically conductive layer and the first ferromagnetic layer; an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer; a spin orbit coupling (SOC) material; and a non-magnetic electrical conductor at least partially between the SOC material and the second ferromagnetic layer.
Dependent claim 6 is indicated allowable based on its dependency on claim 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NILUFA RAHIM/Primary Examiner, Art Unit 2893
Prosecution Insights