Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments with respect to the amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claims 21-24 have been added.
DETAILED ACTION
This action is responsive to application No. 17690358 filed on 03/09/2022.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 1-10, 12-14, 17-18 in the reply filed on 4/29/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 9, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 2023/0013047) in view of Liu et al. (US 2023/0275123).
Regarding Independent claim 1, Chou et al. teach a transistor arrangement, comprising:
a source region (Figs. 7A & 18A, element 220’ of FS2 region, paragraph 0030 discloses epitaxial semiconductor) region;
a source contact, electrically coupled to the source region, wherein the source contact includes a metal (Fig. 18A, element V3, paragraph 0074) and a semiconductor material (Fig. 18A, element 230SD, paragraph 0038-0040) in contact with the metal, the semiconductor material of the source contact has a bandgap that is smaller than a bandgap of a semiconductor material of a channel portion (paragraph 0038-0040), and
the semiconductor material of the source contact is between the metal and the source region (Fig. 18A);
a drain region (Figs. 7A & 18A, element FS3);
a drain contact (Fig. 18A, element V3), electrically coupled to the drain region; and
a channel material (Fig. 7A, element FS1, paragraph 0027) comprising a channel portion between the source region and the drain region,
wherein a width of the channel material in the channel portion is smaller than at least one of a width of the source region and a width of the drain region (Fig. 7A, paragraph 0032).
Chou et al. do not explicitly disclose wherein a semiconductor material of the source region has dopants at a concentration of at least about 5x102' dopants per cubic centimeter.
Liu et al. teach a semiconductor device comprising an epitaxial source/drain region (Fig. 21C, element 118) with dopants at a concentration of at least about 5x102' dopants per cubic centimeter (paragraph 0072), an alloy region 176 above 118 and a metal contact region 174 above 176 (Fig. 21C, paragraph 0094).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chou et al. according to the teachings of Liu et al. with the motivation to form a source and source contact region to provide interconnection.
Regarding claim 2, Chou et al. teach wherein the width of the channel material in the channel portion is less than about 90% of at least one of the width of the source region and the width of the drain region (paragraph 0032 discloses that the width of the source/drain region can be modified to optimize for contact landings. Therefore, the width of the source/drain region is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the width of the source/drain region as Chou et al. has identified the width as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the claimed width, in order to achieve the desired contact landing dimensions, as taught by Chou et al., MPEP 2144.05. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions)).
Regarding claim 3, Chou et al. teach wherein a thickness of the channel material in the channel portion is smaller than at least one of a thickness of the source region and a thickness of the drain region (paragraph 0027 discloses a thickness range for the channel with the motivation to optimize drive current. Therefore, the thickness is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness of the channel region as Chou et al. has identified the thickness as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the claimed thickness, in order to achieve the desired drive current. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions)).
Regarding claim 4, Chou et al. teach wherein the thickness of the channel material in the channel portion is less than about 90% of at least one of the thickness of the source region and the thickness of the drain region (paragraph 0027 discloses a thickness range for the channel with the motivation to optimize drive current. Therefore, the thickness is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness of the channel region as Chou et al. has identified the thickness as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the claimed thickness, in order to achieve the desired drive current. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions)).
Regarding claim 6, Chou et al. teach wherein the source contact includes a metal (paragraph 0074) and a semiconductor material (Fig. 18A, element 230SD, paragraph 0038-0040) in contact with the metal, the semiconductor material of the source contact being different from a semiconductor material of the channel portion (paragraph 0038-0040 disclose different material).
Regarding claim 9, Chou et al. teach wherein the semiconductor material of the source contact is in contact with the source region (Fig. 18A, paragraph 0038-0040).
Regarding claim 14, Chou et al. teach wherein the channel material is a fin (paragraph 0031) or a nanoribbon.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 2023/0013047) in view of Liu et al. (US 2023/0275123) and further in view of Huang et al. (US 2021/0351039).
Regarding claim 10, Chou et al. modified by Liu et al. teach all of the limitations as discussed above.
Chou et al. modified by Liu et al. do not explicitly disclose wherein the semiconductor material of the source contact has dopants at a concentration of at least about 5x1020 dopants per cubic centimeter.
Huang et al. teach a semiconductor device comprising a source contact that contact has dopants at a concentration of at least about 5x1020 dopants per cubic centimeter (paragraph 0057).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chou et al. and Liu et al. according to the teachings of Huang et al. with the motivation to optimize the conductivity of the contact.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 2023/0013047) in view of Liu et al. (US 2023/0275123) and further in view of Gardner et al. (US 2021/0043516).
Regarding claim 12, Chou et al. modified by Liu et al. teach all of the limitations as discussed above.
Chou et al. modified by Liu et al. do not explicitly disclose wherein the channel portion includes a semiconductor material having an average grain size larger than about 1 millimeter.
Gardner et al. teach a semiconductor device with a channel region wherein the channel region has a range for the grain size to provide a desired crystal orientation (paragraph 0006 & 0093). Therefore, the grain size is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the grain size of the channel region as Gardner et al. has identified the grain size as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the claimed grain size, in order to achieve the desired crystal orientation. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions.
Regarding claim 13, Chou et al. modified by Liu et al. teach all of the limitations as discussed above.
Chou et al. modified by Liu et al. do not explicitly disclose wherein the channel portion includes a semiconductor material having an average grain size smaller than about 1 millimeter.
Gardner et al. teach a semiconductor device wherein the channel portion includes a semiconductor material having an average grain size smaller than about 1 millimeter (paragraph 0093).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chou et al. according to the teachings of Gardner et al. with the motivation to provide a desired crystal orientation (paragraph 0006).
Claims 17-18, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 2023/0013047) in view of Liu et al. (US 2023/0275123) and further in view of Bae et al. (US 2023/0093076).
Regarding Independent claim 17, Chou et al. teach an integrated circuit (IC) package, comprising:
an IC die (Fig. 1A, element 100), comprising a transistor (paragraph 0017), the transistor including:
a source region (Figs. 7A & 18A, element 220’ of FS2 region, paragraph 0030 discloses epitaxial semiconductor),
a source contact, electrically coupled to the source region, wherein the source contact includes a metal (Fig. 18A, element V3, paragraph 0074) and a semiconductor material (Fig. 18A, element 230SD, paragraph 0038-0040) in contact with the metal, the semiconductor material of the source contact has a bandgap that is smaller than a bandgap of a semiconductor material of a channel portion (paragraph 0038-0040), and the semiconductor material of the source contact is between the metal and the source region (Fig. 18A),
a drain region (Figs. 7A & 18A, element FS3),
a drain contact (Fig. 18A, element V3), electrically coupled to the drain region, and
a channel material (Fig. 7A, element FS1, paragraph 0027) comprising the channel portion between the source region and the drain region,
wherein a width of the channel material in the channel portion is smaller than at least one of a width of the source region and a width of the drain region (Fig. 7A, paragraph 0032).
Chou et al. do not explicitly disclose wherein a semiconductor material of the source region has dopants at a concentration of at least about 5x102' dopants per cubic centimeter, and a further component, coupled to the IC die.
Liu et al. teach a semiconductor device comprising an epitaxial source/drain region (Fig. 21C, element 118) with dopants at a concentration of at least about 5x102' dopants per cubic centimeter (paragraph 0072), an alloy region 176 above 118 and a metal contact region 174 above 176 (Fig. 21C, paragraph 0094).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chou et al. according to the teachings of Liu et al. with the motivation to form a source and source contact region to provide interconnection.
Chou et al. modified by Liu et al. do not explicitly disclose a further component, coupled to the IC die.
Bae et al. teach a semiconductor device comprising a capacitor (Fig. 8, element 310) coupled to a transistor capacitor (Fig. 8, element 350) via a drain contact (Fig. 8, element 301).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chou et al. and Liu et al. according to the teachings of Bae et al. with the motivation to provide a ferroelectric electronic device capable of quantitatively monitoring and/or controlling a defect in an insulating layer or an interface thereof (paragraph 0005).
Regarding claim 18, Chou et al. modified by Liu et al. and Bae et al. teach wherein the further component is one of a package substrate, an interposer, or a further IC die (paragraph 0097 of Bae).
Regarding claim 24, Chou et al. teach wherein the channel material is a nanoribbon (paragraph 0015).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 2023/0013047) in view of Liu et al. (US 2023/0275123) and in view of Bae et al. (US 2023/0093076) and further in view of Huang et al. (US 2021/0351039).
Regarding claim 21, Chou et al. modified by Liu et al. and Bae et al. teach all of the limitations as discussed above.
Chou et al. modified by Liu et al. and Bae et al. do not explicitly disclose wherein the semiconductor material of the source contact has dopants at a concentration of at least about 5x1020 dopants per cubic centimeter.
Huang et al. teach a semiconductor device comprising a source contact that contact has dopants at a concentration of at least about 5x1020 dopants per cubic centimeter (paragraph 0057).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chou et al. and Liu et al. and Bae et al. according to the teachings of Huang et al. with the motivation to optimize the conductivity of the contact.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 2023/0013047) in view of Liu et al. (US 2023/0275123) and in view of Bae et al. (US 2023/0093076) and further in view of Gardner et al. (US 2021/0043516).
Regarding claim 22, Chou et al. modified by Liu et al. and Bae et al. teach all of the limitations as discussed above.
Chou et al. modified by Liu et al. and Bae et al. do not explicitly disclose wherein the channel portion includes a semiconductor material having an average grain size larger than about 1 millimeter.
Gardner et al. teach a semiconductor device with a channel region wherein the channel region has a range for the grain size to provide a desired crystal orientation (paragraph 0006 & 0093). Therefore, the grain size is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the grain size of the channel region as Gardner et al. has identified the grain size as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the claimed grain size, in order to achieve the desired crystal orientation. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions.
Regarding claim 23, Chou et al. modified by Liu et al. and Bae et al. teach all of the limitations as discussed above.
Chou et al. modified by Liu et al. and Bae et al. do not explicitly disclose wherein the channel portion includes a semiconductor material having an average grain size smaller than about 1 millimeter.
Gardner et al. teach a semiconductor device with a channel region wherein the channel region has a range for the grain size to provide a desired crystal orientation (paragraph 0006 & 0093). Therefore, the grain size is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the grain size of the channel region as Gardner et al. has identified the grain size as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the claimed grain size, in order to achieve the desired crystal orientation. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/Primary Examiner, Art Unit 2813