DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Appeal Brief
In view of the Appeal Brief filed on January 20, 2026, PROSECUTION IS HEREBY REOPENED. New grounds of rejection are set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on September 18, 2025 was considered by the Examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6, 8-14, 34, 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20150053972A1 (“Tokumaru”) in view of US20140077160A1 (“Dai”), further in view of US20220059683A1 (“Tateno”).
RE: Claim 1, Tokumaru discloses A two-dimensional material structure (100 in FIGs. 1A-1C, 2) comprising:
a first insulator (111) comprising a first dielectric material (111 is an insulating material containing oxide, [0059]; As an insulating material from which oxygen is released by heating, oxide containing oxygen at a higher proportion than oxygen in the stoichiometric composition is preferably used, [0060]; As such a material, a material containing silicon oxide is preferably used, [0061]; Accordingly, 111 is silicon oxide; Note the reference US20120235233A1 (“Nowak”) identifies silicon oxide as a dielectric material, [0033]);
a second insulator (112) provided on the first insulator and comprising a second dielectric material (112 is an insulating layer, [0062]; As the material relatively impermeable to oxygen, an insulating material such as silicon nitride or aluminum oxide can be used, [0063]; Accordingly, 112 contains silicon nitride or aluminum oxide; The reference Nowak identifies silicon nitride and aluminum oxide as a dielectric material, [0033]);
a first material film (portion of 102 on exposed surface of 111 in FIG. 2) on an exposed surface of the first insulator; and
a second material film (portion of 102 on exposed surface of 112 in FIG. 2) on an exposed surface of the second insulator.
Tokumaru does not explicitly disclose:
the first material film is a first two-dimensional material film;
the second material film is a second two-dimensional material film;
wherein the first two-dimensional material film and the second two-dimensional material film each comprise a two-dimensional material having a two-dimensional layered structure, and
the second two-dimensional material film comprises more layers of the two- dimensional material than the first two-dimensional material film.
However, Tokumaru discloses The semiconductor layer 102 may contain a semiconductor such as a silicon-based semiconductor in a region where a channel is formed, [0054].
In the same field of endeavor, Dai discloses hydrogenated graphene with an increased relative bandgap is generated and can function as a semiconductor material. Further compared with a general semiconductor material, this semiconductor material has higher carrier mobility, [0048]. Dai discloses graphene is a two-dimensional material, [0048].
Dai further discloses graphene has carrier mobility far higher than silicon, and thus it is a semiconductor material of excellent properties, [0043].
Dai further discloses a channel-region graphene 207 is exposed, as shown in FIG. 5. Furthermore, for example, a hydrogenation treatment is performed on the channel-region graphene 207 by using H2 or a mixed gas of H2 and Ar gas, so as to attain a semiconductor active layer 207, [0042].
Dai further discloses The source electrode 208 contacts with the semiconductor active layer 207 and the drain electrode 206 contacts with the semiconductor active layer 207 so as to define a TFT channel, [0046]; see FIG. 9; TFT is a thin-film transistor, [0006].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use graphene as the material of the semiconductor layer 102 as taught by Dai in order to increase carrier mobility in the channel as further taught by Dai, [0043]. As a result, the material of 102 on the exposed surfaces of 111, 112 would be a two-dimensional graphene material having a two-dimensional layered structure.
Further, Tokumaru discloses One of the pair of electrodes 103 serves as a source electrode and the other serves as a drain electrode, [0057]; 105 is a gate electrode, [0051].
In the same field of endeavor, Tateno discloses the number of the atomic layers 22 of the graphene film 12 in each of the source region 24 where the source electrode 14 is located and the drain region 26 where the drain electrode 16 is located is greater than the number of the atomic layers 22 of the graphene film 12 in the channel region 28 where the gate electrode 18 is located, [0072].
Tateno further discloses The number of the atomic layers 22 in at least the region 23 a (a first region), which is at the source region 24 side, of the access region 23 (a first access region) between the source region 24 and the channel region 28 is greater than the number of the atomic layers 22 in the channel region 28. In addition, the number of the atomic layer 22 in at least the region 25 a (a second region), which is at the drain region 26 side, of the access region 25 (a second access region) between the drain region 26 and the channel region 28 is greater than the number of the atomic layers 22 in the channel region 28. This configuration reduces the sheet resistances of the access regions 23 and 25, thereby reducing the parasitic resistance [0073]. Tateno further discloses The number of the atomic layers 22 in each of the source region 24, the drain region 26, and the regions 23 a and 25 a is preferably ten or greater, and the number of the atomic layers 22 in the channel region 28 is preferably two or less, [0074] see FIG. 1.
FIG. 1 shows the number of atomic layers 22 in the region 24 under the source electrode 14 and the number of atomic layers 22 in the region 26 under the drain electrode 16 are each layer greater than the number of the atomic layers 22 in the channel region 28 directly under the gate electrode 18.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the number of layers in lefthand and righthand portions of the graphene layer 102 under the source and drain electrodes 103 (one or both portions of 102 corresponding to the claimed second two-dimensional material film) relative to the number of layers in the middle channel portion of the graphene layer 102 directly under the gate electrode 105 (corresponding to the claimed first two-dimensional material film) as taught by Tateno in order to reduce sheet resistance in the graphene layer as further taught by Tateno, [0073].
RE: Claim 2, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 1, wherein the first two-dimensional material film and the second two-dimensional material film are connected to each other (In FIG. 1B of Tokumaru, the lefthand, righthand portions of 102 are connected to the middle portion of 102; In FIG. 1 Tateno, the first two-dimensional material film in channel region 28 and the second two-dimensional material film in regions 23, 24, 25, 26 are connected to each other; Accordingly, as modified, the first two-dimensional material film and the second two-dimensional material film would be connected to each other).
RE: Claim 3, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 1, wherein the first insulator comprises a dielectric substrate comprising the first dielectric material (As modified, 111 is silicon oxide which forms a dielectric substrate comprising silicon oxide supporting at least 112, 105, 102, 103), and the second insulator comprises a dielectric layer on the first insulator (As modified, 112 comprises silicon nitride or aluminum oxide on 111).
RE: Claim 4, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 1, wherein the first dielectric material and the second dielectric material comprise different materials or materials formed by different methods (As modified, 111 is silicon oxide, 112 is silicon nitride or aluminum oxide; therefore, 111 and 112 comprise different materials).
RE: Claim 6, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 4, wherein the second dielectric material comprises Al2O3, HfO2, ZrO2, or SiO2 formed by atomic layer deposition (ALD) (As modified, 112 is aluminum oxide; Tokumaru discloses 112 is deposited by an ALD method, [0140]; ALD is atomic layer deposition, [0133]).
RE: Claim 8, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 1, wherein the two-dimensional material comprises a transition metal dichalcogenide (TMD), graphene, or black phosphorus (As modified, the two-dimensional material in 102 is graphene).
RE: Claim 9, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 1, wherein each of the first two-dimensional material film and the second two-dimensional material film comprises about ten or fewer layers (Tateno discloses The number of the atomic layers 22 in each of the source region 24, the drain region 26, and the regions 23 a and 25 a is preferably ten, [0074]; the number of the atomic layers 22 in the channel region 28 is preferably two or less, [0074]).
RE: Claim 10, Tokumaru in view of Dai, Tateno discloses A semiconductor device (100 in FIGs. 1A-1C, 2 Tokumaru) comprising:
a plurality of electrodes (103, 105, [0051], [0057]); and
the two-dimensional material structure of claim 1 (As modified, 100 includes the two-dimensional material structure of claim 1),
wherein the first insulator is a dielectric substrate comprising the first dielectric material (As modified, 111 is silicon oxide which forms a dielectric substrate comprising silicon oxide supporting at least 112, 105, 102, 103),
the second insulator (112) includes a first dielectric layer (lefthand portion of 112 in FIG. 1B in Tokumaru) and a second dielectric layer (righthand portion of 112 in FIG. 1B) spaced apart from each other on the dielectric substrate (As modified, 112 comprises silicon nitride or aluminum oxide on 111; FIG. 1B shows lefthand 112 spaced apart from righthand 112 as a portion of 102 spaces apart the lefthand portion of 112 from the righthand portion of 112),
the first dielectric layer and the second dielectric layer comprising the second dielectric material (As modified, 112 are silicon nitride or aluminum oxide),
the first two-dimensional material film is on a surface of the dielectric substrate between the first and second dielectric layers (Tokumaru FIG. 1B shows the middle portion of 102 on surface of 111 between the lefthand 112 and the righthand 112; Accordingly, as modified, the first two-dimensional material film, i.e., the middle portion of 102, would be on surface of 111 between lefthand 112 and the righthand 112),
the second two-dimensional material film includes second two-dimensional material films (lefthand portion 102, righthand portion 102 in FIG. 1B Tokumaru; the lefthand portion of 102 is between left 103 and left 112 and the righthand portion of 102 is between right 103 and right 112) respectively on a surface of the first dielectric layer and a surface of the second dielectric layer (FIG. 1B shows lefthand portion of 102 and righthand portion of 102 respectively on a surface of the lefthand 112 and a surface of the righthand 112)
the plurality of electrodes include a first electrode (lefthand 103 in FIG. 1B Tokumaru; 103 is labeled in FIGs. 1A, 2, [0051]) and a second electrode (righthand 103 in FIG. 1B) on the second two-dimensional material films (FIG. 1B shows the lefthand 103 on the lefthand portion of 102 and the righthand 103 on the righthand portion of 102), and
the plurality of electrodes further includes a third electrode (105) between the first electrode and the second electrode, and the second two-dimensional material films comprise more layers of the two-dimensional material than the first two-dimensional material film (As modified, the lefthand portion of 102 and the righthand portion of 102 comprise more layers of graphene than the middle portion of 102).
RE: Claim 11, Tokumaru in view of Dai, Tateno discloses The semiconductor device of claim 10, wherein the first two- dimensional material film and the second two-dimensional material films are connected to each other (In FIG. 1B of Tokumaru, the lefthand, righthand portions of 102 are connected to the middle portion of 102; In FIG. 1 Tateno, the first two-dimensional material film in channel region 28 and the second two-dimensional material film in regions 23, 24, 25, 26 are connected to each other; Accordingly, as modified, the first two-dimensional material film and the second two-dimensional material film would be connected to each other).
RE: Claim 12, Tokumaru in view of Dai, Tateno discloses The semiconductor device of claim 10, wherein the first two- dimensional material film forms a channel region (Tokumaru discloses 102 may contain a semiconductor in a region where a channel is formed, [0054]; Tateno discloses the middle region 28 is a channel region; Accordingly, as modified, the middle portion of 102 under gate electrode 105 would form a channel region).
RE: Claim 13, Tokumaru in view of Dai, Tateno discloses The semiconductor device of claim 10, wherein the first dielectric material and the second dielectric material comprise different materials or materials formed by different methods (As modified, 111 is silicon oxide, 112 is silicon nitride or aluminum oxide; therefore, 111 and 112 comprise different materials).
RE: Claim 14, Tokumaru in view of Dai, Tateno discloses The semiconductor device of claim 10, wherein the two-dimensional material comprises a transition metal dichalcogenide (TMD), graphene, or black phosphorus (As modified, the two-dimensional material is graphene).
RE: Claim 34, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 1, wherein the first dielectric material comprises SiO2 or Si3N4 (As modified the first dielectric material of 111 is silicon oxide which is SiO2, see definitions for “silicon oxide” and “silica” by Merriam-Webster), and the second dielectric material comprises Al2O3, HfO2, or ZrO2 (As modified the second dielectric material of 112 is aluminum oxide which is Al2O3, see definitions for “aluminum oxide” and “alumina” by Merriam-Webster).
RE: Claim 36, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 1, wherein the first two-dimensional material film is directly on the first insulator (As modified, the middle portion of 102 is directly on 111 as shown in FIG. 1B Tokumaru), the second two-dimensional material film is directly on the second insulator (As modified, the lefthand portion of 102 is directly on 112), and the second insulator is on top of the first insulator (As modified, 112 is on top of 111 as shown in FIG. 1B Tokumaru).
Claim 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumaru in view of Dai, further in view of Tateno as applied to claim 4, further in view of US20140239393 A1 (“Kuo”).
RE: Claim 5, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 4, wherein the first dielectric material comprises SiO2 (As modified, 111 is silicon oxide which is SiO2, see definitions for “silicon oxide” and “silica” by Merriam-Webster).
Tokumaru in view of Dai, Tateno does not explicitly disclose:
the first dielectric material comprising SiO2 is formed by dry thermal oxidation or the first dielectric material comprises Si3N4 formed by low-pressure chemical vapor deposition (CVD).
In the same field of endeavor, Kuo discloses the silicon oxide can be formed by, wet or dry thermal oxidation, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), other suitable methods, and/or combinations thereof, [0014].
Accordingly, before the effective filing date of the claimed invention, there was a need to select a method for depositing or forming the silicon oxide of the insulating layer 111.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the silicon oxide of the insulating layer 111 by dry thermal oxidation as this would have been obvious to try since dry thermal oxidation is one solution for forming silicon oxide identified by Kuo, and this would have had a reasonable expectation of success, see MPEP 2143.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumaru in view of Dai, further in view of Tateno as applied to claim 4, further in view of US 20190157544 A1 (“Hsu”).
RE: Claim 7, Tokumaru in view of Dai, Tateno discloses The two-dimensional material structure of claim 4, wherein the second dielectric material comprises SiO2 or Si3N4 (As modified, 112 is silicon nitride which is Si3N4; see definition for silicon nitride by Merriam-Webster’s dictionary at <https://www.merriam-webster.com/dictionary/silicon%20nitride>).
Tokumaru in view of Dai, Tateno does not explicitly disclose:
the Si3N4 is formed by plasma enhanced chemical vapor deposition (PECVD).
In the same field of endeavor, Hsu discloses the first dielectric layer 360 includes materials of silicon oxide (SiO.sub.x), silicon nitride (SiN.sub.x), silicon oxynitride (SiON), or silicon carbide (SiC), which may be formed by plasma deposition operation, such as Atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD) including plasma enhanced chemical vapor deposition (PECVD), [0035].
Accordingly, before the effective filing date of the claimed invention there was a need to determine a deposition method for the Si3N4 in layer 112.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit the silicon nitride by plasma enhanced chemical vapor deposition (PECVD) as this would have been obvious to try since PECVD is one solution for depositing silicon nitride as identified by Hsu and this would have had a reasonable expectation of success, see MPEP 2143.
Claim 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumaru in view of Dai, further in view of Tateno as applied to claim 1, further in view of KR 20200050380A (cited in IDS filed Aug. 17, 2022; hereinafter “Yun”; machine translation attached to Office Action dated December 30, 2024).
RE: Claim 33, Tokumaru in view of Dai, Tateno does not explicitly disclose The two-dimensional material structure of claim 1, wherein the first dielectric material has a lower degree of defects than the second dielectric material.
However in the same field of endeavor, Yun discloses in FIG. 3 the unevenness 200 is formed in the region where the electrode is to be formed on the substrate 100. In this case, the unevenness 200 may be formed directly on the substrate 100 or may be formed in a certain region of the surface of the dielectric film 150, [0084].
In FIG. 3, the irregularities are formed in regions of the dielectric film 150, which are underneath the electrodes 500a, 500b, [0078].
Yun further teaches the semiconductor device having improved contact resistance according to the present invention includes a substrate, an unevenness formed to correspond to a region where an electrode on the substrate is to be formed, [0026].
Further, Tokumaru discloses 111 is subjected to planarization treatment to improve the planarity of the top surface of 111, [0138].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce irregularities (i.e., defects) in the lefhand portion of the dielectric 112 and the righthand portion of the dielectric 112 which are underneath the electrodes 103 as taught by Yun in order to improve contact resistance as further taught by Yun. As a result, 112 would have a higher degree of defects than 111 and therefore the dielectric material of 111 would have a lower degree of defects than the dielectric material of 112 as 111 is planarized.
Claim 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumaru in view of Dai, further in view of Tateno as applied to claim 1, further in view of US20180350915A1 (“Shin”).
RE: Claim 38, Tokumaru in view of Dai, Tateno does not explicitly disclose The two-dimensional material structure of claim 1, wherein the first two-dimensional material film is grown on the exposed surface of the first insulator, and the second two-dimensional material film is grown on the exposed surface of the second insulator.
However, Tokumaru discloses The semiconductor film can be deposited by a sputtering method, a CVD method, [0151].
In the same field of endeavor, Shin discloses growing a graphene layer on a surface of the insulator using the PECVD process, [0020].
Shin further discloses PECVD is plasma-enhanced chemical vapor deposition, [0017].
Shin further discloses growing the first and second graphene layers 531 and 532 having different thicknesses directly respectively on the surfaces of the semiconductor substrate 511 and the insulating layer 512 by using the PECVD process, [0098] and The insulating layer 512 may include at least one material from among SiO2, SiN, SiOxNy, wherein 0<x and y<1, SiOxCy, wherein 0<x and y<1, GeOxNy, wherein 0<x and y<1, GeOxCy, wherein 0<x and y<1, Al2O3, HfO2, and ZrO2, [0085].
Shin further discloses Generally, a method of transferring a graphene layer grown via CVD process to a semiconductor substrate by using polymethyl methacrylate (PMMA) is used so as to manufacture a semiconductor device including a graphene layer. However, it is difficult to accurately form a graphene layer on a desired region as a line width of a semiconductor device is recently gradually reduced, and PMMA residue may be generated or an oxide may be formed according to a wet process, [0052].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to grow the first two-dimensional material film on the exposed surface of the first insulator 111, and to grow the second two-dimensional material film on the exposed surface of the second insulator 112 using a PECVD process as taught by Shin in order to simplify manufacturing and to prevent the need to grow the graphene on a separate substrate and transfer the graphene onto the first and second insulators 111, 112.
Claim 28, 32, 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumaru in view of Dai, further in view of Tateno.
RE: Claim 28, Tokumaru discloses A semiconductor device (100 in FIGs. 1A-1C, 2) comprising:
a substrate (101, 111) including a first dielectric material (111 is an insulating material containing oxide, [0059]; As an insulating material from which oxygen is released by heating, oxide containing oxygen at a higher proportion than oxygen in the stoichiometric composition is preferably used, [0060]; As such a material, a material containing silicon oxide is preferably used, [0061]; Accordingly, 111 is silicon oxide; Note the reference US20120235233A1 (“Nowak”) identifies silicon oxide as a dielectric material, [0033]);
a first electrode (lefthand 103 in FIG. 1B, [0051], [0057]; 103 is labeled in FIGs. 1A, 2,) and a second electrode (righthand 103 in FIG. 1B) spaced apart from each other on the substrate;
a dielectric structure (112) on the substrate, the dielectric structure including a second dielectric material (112 is an insulating layer, [0062]; As the material relatively impermeable to oxygen, an insulating material such as silicon nitride or aluminum oxide can be used, [0063]; Accordingly, 112 contains silicon nitride or aluminum oxide; The reference Nowak identifies silicon nitride and aluminum oxide as a dielectric material, [0033]),
the dielectric structure including a first dielectric layer (lefthand portion of 112 in FIG. 1) and a second dielectric layer (righthand portion of 112 in FIG. 1B) spaced apart from each other with the first dielectric layer between the substrate and the first electrode and the second dielectric layer between the substrate and the second electrode (FIG. 1B shows lefthand 112 spaced apart from righthand 112 as a portion of 102 spaces apart the lefthand portion of 112 from the righthand portion of 112; FIG. 1B shows the lefthand 112 between 101, 111 and the lefthand 103; FIG. 1B shows the righthand 112 between 101, 111 and the righthand 103);
a material film (102) on the dielectric structure;
a third electrode (105) on the material film between the first electrode and the second electrode; and
a gate insulating layer (104) extending between the third electrode and the first electrode, the second electrode, and the material film (FIG. 1B shows 104 extending between the 105 and the lefthand 103, the righthand 103, and 102),
the first dielectric material and the second dielectric material comprise different materials (111 is silicon oxide, 112 is silicon nitride or aluminum oxide; therefore, 111 and 112 comprise different materials).
Tokumaru does not explicitly disclose:
the material film is a two-dimensional material film comprising a two-dimensional material having a two-dimensional layered structure; and
wherein a thickness of the two-dimensional material film on the first dielectric layer is greater than a thickness of the two-dimensional material film on a portion of the substrate between the first dielectric layer and the second dielectric layer.
However, Tokumaru discloses The semiconductor layer 102 may contain a semiconductor such as a silicon-based semiconductor in a region where a channel is formed, [0054].
In the same field of endeavor, Dai discloses hydrogenated graphene with an increased relative bandgap is generated and can function as a semiconductor material. Further compared with a general semiconductor material, this semiconductor material has higher carrier mobility, [0048]. Dai discloses graphene is a two-dimensional material, [0048].
Dai further discloses graphene has carrier mobility far higher than silicon, and thus it is a semiconductor material of excellent properties, [0043].
Dai further discloses a channel-region graphene 207 is exposed, as shown in FIG. 5. Furthermore, for example, a hydrogenation treatment is performed on the channel-region graphene 207 by using H2 or a mixed gas of H2 and Ar gas, so as to attain a semiconductor active layer 207, [0042].
Dai further discloses The source electrode 208 contacts with the semiconductor active layer 207 and the drain electrode 206 contacts with the semiconductor active layer 207 so as to define a TFT channel, [0046]; see FIG. 9; TFT is a thin-film transistor, [0006].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use graphene as the material of the semiconductor layer 102 as taught by Dai in order to increase carrier mobility in the channel as further taught by Dai, [0043]. As a result, the material of 102 on the exposed surfaces of 111, 112 would be a two-dimensional graphene material having a two-dimensional layered structure.
Further, Tokumaru discloses One of the pair of electrodes 103 serves as a source electrode and the other serves as a drain electrode, [0057]; 105 is a gate electrode, [0051].
In the same field of endeavor, Tateno discloses the number of the atomic layers 22 of the graphene film 12 in each of the source region 24 where the source electrode 14 is located and the drain region 26 where the drain electrode 16 is located is greater than the number of the atomic layers 22 of the graphene film 12 in the channel region 28 where the gate electrode 18 is located, [0072].
Tateno further discloses The number of the atomic layers 22 in at least the region 23 a (a first region), which is at the source region 24 side, of the access region 23 (a first access region) between the source region 24 and the channel region 28 is greater than the number of the atomic layers 22 in the channel region 28. In addition, the number of the atomic layer 22 in at least the region 25 a (a second region), which is at the drain region 26 side, of the access region 25 (a second access region) between the drain region 26 and the channel region 28 is greater than the number of the atomic layers 22 in the channel region 28. This configuration reduces the sheet resistances of the access regions 23 and 25, thereby reducing the parasitic resistance [0073]. Tateno further discloses The number of the atomic layers 22 in each of the source region 24, the drain region 26, and the regions 23 a and 25 a is preferably ten or greater, and the number of the atomic layers 22 in the channel region 28 is preferably two or less, [0074] see FIG. 1.
FIG. 1 shows the number of atomic layers 22 in the region 24 under the source electrode 14 and the number of atomic layers 22 in the region 26 under the drain electrode 16 are each layer greater than the number of the atomic layers 22 in the channel region 28 directly under the gate electrode 18.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to increase the number of layers in lefthand and righthand portions of the graphene layer 102 on the lefthand and righthand portions of 112 relative to the number of layers in the middle channel portion of the graphene layer 102 directly under the gate electrode 105 as taught by Tateno in order to reduce sheet resistance in the graphene layer as further taught by Tateno, [0073]. In FIG. 1B, the middle channel portion of 102 is on a portion of 111 between the lefthand portion of 112 and the righthand portion of 112.
RE: Claim 32, Tokumaru in view of Dai, Tateno discloses The semiconductor device of claim 28, wherein the two- dimensional material comprises a transition metal dichalcogenide (TMD), graphene, or black phosphorus (As modified, the two-dimensional material of 102 comprises graphene).
RE: Claim 37, Tokumaru in view of Dai, Tateno discloses The semiconductor device of claim 28, wherein the two-dimensional material film is directly on the first dielectric layer, the second dielectric layer, and the substrate (As modified, the two-dimensional material of 102 is directly on the lefthand portion of 112, the righthand portion of 112, and 111 in Tokumaru FIG. 1B).
Claim 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumaru in view of Dai, further in view of Tateno as applied to claim 28, further in view of Shin.
RE: Claim 39, Tokumaru in view of Dai, Tateno does not explicitly disclose The semiconductor device of claim 28, wherein the two-dimensional material film is grown on the dielectric structure and the substrate.
However, Tokumaru discloses The semiconductor film can be deposited by a sputtering method, a CVD method, [0151].
In the same field of endeavor, Shin discloses growing a graphene layer on a surface of the insulator using the PECVD process, [0020].
Shin further discloses PECVD is plasma-enhanced chemical vapor deposition, [0017].
Shin further discloses growing the first and second graphene layers 531 and 532 having different thicknesses directly respectively on the surfaces of the semiconductor substrate 511 and the insulating layer 512 by using the PECVD process, [0098] and The insulating layer 512 may include at least one material from among SiO2, SiN, SiOxNy, wherein 0<x and y<1, SiOxCy, wherein 0<x and y<1, GeOxNy, wherein 0<x and y<1, GeOxCy, wherein 0<x and y<1, Al2O3, HfO2, and ZrO2, [0085].
Shin further discloses Generally, a method of transferring a graphene layer grown via CVD process to a semiconductor substrate by using polymethyl methacrylate (PMMA) is used so as to manufacture a semiconductor device including a graphene layer. However, it is difficult to accurately form a graphene layer on a desired region as a line width of a semiconductor device is recently gradually reduced, and PMMA residue may be generated or an oxide may be formed according to a wet process, [0052].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to grow the first two-dimensional material film on the first insulator 111, and to grow the second two-dimensional material film on the second insulator 112 using a PECVD process as taught by Shin in order to simplify manufacturing and to prevent the need to grow the graphene on a separate substrate and transfer the graphene onto the first and second insulators 111, 112.
Claim 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumaru in view of Dai, further in view of Tateno as applied to claim 28, further in view of Yun.
RE: Claim 31, Tokumaru in view of Dai, further in view of Tateno does not explicitly disclose The semiconductor device of claim 28, wherein the first dielectric material has a lower degree of defects compared to the second dielectric material.
However in the same field of endeavor, Yun discloses in FIG. 3 the unevenness 200 is formed in the region where the electrode is to be formed on the substrate 100. In this case, the unevenness 200 may be formed directly on the substrate 100 or may be formed in a certain region of the surface of the dielectric film 150, [0084].
In FIG. 3, the irregularities are formed in regions of the dielectric film 150, which are underneath the electrodes 500a, 500b, [0078].
Yun further teaches the semiconductor device having improved contact resistance according to the present invention includes a substrate, an unevenness formed to correspond to a region where an electrode on the substrate is to be formed, [0026].
Further, Tokumaru discloses 111 is subjected to planarization treatment to improve the planarity of the top surface of 111, [0138].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce irregularities (i.e., defects) in the lefhand portion of the dielectric 112 and the righthand portion of the dielectric 112 which are underneath the electrodes 103 as taught by Yun in order to improve contact resistance as further taught by Yun. As a result, 112 would have a higher degree of defects than 111 and therefore the dielectric material of 111 would have a lower degree of defects than the dielectric material of 112 as 111 is planarized.
Claim(s) 1, 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokumaru in view of US20180151751A1 (“Yeh”), further in view of US20160300958A1 (“Park”).
RE: Claim 1, Tokumaru discloses A two-dimensional material structure (100 in FIGs. 1A-1C, 2) comprising:
a first insulator (111) comprising a first dielectric material (111 is an insulating material containing oxide, [0059]; As an insulating material from which oxygen is released by heating, oxide containing oxygen at a higher proportion than oxygen in the stoichiometric composition is preferably used, [0060]; As such a material, a material containing silicon oxide is preferably used, [0061]; Accordingly, 111 is silicon oxide; Note the reference US20120235233A1 (“Nowak”) identifies silicon oxide as a dielectric material, [0033]);
a second insulator (112) provided on the first insulator and comprising a second dielectric material (112 is an insulating layer, [0062]; As the material relatively impermeable to oxygen, an insulating material such as silicon nitride or aluminum oxide can be used, [0063]; Accordingly, 112 contains silicon nitride or aluminum oxide; The reference Nowak identifies silicon nitride and aluminum oxide as a dielectric material, [0033]);
a first material film (portion of 102 on exposed surface of 111 in FIG. 2) on an exposed surface of the first insulator; and
a second material film (portion of 102 on exposed surface of 112 in FIG. 2) on an exposed surface of the second insulator.
Tokumaru does not explicitly disclose:
the first material film is a first two-dimensional material film;
the second material film is a second two-dimensional material film;
wherein the first two-dimensional material film and the second two-dimensional material film each comprise a two-dimensional material having a two-dimensional layered structure, and
the second two-dimensional material film comprises more layers of the two- dimensional material than the first two-dimensional material film.
However, Tokumaru discloses The semiconductor layer 102 may contain a semiconductor such as a silicon-based semiconductor in a region where a channel is formed, [0054].
In the same field of endeavor, Yeh discloses the off-state current has dramatically increased with further reduction in the channel length of a transistor, i.e., short channel effect. This effect is the major challenge of further increasing the density of transistors for transistors' channel length less than 20 nm. Reducing the thickness of channel is known as one way of suppressing short channel effect. Ultra-thin body transistors may employ ultra-thin semiconductor channel materials to suppress the short channel effect. 2D semiconductors are expected to be the channel material in ultra-thin body transistors. Two dimensional materials, such as transition metal dichalcogendies, graphene, and black phosphorus are regarded as promising candidates for transistor channels in FET devices, [0003].
Yeh further discloses the 2D material layer 204, shown in the X-cut view 200A, is formed from a 2D material and is subsequently formed into a channel, [0014], see FIG. 3.
FIG. 3 shows the 2D semiconductor channel extending from under the source contact 230 to under the gate electrode 222, and from under the gate electrode 222 to under the drain contact 230.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a two-dimensional material such as a 2D transition metal dichalcogenide (TMD) as the material of the semiconductor layer 102 as taught by 102 in order to suppress a short channel effect and/or to minimize the thickness and therefore size off the semiconductor layer 102. As a result, the material of 102 on the exposed surfaces of 111, 112 would be a two-dimensional TMD material having a two-dimensional layered structure.
In the same field of endeavor, Park discloses The 2D material layer 12 may include a first multilayer 2D material region 12 a and a second multilayer 2D material region 12 c, which each have a structure in which a plurality of layers are stacked on each other, and a channel region 12 b that includes a smaller number of layers than those of the first and second multilayer 2D material regions 12 a and 12 c, [0043], see FIG. 1.
Park further discloses The numbers of layers of the first and second multilayer 2D material regions 12 a and 12 c may be higher than the number of layers of the channel region 12 b, [0048].
Park discloses the first and second electrodes 13 and 14 do not directly contact the channel region 12 b, and may respectively contact the first and second multilayer 2D material regions 12 a and 12 c. Accordingly, contact resistance between the metal electrode and the active layer may be decreased, [0048].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to increase the number of layers in lefthand and righthand portions of the TMD layer 102 under the source and drain electrodes 103 (one or both portions of 102 corresponding to the claimed second two-dimensional material film) relative to the number of layers in the middle channel portion of the TMD layer 102 directly under the gate electrode 105 (corresponding to the claimed first two-dimensional material film) as taught by Park in order to reduce contact resistance between the electrodes 103 and the TMD layer 102 as further taught by Park, [0048].
RE: Claim 35, Tokumaru in view of Yeh, Park discloses The two-dimensional material structure of claim 1, wherein the two-dimensional material comprises a transition metal dichalcogenide (TMD) (As modified, the two-dimensional material of 102 is a transition metal dichalcogenide (TMD)).
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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