Prosecution Insights
Last updated: May 29, 2026
Application No. 17/690,399

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102
Filed
Mar 09, 2022
Priority
Sep 22, 2021 — JP 2021-154482
Examiner
REIDA, MOLLY KAY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toshiba Electronic Devices & Storage Corporation
OA Round
4 (Non-Final)
83%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
350 granted / 423 resolved
+14.7% vs TC avg
Minimal +2% lift
Without
With
+1.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
29 currently pending
Career history
454
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
76.6%
+36.6% vs TC avg
§102
14.4%
-25.6% vs TC avg
§112
5.7%
-34.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 423 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, 20, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukasawa (US Pub. 2018/0184518). Regarding independent claim 1, Fukasawa teaches a semiconductor device (Fig. 2b; para. 0071+), comprising: a semiconductor chip (200) having a first bottom surface having a first area and a first side surface (Fig. 2B); and an electrode (100) provided below the semiconductor chip, the electrode containing an electrically conductive material (metal) (para. 0072), and the electrode having a first portion having a second top surface, a second bottom surface provided on an opposite side of the second top surface, and a second side surface, and wherein the second top surface is in contact (via connection terminals 210 and pads P2) with the first bottom surface (Fig. 2B), a second portion connected to an end of the first portion, the second portion being provided diagonally downward with respect to the semiconductor chip, the second portion being protruded downward with respect to the second bottom surface first portion, and the second portion having a third top surface (Fig. 2B), and a sum of a second area of the second top surface and a third area of the third top surface being larger than the first area of the first bottom surface (Fig. 2B). Re claim 3, Fukasawa teaches an adhesive (300) in contact with the first side surface, the second side surface, and the third top surface (para. 0077). Re claim 20, Fukasawa teaches wherein the second portion protrudes from the first side surface and the second side surface in a direction that is parallel to the first bottom surface (Fig. 2B). Re claim 21, Fukasawa teaches wherein the second bottom surface extends in a direction parallel to the first bottom surface (Fig. 2B). Response to Arguments Applicant’s arguments with respect to claim(s) 1, 3, 20, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (571)272-4237. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Show 1 earlier event
Feb 13, 2025
Non-Final Rejection mailed — §102
May 12, 2025
Response Filed
May 28, 2025
Final Rejection mailed — §102
Aug 28, 2025
Request for Continued Examination
Sep 02, 2025
Response after Non-Final Action
Sep 25, 2025
Non-Final Rejection mailed — §102
Dec 26, 2025
Response Filed
Jan 13, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12635127
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FORMING THE SAME
2y 11m to grant Granted May 19, 2026
Patent 12628468
METHOD OF MANUFACTURING MICRO-LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING DISPLAY APPARATUS BY USING THE SAME
2y 10m to grant Granted May 12, 2026
Patent 12622077
IMAGE SENSOR INCLUDING JUNCTIONLESS TRANSFER TRANSISTOR
2y 6m to grant Granted May 05, 2026
Patent 12604647
DISPLAY PANEL AND DISPLAY APPARATUS
3y 10m to grant Granted Apr 14, 2026
Patent 12598736
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
3y 2m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

4-5
Expected OA Rounds
83%
Grant Probability
84%
With Interview (+1.6%)
2y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 423 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month