DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed February 27, 2026. Claims 1, 2, 11, and 18 have been amended. No claims have been added. Claims 3 and 17 have been canceled. Claims 7, 15-16, and 18-20 stand withdrawn. Currently, claims 1-2, 4-6, 8-14 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 18 is objected to because of the following informalities:
The status identifier of claim 18 reads “Currently amended” when it should read --Withdrawn - Currently amended--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Jackson et al. (US 20170345774 A1) herein after “Jackson” in view of Saito et al. (US 20160071872 A1) herein after “Saito”, Lane et al. (US 20080277765 A1) herein after “Lane” and Kweon et al. (US 20230260845 A1) herein after “Kweon”.
Regarding claim 1, Figs. 5 and 8 of Jackson discloses a semiconductor device (Fig. 8, semiconductor wafer 805, ¶ [0064]) comprising:
a die region (Fig. 8, integrated circuit die 810, ¶ [0064]) including circuitry (“Integrated circuits can include a few, many thousands, or even millions of devices”, ¶ [0023]);
a plurality of sidewalls (Fig. 8, “the jagged line 806 illustrates the outside edge of the integrated circuit following a dicing operation”, ¶ [0036]) (see Annotation 1, Fig. 8 of Jackson) defining outer edges of the semiconductor device (805); and
a scribe line region (see Annotation 1, Fig. 8 of Jackson, “Region 1”) between the sidewalls (806) and the die region (810),
the scribe line region (Region 1) including a plurality of vertical walls proximate to corner regions (see Fig. 5) of the semiconductor device (Fig. 8, crack arrest structure 824, ¶ [0065]),
the plurality of vertical walls extending at least partially through a thickness of the semiconductor device (805), each of the plurality of vertical walls (824) including at least a portion extending substantially parallel to one of the plurality of sidewalls (806) (The crack arrest structure 824 is arranged in the same way as 524 shown in Fig. 5, ¶ [0065], [0047]. Fig. 5 of Jackson shows crack arrest structure 524 made up of four vertical walls extending parallel to the edges of each integrated circuit die 510 and the scribe lines , ¶ [0046]. Therefore, the crack arrest structure 824 are substantially parallel to one of the sidewall 806.)
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Annotation 1, Fig. 8 of Jackson
Jackson fails to disclose the plurality of vertical walls absent from medial sidewall regions of the semiconductor device,
the plurality of vertical walls extending vertically into an active layer of the semiconductor device including CMOS elements; and
one or more air gaps, each air gap of the one or more air gaps disposed directly between an adjacent pair of the plurality of vertical walls.
In the similar field of endeavor of semiconductor devices, Fig. 4B of Saito discloses the plurality of vertical walls (Fig. 4B, edge seals 21b and 22b, ¶ [0082]) absent from medial sidewall regions (Fig. 4B, “The edge seals 21b and 22b are disposed, for example, in an L-shape including the intersection points N”, ¶ [0082]) of the semiconductor device (Fig. 4B, chip area 1b, ¶ [0084]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the vertical walls as disclosed by Saito, to enhance crack prevention at the dicing intersections (see Saito, ¶ [0083-0084]).
Saito fails to disclose the plurality of vertical walls extending vertically into an active layer of the semiconductor device including CMOS elements; and
one or more air gaps, each air gap of the one or more air gaps disposed directly between an adjacent pair of the plurality of vertical walls.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Lane discloses the plurality of vertical walls (Fig. 3A, crackstops 50A, ¶ [0006]) extending vertically into an active layer (Fig. 3A, active device FEOL region 14, ¶ [0004]) of the semiconductor device including CMOS elements (Fig. 3A, “The active device FEOL region 14 contains structures, e.g. CMOS FET devices”, ¶ [0004]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the vertical walls as disclosed by Lane, to prevent cracking in all layers of the device (see Lane, ¶ [0006]).
Lane fails to disclose one or more air gaps, each air gap of the one or more air gaps disposed directly between an adjacent pair of the plurality of vertical walls.
In the similar field of endeavor of semiconductor devices, Fig. 3B of Kweon discloses one or more air gaps (Fig. 3B, void VO, ¶ [0075]), each air gap of the one or more air gaps (“The void VO may be… occupied by air”, ¶ [0075])disposed directly between an adjacent pair of the plurality of vertical walls (Fig. 3B, walls made by the sidewalls of the first trench TR1, ¶ [0075]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the air gaps as disclosed by Kweon, to limit or prevent damage during the dicing process (see Kweon, ¶ [0128]).
Regarding claim 2, Jackson, Saito, Lane, and Kweon together disclose the semiconductor device of claim 1 as applied above, but Jackson, Saito and Lane fail to disclose wherein each of the one or more air gaps is configured to guide a crack along between the corresponding adjacent pair of vertical walls.
In the similar field of endeavor of semiconductor devices, Fig. 3B of Kweon discloses wherein each of the one or more air gaps (VO) configured to guide a crack along the vertical walls (“it may be possible to limit and/or prevent the horizontal crack propagation. The crack may easily pass through the cell array structure 300 via the void VO”, ¶ [0126]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the air gaps as disclosed by Kweon, to limit or prevent damage during the dicing process (see Kweon, ¶ [0128]).
Regarding claim 4, Jackson, Saito, Lane, and Kweon together disclose the semiconductor device of claim 1 as applied above, and Fig. 8 of Jackson further discloses comprising:
a seal ring (Fig. 8, scribe seal 822, ¶ [0065]) surrounding the die region (810) (“Scribe seal 822 surrounds the integrated circuit die 810”, ¶ [0065]),
wherein the plurality of vertical walls (824) comprises a same material as the seal ring (822). (“The crack arrest structure 624 is formed from the same conductor layers and at the same time as the scribe seal 622”, ¶ [0051]. The crack arrest structure 824 and scribe seal 822 are arranged in the same way as 624 and 622, ¶ [0065]. Therefore, the crack arrest structure 824 is formed from the same material as the scribe seal 822.)
Regarding claim 5, Jackson, Saito, Lane, and Kweon together disclose the semiconductor device of claim 1 as applied above, and Fig. 8 of Jackson further discloses wherein each of the plurality of vertical walls (824) comprises tungsten (“crack arrest structure 824 includes the trench vias 864 … and the trench via 866”, ¶ [0066]. “The trench vias are filled with conductive material used for via plugs, such as tungsten”, ¶ [0053]).
Claims 6, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jackson (US 20170345774 A1), Saito (US 20160071872 A1), Lane (US 20080277765 A1), and Kweon (US 20230260845 A1) in further view of Vo (US 20090039470 A1).
Regarding claim 6, Jackson, Saito, Lane, and Kweon together disclose the semiconductor device of claim 1 as applied above, but the combination fails to disclose wherein each of the plurality of vertical walls includes a chamfered corner.
In the similar field of endeavor of semiconductor manufacturing, Fig. 2 of Vo discloses wherein each of the plurality of vertical walls (Fig. 2, edge seal 20 and the crack stop 22, ¶ [0014]) includes a chamfered corner (see Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time of
effective filing of the invention to modify the crack assist structure of Jackson with the chamfered corner disclosed by Vo, to divert crack propagation at the corners away from the active area (see Vo, ¶ [0011]).
Regarding claim 8, Jackson, Saito, Lane, and Kweon together disclose the semiconductor device of claim 1 as applied above, but the combination fails to disclose wherein the portion extending substantially parallel to one of the plurality of sidewalls is a first portion, and each of the plurality of vertical walls further includes a second portion extending at an oblique angle relative to the first portion.
In the similar field of endeavor of semiconductor manufacturing, Fig. 2 of Vo discloses wherein the portion extending substantially parallel to one of the plurality of sidewalls is a first portion (see Annotation 3, Fig. 2 of Vo, “Portion A”), and each of the plurality of vertical walls further includes a second portion (see Annotation 3, Fig. 2 of Vo, “Portion B”) extending at an oblique angle relative to the first portion (“the crack stops 22, 36, 48, and 56 and edge seals 20, 34, 46, and 54 cut across the corner of the die 12-15 at approximately a 45-degree angle relative to the edge of the die 12-15”, ¶ [0020]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the first and second portion as disclosed by Vo, to divert crack propagation at the corners away from the active area (see Vo, ¶ [0011]).
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Annotation 3, Fig. 2 of Vo
Regarding claim 9, Jackson, Saito, Lane, Kweon and Vo together disclose the semiconductor device of claim 8 as applied above, Jackson, Saito, Lane, and Kweon fail to disclose wherein the oblique angle is about 45 degrees.
In the similar field of endeavor of semiconductor manufacturing, Fig. 2 of Vo discloses wherein the oblique angle is about 45 degrees (“the crack stops 22, 36, 48, and 56 and edge seals 20, 34, 46, and 54 cut across the corner of the die 12-15 at approximately a 45-degree angle relative to the edge of the die 12-15”, ¶ [0020]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the 45 degree angle as disclosed by Vo, to divert crack propagation at the corners away from the active area (see Vo, ¶ [0011]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jackson (US 20170345774 A1), Saito (US 20160071872 A1), Lane (US 20080277765 A1), and Kweon (US 20230260845 A1) in further view of Asano et al. (US 20030017644 A1) herein after “Asano”.
Regarding claim 10, Jackson, Saito, Lane, and Kweon together disclose the semiconductor device of claim 1 as applied above, and Jackson further discloses wherein the semiconductor device (805) is a memory device. (The integrated circuit chips can form “memory devices such as static random access memory (SRAM) devices or dynamic random access memory (DRAM) devices”, ¶ [0023]).
Jackson, Saito, Lane, and Kweon fail to disclose that the semiconductor device is formed on a 45-degree silicon substrate.
In the similar field of endeavor of semiconductor manufacturing, Fig. 2 of Asano discloses a semiconductor device (Fig. 2, compound semiconductor device, ¶ [0013]) formed on a 45-degree silicon substrate (Fig. 2, “the substrate is diced along a direction slanting by 45 degrees with respect to a cleavage direction”, ¶ [0014]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the semiconductor device of Jackson to include the 45-degree silicon substrate Asano, to reduce edge chipping when cutting (see Asano, ¶ [0019]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20220246549 A1) herein after “Wu” in view of Lane (US 20080277765 A1), Saito (US 20160071872 A1), and Kweon (US 20230260845 A1).
Regarding claim 11, Figs. 1C-2B of Wu disclose an intermediate semiconductor device (Fig. 1C, semiconductor wafer 100, ¶ [0019]) comprising:
a plurality of die areas (Fig. 1C, plurality of individual dies 101, ¶ [0019]), each die (Fig. 1, individual die 101, ¶ [0020]) area including a plurality of integrated circuits (Fig. 1C, device region 109, ¶ [0020]);
a scribe junction (Fig. 1C, orthogonal scribe lines 103, 105, ¶ [0020]) between proximate ones of the plurality of die areas (101), the scribe junction (103, 105) including a first scribe line (103) having a first direction (see Annotation 2, Fig. 2B of Wu, “First direction”) and a second scribe line (105) having a second direction (see Annotation 2, Fig. 2B of Wu, “Second direction”); and
a crack assist structure (Fig. 2A, crack-stop structure 107, seal ring structure 112, ¶ [0020] and [0024]) positioned at the scribe junction (103, 105), the crack assist structure (107, 112) including:
a plurality of vertical walls (Figs. 2A-2B, outer crack-stop structure 107a, inner crack-stop structure 107b, ¶ [0032]) extending at least partially through a thickness (shown in Fig. 2A) of the intermediate semiconductor device (100) proximate to corner regions (shown in Fig. 1C) of the plurality of die areas (101), wherein the plurality of walls includes a first wall running along the first direction in the first scribe line (103) and a second wall running along the second direction in the second scribe line (105) (see Annotation 2, Fig. 2B of Wu), and
a plurality of weak interface regions (Fig. 2A, second crack-stop segment 203, ¶ [0032]) coupled to the plurality of vertical walls (107a, 107b) configured to guide a crack along the plurality of vertical walls (107a, 107b).
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Annotation 2, Fig. 2B of Wu
Wu fails to disclose a plurality of vertical walls extending vertically into an active layer of the semiconductor device including CMOS elements,
the plurality of vertical walls absent from medial sidewall regions of the plurality of die areas, and
one or more air gaps, each air gap of the one or more air gaps disposed directly between an adjacent pair of the plurality of vertical walls, the one or more air gaps configured to guide a crack along between the corresponding adjacent pair of vertical walls.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Lane discloses a plurality of vertical walls (50A) extending vertically into an active layer (14) of the semiconductor device including CMOS elements (Fig. 3A, “The active device FEOL region 14 contains structures, e.g. CMOS FET devices”, ¶ [0004]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the vertical walls as disclosed by Lane, to prevent cracking in all layers of the device (see Lane, ¶ [0006]).
Lane fails to disclose the plurality of vertical walls absent from medial sidewall regions of the plurality of die areas, and
one or more air gaps, each air gap of the one or more air gaps disposed directly between an adjacent pair of the plurality of vertical walls, the one or more air gaps configured to guide a crack along between the corresponding adjacent pair of vertical walls.
In the similar field of endeavor of semiconductor devices, Fig. 4B of Saito discloses the plurality of vertical walls (21b, 22b) absent from medial sidewall regions (Fig. 4B, “The edge seals 21b and 22b are disposed, for example, in an L-shape including the intersection points N”, ¶ [0082]) of the plurality of die areas (Fig. 4B shows a plurality of chip areas 1b).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the vertical walls as disclosed by Saito, to enhance crack prevention at the dicing intersections (see Saito, ¶ [0083-0084]).
Saito fails to disclose one or more air gaps, each air gap of the one or more air gaps disposed directly between an adjacent pair of the plurality of vertical walls, the one or more air gaps configured to guide a crack along between the corresponding adjacent pair of vertical walls.
In the similar field of endeavor of semiconductor devices, Fig. 3B of Kweon discloses one or more air gaps (VO), each air gap of the one or more air gaps disposed directly between an adjacent pair of the plurality of vertical walls (TR1), the one or more air gaps (VO) configured to guide a crack between the corresponding adjacent pair of vertical walls (“it may be possible to limit and/or prevent the horizontal crack propagation. The crack may easily pass through the cell array structure 300 via the void VO”, ¶ [0126]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the air gaps as disclosed by Kweon, to limit or prevent damage during the dicing process (see Kweon, ¶ [0128]).
Regarding claim 12, Wu, Lane, Saito, and Kweon together disclose the intermediate semiconductor device of claim 11 as applied above, and Fig. 1C of Wu further discloses wherein the first direction and the second direction are orthogonal (Fig. 1C, “the individual dies 101 are separated from one another by “dicing” the semiconductor wafer along orthogonal scribe lines”, ¶ [0020]).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20220246549 A1), Lane (US 20080277765 A1) Saito (US 20160071872 A1), and Kweon (US 20230260845 A1) in further view of in view of Vo (US 20090039470 A1).
Regarding claim 13, Wu, Lane, Saito, and Kweon together disclose the intermediate semiconductor device of claim 11 as applied above, and Fig. 2B of Wu further discloses wherein at least a subset of the plurality of vertical walls (107a, 107b) comprises:
a first portion running in the first direction (see Annotation 2, Fig. 2B of Wu, “First direction”);
a second portion running in the second direction (see Annotation 2, Fig. 2B of Wu, “Second direction”).
Wu, Lane, Saito, and Kweon fail to disclose a third portion joining the first and second portions to form a chamfered corner.
In the similar field of endeavor of semiconductor manufacturing, Fig. 2 of Vo discloses a first portion running in the first direction (see Annotation 3, Fig. 2 of Vo, “Portion A”);
a second portion running in the second direction (see Annotation 3, Fig. 2 of Vo, “Portion C”); and
a third portion joining the first and second portions to form a chamfered corner (see Annotation 3, Fig. 2 of Vo, “Portion B”).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the chamfered corner disclosed by Vo, to divert crack propagation at the corners away from the active area (see Vo, ¶ [0011]).
Regarding claim 14, Wu, Lane, Saito, and Kweon together disclose the intermediate semiconductor device of claim 11 as applied above, and Fig. 2B of Wu further discloses wherein at least a subset of the plurality of vertical walls (107a, 107b) comprises:
a first portion running in the first direction or the second direction (see Annotation 2, Fig. 2B of Wu, “First direction”).
Wu, Lane, Saito, and Kweon fail to disclose a second portion running in a third direction at an angle 45 degrees relative to the first portion.
In the similar field of endeavor of semiconductor manufacturing, Fig. 2 of Vo discloses a second portion (see Annotation 3, Fig. 2 of Vo, “Portion B”) running in a third direction at an angle 45 degrees relative to the first portion (“the crack stops 22, 36, 48, and 56 and edge seals 20, 34, 46, and 54 cut across the corner of the die 12-15 at approximately a 45-degree angle relative to the edge of the die 12-15”, ¶ [0020]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the crack assist structure of Jackson with the 45 degree angle as disclosed by Vo, to divert crack propagation at the corners away from the active area (see Vo, ¶ [0011]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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