Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/09/2026 has been entered.
Claims 1-11, 21-31 are presented for the examination.
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ash( US 20040059870 A1) in view of DORSEY(US 20180349191 A1) in view of Poplack( US 10303230 B) and further in view of ELLINGSON( US 20200067927 A1).
As to claim 1, Ash teaches saving context of the first processor cluster ( separate clusters 20a, 20b of hardware components to provide redundancy for improved availability. Each cluster 20a, 20b may be maintained on a separate power boundary, and includes a processor complex 22a, 22b, a cache 24a, 24b, and a non-volatile storage unit (NVS) 26a, 26b, para[0022], ln 1-10/ provide redundant hardware clusters. Each hardware cluster comprises a processor complex, cache, non-volatile storage (NVS), such as a battery backed-up Random Access Memory (RAM), and separate power supply to provide connection paths to the attached storage. The NVS in one cluster would backup write data from the cache in the other cluster so that if one cluster fails, the write data in the cache of the failed cluster is stored in the NVS of the surviving cluster, para[0005], ln 2-12) ;
restoring saved context to a second processor cluster and a third processor cluster( As part of the failover process , the surviving cluster remains online and all the cached data for the failed cluster, i.e., the write data to the logical devices assigned to the failed cluster that was backed up in the NVS of the surviving cluster, is copied (also known as restored) from the NVS in the surviving cluster to the cache of the surviving cluster. Thus, after failover, the cache and NVS in the surviving cluster buffer writes that were previously directed to the failed cluster. During this restore/failover process, host I/O requests directed to logical devices previously assigned to the failed cluster are delayed until all writes to such logical devices in the NVS in the surviving cluster are restored/copied to the cache in the surviving cluster.)
and resuming execution of the software process on the second processor cluster and the third processor cluster( In one implementation, one or more shared resources, such as the system control unit (SCU) for the multi-core cluster, causes the given core of the multi-core cluster to execute a reset vector that points to the saved context to restart execution of the on or more processes, para[0025], ln 6-15/ For each determined track, the surviving processor complex 22b then calls (at block 106) the cache manager 30 for the surviving cache 24b in the surviving cluster 20b to allocate an entry in the cache memory 34 for the determined track. With this call, the cache manager 30 creates an entry in the cache directory 32 for the determined track without actually copying the track over from the surviving NVS 26b to the surviving cache 24b. The surviving processor complex 22b then ends the restore and allows (at block 108) the hosts 2a, 2b . . . 2n to issue I/O requests to the logical devices (LDs) 10a, 10b . . . 10n previously assigned to the failed cluster 20a, where such logical devices 10a, 10b . . . 10n are now reassigned to the surviving cluster 20b.), para[0025], ln 19-26/ in alternative implementations, the storage system may have only one cluster and the cache data may be restored from that single NVS in the single cluster. In still further implementations, there may be more than two clusters as shown and cache data may be restored from an NVS in the same cluster as the cache or in any of the other clusters. Further, the NVS may comprise any non-volatile storage that is sed to backup data in the cache, such as write data., para[0036], ln 7-16).
Dorsey teaches suspending execution of a multi-threaded software process by a first processor cluster on a first integrated circuit, and resuming execution of the multi-threaded software process on the second processor cluster and the third processor cluster on second integrated circuit (scheduling threads on a processor having a first cluster type having one or more cores and a second cluster type having one or more cores in a system that includes the processor, para[0023], ln 1-5/ Advantages of using DWI in a processor having multiple core types, such as AMP, include increased performance and efficiency for high-performance multi-threaded workloads on AMP systems, para[0138], ln 1-6/ Although four (4) E-cores and two (2) P-cores are shown, this is by way of example only. Any number of E-cores and P-cores can form a cluster of cores of a core type, para[0134], ln 3-10/ comprising performance cores (P-core) and efficiency cores (E-cores), a thread group may be recommended for running a P-core. Threads of the thread groups recommended for running on a P-core are said to be “P-eligible.” If a P-eligible thread is runnable but waiting on a P-core to become available, and an E-core is available, one solution to ensuring that the thread makes progress is to “spillover” the P-eligible thread to run on an E-core. However, this solution requires a certain amount of overhead to run the P-eligible thread on the E-core. An alternative solution is to have the P-eligible thread wait for a small amount of time for a P-core to become available and run the P-eligible thread on the P-core. While it is counter-intuitive that waiting can increase performance, this solution using DIPI recognizes that P-cores generally retire instructions faster than E-cores, and a P-core may become available sooner than the time it takes wake up an idle E-core and switch the P-eligible thread to run on an E-core, para[0130], ln 5-27/ Hardware 110 can include a processor complex 111 with a plurality of core types or multiple processors of differing types. Processor complex 111 can comprise a multiprocessing system having a plurality of clusters of cores, each cluster having one or more cores of a core type, interconnected with one or more buses, para[0069], ln 1-7/ A processor complex 111 may be a system on a chip (SoC), para[0217]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash and Dorsey Provides improved scheduling latency and thread migration hysteresis, and energy-efficiency for low-demand workloads, using deferred IPIs that avoid unnecessary core shutdown and subsequent power-up.
Poplack teaches first processor cluster on a first integrated circuit, second and third processor cluster a second integrated circuit different from the first integrated circuit(emulation chips may comprise hardware components, such as processors, capable of processor-based (e.g., hardware-based) emulation of logic systems, such as application specific integrated circuits (ASICs), col 1, ln 20-25/ Complex integrated circuits, such as chips (e.g., emulation chips), may include any number of processors, which, in some cases, may be organized on a chip into one or more processor clusters, comprising a set of one or more processors, col 6, ln 17-25/ Emulation logic boards 232 comprise computing hardware components capable of emulation functionality to emulate the design and functions of an ASIC or other circuitry; non-limiting examples of emulated ASICs might include CPUs, GPUs, and ALUs, among others. The logic board 232 may comprise one or more emulation chips 234 performing the functions needed for emulation, and one or more buses interconnecting the emulation chips 234, col 10, ln 20-30/ an emulation system comprises a plurality of emulation chips. Each of the emulation chips comprises a plurality of processor clusters, col 15, ln 29-34/ Fig. 2B/ The sequencer 304 may be configured to provide commands to a set of emulation chips and/or processor clusters from a total number of emulation chips/processor clusters on each of the emulation chip, col 15, ln 40-45/ when mission cycles are run on different emulation chips, col 16, ln 51-55).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash and Dorsey with Poplack to incorporate the above feature because this enables one or more processors or one or more processor clusters at a time, thereby reducing the load step by a factor of the number of processors or processor clusters enabled.
Ellingson teaches the second integrated circuit having a different processor--per--processor cluster profile than the first integrated circuit( ELLINGSON teaches second integrated circuit having a different multi-core processing cluster per graphics processing processor per processor cluster (GPC) profile than the first integrated circuit profile( The term "system-on-chip" (SoC) is used herein to refer to a set of interconnected electronic circuits typically, but not exclusively, including a processing device, a memory, and a communication interface. A processing device may include a variety of different types of processors and processor cores, such as a general purpose processor, a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), an accelerated processing unit (APU), a secure processing unit (SPU), a subsystem processor of specific components of the computing device, such as an image processor for a camera subsystem or a display processor for a display, an auxiliary processor, a single- core processor, and a multicore processor. A processing device may further embody other hardware and hardware combinations, such as a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), para[0048], In 1-30/ The CPU 102, the GPU 104, the DSP 106, and the custom hardware accelerator 108, may each be configured for specific purposes that may be the same as or different from other processing devices of the SoC 100. One or more of the CPU 102, the GPU 104, the DSP 106, and the custom hardware accelerator 108 and their processor cores of the same or different configurations may be grouped together. A group of CPUs 102, GPUs 104, DSPs 106, and custom hardware accelerators 108 or their processor cores may be referred to as a multi-processor cluster, para[0075]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash, Dorsey and Poplack with Ellingson to incorporate the above feature because this enables the processing device to generate a very large number of unpredictable element values and relationships among data elements from a relatively small number of portions and allows the reliability and security of digital certificates or other similar information for trusted device identity verification.
As to claim 21, it is rejected for the same reason as to claim 1, In additional, Popllack teaches memory, and at least one processor or processing circuit connected to a first integrated circuit, a second integrated circuit and the memory, the at least one processor or processing circuit configured to perform operations comprising: controlling the first/second integrated circuit( A processor 306 of the emulation chip may be associated with a data memory array 302. In some cases, the data memory array 302 may be a component of the processor 306. In some cases, the data memory array 302 may be communicatively coupled to a plurality of processors 306, such that the data memory array 302 is accessible by a cluster of processors 306. The data memory array 302 is a memory circuit that stores outputs of processors 306 of the emulation chip, as well as data from other external processors. For example, the data memory array 302 may store results generated by the processor 306 after executing an mission instruction during a mission cycle, or the memory array 302 may store inputs from external sources (e.g., external processors of another emulation chip) that will be used by the processor 306 in an upcoming mission cycle, col 11, ln 55-67/ Emulation chips 234 may comprise any number of processors capable of performing the various tasks and processes for emulating logic systems (e.g., ASIC, FPGA) being designed; multiplexers configured to direct data signals to and from the processors; buses for communicating data between the processors; and data lanes connecting the components of processors, col 10, ln 39-46/ he emulation engine may test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system, without having to actually, physically fabricate the hardware, col 9, ln 15-20).
Claims 2, 3, 22, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ash( US 20040059870 A1) In view of DORSEY(US 20180349191 A1) in view of Poplack( US 10303230 B) in view of ELLINGSON( US 20200067927 A1) and further in view of in view of Chen( US 20160139655 A1)
As to claim 2, Chen teaches resuming execution includes resuming execution on a different number of processors of the second integrated circuit than had been executing the software process on the first integrated circuit( The helps indicates the required number of active processor cores for processing a system workload. In one embodiment, the required number of active processor cores can be obtained or calculated from the number of threads or tasks with loading greater than a threshold, e.g., the number of threads or tasks that the system is required to process multiplied by the loading. The loading increases when system workload increases and the number of active cores stays the same. When the loading exceeds a predetermined threshold, more processor cores or more clusters may be activated to keep the loading below that threshold. In one embodiment, the determination of how many active processor cores and active clusters to have in the system depends on the value of helps, para[0031], ln 20-35/ para[0044], ln 1-10/ para[0062], ln 3-6).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash, Dorsey, Poplack and Ellingson with Chen to incorporate the above feature because this provides a need to improve the power and performance management in a multi-cluster system that has more than one processor type.
As to claim 3, Chen teaches suspending and resuming are performed on a per-processor basis( para[0070], ln 12-20) for the same reason as to claim 1 above.
As to claims 22, 23, they are rejected for the same reasons as to claims 2, 3 above.
4. Claims 4, 5, 24, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Ash( US 20040059870 A1) in view of DORSEY(US 20180349191 A1) in view of Poplack( US 10303230 B) in view of ELLINGSON( US 20200067927 A1) and further in view of RYU( US 20130339771 A1).
As to claim 4, Ryu teaches suspending and resuming include migrating execution of a first Singleton multi-core processing cluster to a second Singleton multi-core processing cluster( there is provided a multi-cluster processing system comprising: a first cluster including a plurality of first-type cores; a second cluster comprising a plurality of second-type cores; and a control unit which enables at least one disabled first-type cores, among the first-type cores, when a first event occurs, and the control unit which disables all enabled first-type cores, among the first-type cores and enables at least one of the disabled second-type cores, para[0010], ln 2-11).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash, Dorsey, Poplack and Ellingson with Ryu to incorporate the above feature because this reduces power consumption during operation.
As to claim 5, Ryu teaches wherein the first Singleton multi-core processing cluster and the second Singletons Singleton multi-core processing cluster have different physical and/or logical identifiers( para[0012], ln 2-14/ para[0029], ln 1-6/ para[0024]) for the same reason as to claim 4 above.
As to claims 24, 25, they are rejected for the same reasons as to claims 4, 5 above.
5. Claims 6, 7, 9, 26, 27, 29 are rejected under 35 U.S.C. 103 as being unpatentable over Ash( US 20040059870 A1) In view of DORSEY(US 20180349191 A1) in view of Poplack( US 10303230 B) in view of ELLINGSON( US 20200067927 A1) and further in view of Therien(US 20170177407 A1).
As to claim 6, Therien teaches saving and restoring are performed on a per- processor basis( A migration request is shown in FIG. 2. In some embodiments, a processor uses virtual core identifiers to hide core migration from an operating system. The migration is shown in three phases: a context saving phase 210, a virtual core swap phase 212 and a restore phase 214. In the context saving phase 210, the cores 202 and 204 receive a request to save their state to the C6 storage 206, 208 associated with the cores 202, 204. The C0 (202) saves to the C6 storage 206. The C1 (204) saves to the C6 storage 208. After saving context, both cores 202, 204 quiesce. In the virtual core swap phase 212, a virtual core ID (e.g., an APIC ID) can be swapped from the C0 (202) to the C1 (204). The C0 (202) now appears externally to be C1 and the C1 (204) now appears externally to be C0. In the restore phase 214, the context stored in the C6 storage (208) of the C1 (204) is restored to the C0 (202). The context stored in the C6 storage (206) of the C0 (202) is restored to the C1 (204). When resumed, an external system (e.g., an OS) views threads as continuing to operate on the same virtual cores. However, the physical cores 202, 204 have been swapped. It should be noted that the uncore (not shown) should redirect traffic based on virtual core IDs, para[0030]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash, Dorsey, Poplack and Ellingson with Therien to incorporate the feature of saving and restoring are performed on a per- processor basis because this enable spare cores to be used alternatively with other cores to reduce overall stress, which can result in lower power and higher performance (as power demand can increase over lifetime use).
As to claim 7, Therien teaches the saving and restoring preserve virtual processor identifiers( para[0030]/ para[0036], ln 23-28) for the reason as to claim 4 above.
As to claims 26, 27, 29, they are rejected for the same reasons as to claims 6, 7, 9 above.
6. Claims 8, 28 are rejected under 35 U.S.C. 103 as being unpatentable over Ash( US 20040059870 A1) in view of DORSEY(US 20180349191 A1) in view of Poplack( US 10303230 B) in view of ELLINGSON( US 20200067927 A1) in view of Therien(US 20170177407 A1) and further in view of ALBEN(US 20210286693 A1).
As to claim 8, Alben teaches saving and restoring GPC state information( The fault testing described herein may be performed on any type of processing cores and/or component thereof, such as graphics processing units (GPUs), central processing units (CPUs), graphics processing cluster (GPCs), para[0014], ln 10-19/ By storing the state information during the test, a state restorer 114 may be used to restore the state information to the component(s) after testing is completed. As such, once the component(s) are put back into operation, the state of the component(s) appears unchanged to the system, thereby ensuring continuity, accuracy, and the safety of the system. With reference to FIG. 2A, the state information may be retrieved from a component(s) of the system (e.g., from a GPC 208, a TPC 212, etc.), and stored in the memory 214. para[0024], ln 7-23).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash, Dorsey, Poplack and Ellingson with Alben to incorporate the feature of do not teach saving and restoring GPC state information because this enables a component to be tested during an idle or low power state without interfering with operation of the system, while preserving the state integrity of the component.
As to claim 28, it is rejected for the same reason as to claim 8 above.
7. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ash( US 20040059870 A1) in view of DORSEY(US 20180349191 A1) in view of Poplack( US 10303230 B) in view of ELLINGSON( US 20200067927 A1) in view of Therien(US 20170177407 A1) and further in view of Lai( US 20170262291A1) .
As to claim 9, Lai teaches synthesizing per-processor state information when resuming execution comprises resuming execution on more processors on the second integrated circuit than were suspended on the first integrated circuit( When SIMD execution switches from a first processor to a second processor, the stored context of the second processor can be quickly (e.g., in one cycle) retrieved from its internal registers or buffers to start the execution process. The context of the first processor is stored in its internal registers or buffers for fast retrieval when the SIMD execution switches back to the first processor, para[0026], ln 8-14).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash, Dorsey, Poplack, Ellingson and Therien with Lai to incorporate the feature of do not teach saving and restoring GPC state information because this enables a component to be tested during an idle or low power state without interfering with operation of the system, while preserving the state integrity of the component.
8. Claims 10, 30 are rejected under 35 U.S.C. 103 as being unpatentable over Ash( US 20040059870 A1) in view of DORSEY(US 20180349191 A1) in view of Poplack( US 10303230 B) in view of ELLINGSON( US 20200067927 A1) and further in view of APPU( US 20180293701 A1).
As to claim 10, Appu teaches suspending execution is performed on a first number of GPCs, and resuming execution is performed on a second number of GPCs different from the first number of GPCs( virtualization mediator 1622 emulates virtual GPUs (vGPUs) 1624 for privileged resource accesses, and conducts context switches amongst the vGPUs 1624, para[0140], ln 1-5/ The steps used to switch a context in one embodiment are: 1) save current I/O states, 2) flush the current context, 3) use the additional commands to save the current context, 4) use the additional commands to restore the new context, and 5) restore I/O state of the new context, para[0147], ln 13-21).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash, Dorsey, Poplack and Ellingson with APPU to incorporate the feature of suspending execution is performed on a first number of GPCs, and resuming execution is performed on a second number of GPCs different from the first number of GPCs because this performs full GPU virtualization through trap-and-emulation to emulate a full-featured virtual GPU (vGPU) while still providing near-to-native performance by passing through performance-critical graphics memory resources.
As to claim 30, it is rejected for the same reasons as to claim 10 above.
9. Claims 11, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Ash( US 20040059870 A1) in view of DORSEY(US 20180349191 A1) in view of Poplack( US 10303230 B) in view of ELLINGSON( US 20200067927 A1) and further in view of KOO(US 20220092722 A1).
As to claim 11, Koo teaches dynamically disabling processors on the second integrated circuit by maintaining status updates to them but not sending any work to them( glitchless switching between the low-power GPU 130 and the high-performance GPU 135 at the MUX 140 without blanking or artifacts, the control logic 120 signals the display device 170 to capture the current video frame at its frame buffer and replay the captured frame in response to the control logic 120 determining that a switch between the GPUs 130, 135 is to occur at the MUX 140. In response to receiving a Capture Frame signal to, the display device 170 begins to capture the current frame at the frame buffer. Once the capture is complete, the control logic 120 sends a Replay Frame signal to signal the display device 170 to maintain a static image by continually refreshing the panel using the captured frame. While the display device 170 refreshes the panel using the captured frame, the control logic 120 disables output from the active GPU, ceases transmitting data via the interconnect 160 to the display device 170, and initiates a switch from the active GPU 130, 135 to the other GPU 130, 135. For example, if the low-power GPU 130 was the initially active GPU that rendered the current frame, and the control logic 120 determines based on the graphics intensity of the next frame that a switch to the high-performance GPU 135 is desired, the control logic 120 disables output from the low-power GPU 130 once the display device 170 has begun self-refreshing with the captured frame and switches to the high-performance GPU 135 at the MUX 140, para[0018], ln 1-23/ If, at block 510, the control logic 120 determines to not switch GPUs 130, 135 at the MUX 140, the method flow continues back to block 504, at which the next frame of pixel data is received. If, at block 510, the control logic 120 determines to switch GPUs 130, 135 at the MUX 140, the method flow continues to block 512. At block 512, the active GPU 130, 135 sends a Capture Frame signal to the display device 170 to capture the current frame and a Replay Frame signal to replay the captured frame, para[0033], ln 1-10).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Ash, Dorsey, Poplack and Ellingson with Koo to incorporate the feature of dynamically disabling processors on the second integrated circuit by maintaining status updates to them but not sending any work to them because this conserves power and improves efficiency.
As to claim 31, it is rejected for the same reasons as to claim 11 above.
Response to the argument:
A. Applicant amendment filed on 03/09/2026 has been considered but they are not persuasive:
Applicant argued in substance that :
“the Office Action has not explained why Ryu would deactivate a first cluster with only one processing core on and instead activate a second cluster with only one processing core on since each would appear to consume the same power. In any event, Ryu says nothing about suspending and resuming including migrating execution as applicant has claimed. ”
B. Examiner respectfully disagreed with Applicant's remarks:
As to the point (1), Ash teaches saving context of the first processor cluster ( separate clusters 20a, 20b of hardware components to provide redundancy for improved availability. Each cluster 20a, 20b may be maintained on a separate power boundary, and includes a processor complex 22a, 22b, a cache 24a, 24b, and a non-volatile storage unit (NVS) 26a, 26b, para[0022], ln 1-10/ provide redundant hardware clusters. Each hardware cluster comprises a processor complex, cache, non-volatile storage (NVS), such as a battery backed-up Random Access Memory (RAM), and separate power supply to provide connection paths to the attached storage. The NVS in one cluster would backup write data from the cache in the other cluster so that if one cluster fails, the write data in the cache of the failed cluster is stored in the NVS of the surviving cluster, para[0005], ln 2-12) ;
restoring saved context to a second processor cluster and a third processor cluster( As part of the failover process , the surviving cluster remains online and all the cached data for the failed cluster, i.e., the write data to the logical devices assigned to the failed cluster that was backed up in the NVS of the surviving cluster, is copied (also known as restored) from the NVS in the surviving cluster to the cache of the surviving cluster. Thus, after failover, the cache and NVS in the surviving cluster buffer writes that were previously directed to the failed cluster. During this restore/failover process, host I/O requests directed to logical devices previously assigned to the failed cluster are delayed until all writes to such logical devices in the NVS in the surviving cluster are restored/copied to the cache in the surviving cluster.)
and resuming execution of the software process on the second processor cluster and the third processor cluster( In one implementation, one or more shared resources, such as the system control unit (SCU) for the multi-core cluster, causes the given core of the multi-core cluster to execute a reset vector that points to the saved context to restart execution of the on or more processes, para[0025], ln 6-15/ For each determined track, the surviving processor complex 22b then calls (at block 106) the cache manager 30 for the surviving cache 24b in the surviving cluster 20b to allocate an entry in the cache memory 34 for the determined track. With this call, the cache manager 30 creates an entry in the cache directory 32 for the determined track without actually copying the track over from the surviving NVS 26b to the surviving cache 24b. The surviving processor complex 22b then ends the restore and allows (at block 108) the hosts 2a, 2b . . . 2n to issue I/O requests to the logical devices (LDs) 10a, 10b . . . 10n previously assigned to the failed cluster 20a, where such logical devices 10a, 10b . . . 10n are now reassigned to the surviving cluster 20b.), para[0025], ln 19-26/ in alternative implementations, the storage system may have only one cluster and the cache data may be restored from that single NVS in the single cluster. In still further implementations, there may be more than two clusters as shown and cache data may be restored from an NVS in the same cluster as the cache or in any of the other clusters. Further, the NVS may comprise any non-volatile storage that is sed to backup data in the cache, such as write data., para[0036], ln 7-16).
Dorsey teaches suspending execution of a multi-threaded software process by a first processor cluster on a first integrated circuit, and resuming execution of the multi-threaded software process on the second processor cluster and the third processor cluster on second integrated circuit (scheduling threads on a processor having a first cluster type having one or more cores and a second cluster type having one or more cores in a system that includes the processor, para[0023], ln 1-5/ Advantages of using DWI in a processor having multiple core types, such as AMP, include increased performance and efficiency for high-performance multi-threaded workloads on AMP systems, para[0138], ln 1-6/ Although four (4) E-cores and two (2) P-cores are shown, this is by way of example only. Any number of E-cores and P-cores can form a cluster of cores of a core type, para[0134], ln 3-10/ comprising performance cores (P-core) and efficiency cores (E-cores), a thread group may be recommended for running a P-core. Threads of the thread groups recommended for running on a P-core are said to be “P-eligible.” If a P-eligible thread is runnable but waiting on a P-core to become available, and an E-core is available, one solution to ensuring that the thread makes progress is to “spillover” the P-eligible thread to run on an E-core. However, this solution requires a certain amount of overhead to run the P-eligible thread on the E-core. An alternative solution is to have the P-eligible thread wait for a small amount of time for a P-core to become available and run the P-eligible thread on the P-core. While it is counter-intuitive that waiting can increase performance, this solution using DIPI recognizes that P-cores generally retire instructions faster than E-cores, and a P-core may become available sooner than the time it takes wake up an idle E-core and switch the P-eligible thread to run on an E-core, para[0130], ln 5-27/ Hardware 110 can include a processor complex 111 with a plurality of core types or multiple processors of differing types. Processor complex 111 can comprise a multiprocessing system having a plurality of clusters of cores, each cluster having one or more cores of a core type, interconnected with one or more buses, para[0069], ln 1-7/ A processor complex 111 may be a system on a chip (SoC), para[0217]).
Poplack teaches first processor cluster on a first integrated circuit, second and third processor cluster a second integrated circuit different from the first integrated circuit(emulation chips may comprise hardware components, such as processors, capable of processor-based (e.g., hardware-based) emulation of logic systems, such as application specific integrated circuits (ASICs), col 1, ln 20-25/ Complex integrated circuits, such as chips (e.g., emulation chips), may include any number of processors, which, in some cases, may be organized on a chip into one or more processor clusters, comprising a set of one or more processors, col 6, ln 17-25/ Emulation logic boards 232 comprise computing hardware components capable of emulation functionality to emulate the design and functions of an ASIC or other circuitry; non-limiting examples of emulated ASICs might include CPUs, GPUs, and ALUs, among others. The logic board 232 may comprise one or more emulation chips 234 performing the functions needed for emulation, and one or more buses interconnecting the emulation chips 234, col 10, ln 20-30/ an emulation system comprises a plurality of emulation chips. Each of the emulation chips comprises a plurality of processor clusters, col 15, ln 29-34/ Fig. 2B/ The sequencer 304 may be configured to provide commands to a set of emulation chips and/or processor clusters from a total number of emulation chips/processor clusters on each of the emulation chip, col 15, ln 40-45/ when mission cycles are run on different emulation chips, col 16, ln 51-55).
Conclusion
US 20140059548 A1 teaches cluster switching one or more shared resources utilized by the given core of the multi-core cluster to the core of the single-core cluster after power-ungating the core of the single-core cluster and saving the context of the one or more processes executing on the given core of the multi-core cluster, wherein the multi-core cluster.
US 20140189317 A1 teaches a high level flow in which one or more processor clusters 804 perform general purpose processing operations and one or more accelerator clusters 801 perform accelerator-specific operations. By way of example, the general purpose processor clusters 804 may include execution logic within a processor core for executing instructions.
US 20170168876 A1 teaches Processor , which may be a data processor, a graphics engine, a graphics pose processor (GPP), a processing core, clusters of processing cores, input/output (I/O) masters, a digital signal processor (DSP), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) device as has been described, controls outgoing requests element to transmit in any order first and second reservation requests for reservation of one or more resources needed for execution of the first and second transaction requests.
US 6950963 B1 teaches When all group members have requested the group scan, the chain manager 106 commences with the group scan, and then deallocates all group resources, effectively dissolving the group. The system user may select synchronous or asynchronous group control of the processor group for commands such as run, resume, step, step-n, halt, and halt at breakpoint. All knowledge of the processor-specific IEEE 1149.1 interface for a given processor is contained in the corresponding TAP manager program.
US 20140157277 A1 teaches as the number of processor cores sharing a common supply rail or the number of processors in a processor group sharing a common supply rail increase, whether on a same chip or on different chips,
US 20140298480 teaches power controller 130, in order to render the processing unit fully functional for highly current consuming use cases, transmit command (603) to the second cluster (i.e. processors ) in order to wake them up. Both processors restore (611 and 612) their own personal context and inform the power controller that they are fully functional (604a and 604b).
US 20170024329 A1 teaches The suspend detection circuit 18 outputs an all-core suspend signal ALL_CORE_SUSPEND indicating that all cores in a cluster are in a suspend state when all threads belonging to the cluster are offline or suspended. The suspend detection circuit includes an OR gate that takes logical OR between offline signals and suspend signals of each thread in the cluster and an AND gate 182 that takes logical AND between the outputs of the OR gates 181 of all threads.
US 20230088998 A1 teaches The first sub-processor cluster 112, the second sub-processor cluster 114 and the communication CPU LCPU may be attached onto a main board of the system on chip .
US 20160013643 teaches A1Once the tasks are appropriately migrated, the clocks driving the processors of the clusters are temporarily gated by the power rail controller 102, at step 222, to pause all processes running on the processors so that the processors stop once the current instructions are completed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LECHI TRUONG whose telephone number is (571)272-3767. The examiner can normally be reached 10-8 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Young Kevin can be reached on (571)270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LECHI TRUONG/ Primary Examiner, Art Unit 2194
Prosecution Insights