The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This communication is responsive to Amendment filed 05/14/2026.
Claims 1, 3-9, 11-14, 17-22, and 24-30 have been examined.
Response to Amendment
In the instant amendment, claims 1, 3, 5-9, 11-12, 20, 22 and 28 have been amended. Claims 29-30 are newly added.
Allowable Subject Matter
Claims 14 and 17-22 and 24-28 are allowed.
Claim 8 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-5, and 9, 11-12 and 29 are rejected under 35 U.S.C. 102(XYZ) as being anticipated by US 2014/0123150 to Lindholm et al. (hereinafter “Lindholm”) in view of US 2014/0337389 to Ricketts et al. (hereafter “Ricketts”), US 2013/0198759 to Shah et al. (hereafter “Shah”) and US 2020/0043123 to Dash et al. (hereafter “Dash”)
As per claim 1, Lindholm discloses a processing system including:
a set of plural processors (FIGs. 2-3; paragraphs 0027, 0029, 0030-0031, and 0047-0048: a plurality of GPC 208 [Wingdings font/0xE0] a plurality of multiprocessor SM 310), and
a work distributor (FIGs. 3C; paragraphs 0031 and 0047-0048: CPU 102 and SM 310) that distributes a collection of cooperative thread arrays (CTAs) (FIGs. 3-4; paragraphs 0047-0049, 0055-0056, 0067 and 0084) across to the set of plural processors for execution by the set of plural processors (FIGs. 3-4; paragraphs 0047-0048, 0055 and 0067: “As shown in FIG. 4, 128 warps may be simultaneously processed by an SM 310 and the four thread blocks may be distributed to different execution units 302 for load balancing across the different execution units 302.” [Wingdings font/0xE0] thread blocks are a assigned to a Exc units 302),
wherein the set of plural processors is configured to launch and execute at the same time the collection of CTAs (FIG. 3-4; paragraphs 0048, 0063 and 0067: “Sixteen warps are reserved for processing the thread blocks, where each warp includes 4 threads. Therefore, each thread block is a group of 64 threads having resources that are allocated together. In another embodiment, a thread block includes a different number of threads, e.g., a thread block is a group of 16 threads (4 warps of 4 threads each). As shown in FIG. 4, 128 warps may be simultaneously processed by an SM 310 and the four thread blocks may be distributed to different execution units 302 for load balancing across the different execution units 302.”),
the work distributor being configured to:
(a) balance loading of the CTAs across the set of plural processors (FIG. 3-4; paragraph 0067: “As shown in FIG. 4, 128 warps may be simultaneously processed by an SM 310 and the four thread blocks may be distributed to different execution units 302 for load balancing across the different execution units 302.”), and
(b) guarantee the set of plural processors can have processing resources to concurrently execute the collection of CTAs (FIG. 3-4; paragraphs 0048, 0063 and 0067: “Sixteen warps are reserved for processing the thread blocks, where each warp includes 4 threads. Therefore, each thread block is a group of 64 threads having resources that are allocated together. In another embodiment, a thread block includes a different number of threads, e.g., a thread block is a group of 16 threads (4 warps of 4 threads each). As shown in FIG. 4, 128 warps may be simultaneously processed by an SM 310 and the four thread blocks may be distributed to different execution units 302 for load balancing across the different execution units 302.”),
wherein the respective thread blocks CTAs are assigned identifier coordinates for execution on the set of plural processors (FIG. 4; paragraphs 0067-0071: “the thread block is computed by truncating the lowest 4 bits of the logical identifier. The lowest 4 bits of the logical identifier are an offset within the thread block. The physical identifier for the thread is computed by mapping the thread block to a corresponding physical identifier base and then using the offset to locate the processing resources allocated for the thread. For example, the high bits of the physical identifier may be used to determine the thread block and the lower bits may be used to determine the particular thread within the thread block.”).
Lindholm does not explicitly disclose a cooperative group array (CGA) comprising a collection of cooperative thread arrays (CTAs); wherein the set of plural processors is configured to launch and execute at the same time the collection of CTAs comprising the CGA; CTAs in the CGA; (b) guarantee the set of plural processors can have processing resources to concurrently launch and execute the collection of CTAs in the CGA before launching any of the CTAs in the CGA.
Ricketts further discloses a cooperative group array (CGA) comprising a collection of cooperative thread arrays (CTAs) (paragraphs 0023, 0041 and 0043: “In one embodiment, a thread block comprises 32 related threads and a grid is an array of one or more thread blocks that execute the same stream and the different thread blocks may exchange data through global memory. A thread block may also be referred to as a cooperative thread array (CTA).” [Wingdings font/0xE0] a grid (CGA as claimed) having one or more thread blocks (CTA));
the collection of CTAs comprising the CGA (paragraphs 0023, 0041 and 0043: “In one embodiment, a thread block comprises 32 related threads and a grid is an array of one or more thread blocks that execute the same stream and the different thread blocks may exchange data through global memory. A thread block may also be referred to as a cooperative thread array (CTA).” [Wingdings font/0xE0] a grid (CGA as claimed) having one or more thread blocks (CTA)); and
CTAs in the CGA (paragraphs 0023, 0041 and 0043: “In one embodiment, a thread block comprises 32 related threads and a grid is an array of one or more thread blocks that execute the same stream and the different thread blocks may exchange data through global memory. A thread block may also be referred to as a cooperative thread array (CTA).” [Wingdings font/0xE0] a grid (CGA as claimed) having one or more thread blocks (CTA)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ricketts into Lindholm’s teaching because it would provide for the purpose of the CPU executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the CPU to schedule operations for execution on the PPU (Rickett, paragraph 0023).
Shah further discloses wherein the set of plural processors is configured to launch and execute at the same time the collection of CTAs (FIG. 1; paragraphs 0025-0026 and 0066-0067: “If all 50 entries are written at the same time, all 5 CTAS may launch at the same time. If the 50 entries are written over several clock cycles, then the CTAS will be launched as each successive group of 10 contiguous entries is written.”)
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Shah into Lindholm’s teaching and Ricketts’ teaching because it would provide for the purpose of launching a set of CTAS for execution by the streaming multiprocessor, based on the work distribution parameters, to process the amount of the work, and update a pointer to a first entry in the first queue to be processed by a next set of CTAS based on the work distribution parameters (Shah, paragraph 0008).
Dash further discloses (b) guarantee the set of plural processors can have processing resources to concurrently launch and execute the collection of CTAs before launching any of the CTAs (paragraphs 0061-0162 and 0165-0170: “Once MPC requests CTAs, resources in SM are reserved and there is a guarantee that any CTA launched by CWD will be quickly loaded onto the SM.”)
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Dash into Lindholm’s teaching, Ricketts’ teaching and Shah’s teaching because it would provide for the purpose of guarantee that any CTA launched by CWD will be quickly loaded onto the SM (Dash, paragraph 0162).
As per claim 3, Lindholm does not explicitly disclose wherein the CGA is represented by a grid comprises a three-dimensional array of the CTAs.
Ricketts further discloses wherein the CGA is represented by a grid comprises a three-dimensional array of the CTAs (paragraphs 0023 and 0039).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ricketts into Lindholm’s teaching because it would provide for the purpose of the CPU executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the CPU to schedule operations for execution on the PPU (Rickett, paragraph 0023).
As per claim 4, Lindholm discloses wherein the processors comprise streaming multiprocessors (paragraphs 0046-0047: GPC 208 including streaming processor 310) and the work distributor comprises a hardware circuit (FIGs. 3-5; paragraphs 0047-0050).
As per claim 5, Lindholm discloses wherein the work distributor comprises a first work distributor hardware circuit configured to distribute the CTAs in the CGA across the set of plural processors (FIGs. 1-2; paragraph 0031: CPU 102 writes stream commands for each PPU), and a plurality of second work distributor hardware circuits structured to assign CTAs to individual processors of the set of plural processors (FIGs. 2-5; paragraphs 0047-0048: each PPU having GPC including SM scheduling works across Exec unit 302).
Lindholm does not explicitly disclose CTAs in the CGA.
Ricketts further discloses CTAs in the CGA (paragraphs 0023, 0041 and 0043: “In one embodiment, a thread block comprises 32 related threads and a grid is an array of one or more thread blocks that execute the same stream and the different thread blocks may exchange data through global memory. A thread block may also be referred to as a cooperative thread array (CTA).” [Wingdings font/0xE0] a grid (CGA as claimed) having one or more thread blocks (CTA)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ricketts into Lindholm’s teaching because it would provide for the purpose of the CPU executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the CPU to schedule operations for execution on the PPU (Rickett, paragraph 0023).
As per claim 9, Lindholm discloses wherein the work distributor load balances the CTAs across the set of plural processors by simultaneously selecting more than one processor to concurrently launch and execute CTAs (FIG. 3-4; paragraphs 0048, 0063 and 0067: “Sixteen warps are reserved for processing the thread blocks, where each warp includes 4 threads. Therefore, each thread block is a group of 64 threads having resources that are allocated together. In another embodiment, a thread block includes a different number of threads, e.g., a thread block is a group of 16 threads (4 warps of 4 threads each). As shown in FIG. 4, 128 warps may be simultaneously processed by an SM 310 and the four thread blocks may be distributed to different execution units 302 for load balancing across the different execution units 302.”).
Lindholm does not explicitly disclose CTAs of the CGA.
Ricketts further discloses CTAs of the CGA (paragraphs 0023, 0041 and 0043: “In one embodiment, a thread block comprises 32 related threads and a grid is an array of one or more thread blocks that execute the same stream and the different thread blocks may exchange data through global memory. A thread block may also be referred to as a cooperative thread array (CTA).” [Wingdings font/0xE0] a grid (CGA as claimed) having one or more thread blocks (CTA)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ricketts into Lindholm’s teaching because it would provide for the purpose of the CPU executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the CPU to schedule operations for execution on the PPU (Rickett, paragraph 0023).
As per claim 11, Lindholm discloses wherein the work distributor launches no more than one CTA of the CGA on any one processor of the set of plural processors (paragraphs 0084-0085).
Lindholm does not explicitly disclose CTAs of the CGA.
Ricketts further discloses CTAs of the CGA (paragraphs 0023, 0041 and 0043: “In one embodiment, a thread block comprises 32 related threads and a grid is an array of one or more thread blocks that execute the same stream and the different thread blocks may exchange data through global memory. A thread block may also be referred to as a cooperative thread array (CTA).” [Wingdings font/0xE0] a grid (CGA as claimed) having one or more thread blocks (CTA)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ricketts into Lindholm’s teaching because it would provide for the purpose of the CPU executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the CPU to schedule operations for execution on the PPU (Rickett, paragraph 0023).
As per claim 12, Lindholm discloses wherein the plural processors each comprise hardware that independently derives or calculates a unique identifier for a CTA executed thereby (the claim language only claims a unique identifier [Wingdings font/0xE0] the identifier can be any identifier not only CTA identifier. [Wingdings font/0xE0] Lindholm FIG. 4; paragraphs 0067-0071: “For example, the high bits of the physical identifier may be used to determine the thread block and the lower bits may be used to determine the particular thread within the thread block. In sum, the logical identifier is a CTA-oriented identifier for each thread in the CTA and the physical identifier is hardware-oriented identifier for each thread that is executed by the SM 310 for the CTA.” [Wingdings font/0xE0] the claim language only claims a unique identifier [Wingdings font/0xE0] the identifier can be any identifier not only CTA identifier. ).
As per claim 29, Lindholm discloses wherein a first processor of the set of processors is configured to launch and execute a first CTA and a second processor of the set of processors different from the first processor is configured to launch and execute a second CTA (FIGs. 3-4; paragraphs 0047-0048, 0055 and 0067: “As shown in FIG. 4, 128 warps may be simultaneously processed by an SM 310 and the four thread blocks may be distributed to different execution units 302 for load balancing across the different execution units 302.” [Wingdings font/0xE0] thread blocks are a assigned to a Exc units 302).
Lindholm does not explicitly disclose wherein a first processor of the set of processors is configured to launch and execute a first CTA and a second processor of the set of processors different from the first processor is configured to launch and execute a second CTA at the same time the first CTA launches and begins execution on the first processor.
Shah further discloses wherein a first processor of the set of processors is configured to launch and execute a first CTA and a second processor of the set of processors different from the first processor (FIGs. 2 and 3A-B; paragraphs 0045 and 0058: “In other embodiments, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of the GPCs 208. Unlike a SIMD execution regime, where all processing engines typically execute identical instructions, SIMT execution allows different threads to more readily follow divergent execution paths through a given thread program.” [Wingdings font/0xE0] multi GPCs 208 including multi processing engines (processors as claimed) providing parallel execution of synchronized threads) is configured to launch and execute a second CTA at the same time the first CTA launches and begins execution on the first processor (FIG. 1; paragraphs 0025-0026 and 0066-0067: “If all 50 entries are written at the same time, all 5 CTAS may launch at the same time. If the 50 entries are written over several clock cycles, then the CTAS will be launched as each successive group of 10 contiguous entries is written.”)
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Shah into Lindholm’s teaching and Ricketts’ teaching because it would provide for the purpose of launching a set of CTAS for execution by the streaming multiprocessor, based on the work distribution parameters, to process the amount of the work, and update a pointer to a first entry in the first queue to be processed by a next set of CTAS based on the work distribution parameters (Shah, paragraph 0008).
Claim 6, are rejected under 35 U.S.C. 103 as being unpatentable over Lindholm, Ricketts, Shah, and Dash, as applied to claim 1, and further in view of US 2003/0120778 to Chaboud et al. (hereafter “Chaboud”) and US 2015/0039860 to Sundar et al. (hereafter “Sundar”)
As per claim 6, Lindholm discloses wherein the work distributor includes a query model of the set of plural processors (FIGs. 3-4; paragraphs 0047-0048, 0055 and 0067).
Lindholm does not explicitly disclose CTAs in the CGA, and uses the query model to test launch the CTAs in the CGA against a shadow state of the set of plural processors to determine whether the CTAs of the CGA can launch and execute concurrently on the set of plural processors.
Ricketts further discloses CTAs in the CGA (paragraphs 0023, 0041 and 0043: “In one embodiment, a thread block comprises 32 related threads and a grid is an array of one or more thread blocks that execute the same stream and the different thread blocks may exchange data through global memory. A thread block may also be referred to as a cooperative thread array (CTA).” [Wingdings font/0xE0] a grid (CGA as claimed) having one or more thread blocks (CTA)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ricketts into Lindholm’s teaching because it would provide for the purpose of the CPU executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the CPU to schedule operations for execution on the PPU (Rickett, paragraph 0023).
Chaboud discloses uses the query model to test launch the CTAs against a state of the set of plural processors to determine whether the CTAs of the CGA can launch and execute concurrently on the set of plural processors (FIGs. 2-3; paragraphs 0048-0049).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Chaboud into Lindholm’s teaching, Ricketts’ teaching, Shah’s teaching and Dash’s teaching because it would provide for the purpose of allocating remotely accessible system resources is performed if there are insufficient local system resources to perform the task (Chaboud, paragraph 0010).
Sundar further discloses the state is a shadow state of the set of processors (paragraph 0061: copies of state in a particular of time).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Sundar into Lindholm’s teaching, Ricketts’ teaching, Shah’s teaching, Dash’s teaching and Chaboud’ teaching because it would provide for the purpose of when a speculative misprediction or an exception is detected, control logic within the processor 200 is able to select a given checkpoint or snapshot. The control logic utilizes the information stored in the snapshot to recover the architectural state and restart instruction processing at that point (Sundar, paragraph 0061).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lindholm, Ricketts, Shah’s teaching Dash’s teaching, Chaboud and Sundar, as applied to claim 6, and further in view of US 2006/0036580 to Stata et al. (hereafter “Stata”)
As per claim 7, Lindholm does not explicitly disclose wherein the work distributor maintains a live query model of the set of plural processors, and a further query model of the set of plural processors that stores a shadow state of the set of plural processors.
Stata further discloses wherein the work distributor maintains a live query model of the set of plural processors, and a further query model of the set of plural processors that stores a shadow state of the set of plural processors (paragraphs 0056 and 0071).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Stata into Lindholm’s teaching, Ricketts’ teaching, Shah’s teaching, Dash’s teaching, Chaboud’s teaching and Sundar’s teaching because it would provide for the purpose of providing the capability to continuously update the query (Stata, paragraph 0056).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lindholm, Ricketts, Shah, and Dash, as applied to claim 1, further in view of US 2009/0063885 to Arimilli et al. (hereafter “Arimilli”)
As per claim 13, Lindholm does not explicitly disclose wherein the work distributor is configured to determine, based on respective loading levels of the processors in the set of plural processor, which processors in the set of plural processor are likely to execute new work fastest.
Arimilli further discloses wherein the work distributor is configured to determine, based on respective loading levels of the processors in the set of plural processor, which processors in the set of plural processor are likely to execute new work fastest (paragraph 0084).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Arimilli into Lindholm’s teaching, Ricketts’ teaching, Shah’s teaching, and Dash’s teaching because it would provide for the purpose of based on a determined time difference between the fastest and slowest processors, a corresponding amount of data to be shifted may be identified (Arimilli, paragraph 0084).
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the new ground(s) of rejection. Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication should be directed to examiner Tuan Dao, whose telephone/fax numbers are (571) 270 3387 and (571) 270 4387, respectively. The examiner can normally be reached on every Monday-Thursday and the second Friday of the bi-week from 7:30AM to 5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Pierre Vital, can be reached at telephone number (571) 272 4215.
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Any inquiry of a general nature of relating to the status of this application or proceeding should be directed to the TC 2100 Group receptionist whose telephone number is (571) 272 2100.
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/TUAN C DAO/Primary Examiner, Art Unit 2198
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