DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendments filed on 2/02/26. Claims 1-20. Newly added claim 20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito et al. (US PGPub 2005/0224945, hereinafter referred to as “Saito”).
Saito discloses the semiconductor as claimed. See figures 1-12 and corresponding text, where Saito teaches, in claim 1, a lead-frame based half-bridge package, comprising:
a die pad (3), (portion underneath the first MOSFET chip) having a first surface and a second surface, wherein the die pad (3) is electrically connected to a drain terminal (5);
a first semiconductor die (1) arranged on the first surface of the die pad (3), the first semiconductor die (1) having a first transistor integrated thereon that comprises a first terminal (4) and a second terminal (6) arranged at a first surface of the first semiconductor die (1), and a third terminal (5) arranged at a second surface of the first semiconductor die (1) (figures 1 and 2; [0031]);
a second semiconductor die (2) having a second transistor integrated thereon that comprises a first terminal (4) and a second terminal (6) arranged at a first surface of the second semiconductor die (2), and a third terminal (5) arranged at a second surface of the second semiconductor die (2) (figures 1 and 2; [0031]);
wherein the second surface of the second semiconductor die (2) is arranged to face the first surface of the first semiconductor die (1) (figures 1 and 2; [0031]);
a first contact element (11a) arranged on the first surface of the first semiconductor die (1) and electrically connected to the first terminal (4) of the first transistor (figures 1 and 2; [0031]);
a second contact element (9) arranged in between the first and second semiconductor die (1, 2) and electrically connected to the second terminal (6) of the first transistor and the third terminal (5) of the second transistor (figure 1; [0031]);
a third contact element (11b) arranged on the first surface of the second semiconductor die and electrically connected to the first terminal (4) of the second transistor (figures 1 and 2; [0031]);
a fourth contact element (8) arranged on the first surface of the second semiconductor die (2) and electrically connected to the second terminal (6) of the second transistor; and
a solidified moulding compound (7) encapsulating the first semiconductor die (1), the second semiconductor die (2) and the first through fourth contact element (figures 1 and 2; [0031-0039]);
wherein each of the first, second, third and fourth contact elements comprises one or more leads that extend from their respective contact elements through and out of a side of the solidified moulding compound (7) to provide external access to the respective contact elements (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 2, wherein the solidified moulding compound partially encapsulates the die pad;
wherein at least part of the second surface of the die pad is exposed through the solidified moulding compound to provide external access to the third terminal of the first transistor (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 3, wherein the package further comprises one or more leads extending, from the die pad, through and out of the solidified moulding compound to provide external access to the die pad (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 4, wherein the leads of the first and second contact element extend parallel to each other and originate from different parts of a same clip comprised in a lead frame (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 5, wherein the leads of the third and fourth contact element extend parallel to each other and originate from different parts of a same clip comprised in a lead frame (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 6, wherein at least one of the first, second, third and fourth contact elements comprises a central planar part that is connected to one or more corresponding terminals of the first and second transistor and from which the one or more respective leads extend (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 7, wherein the leads corresponding to the first, second, third and fourth contact elements are gull-wing shaped formed so that an end thereof is positioned on a plane that coincides with a plane on which a bottom surface of the moulding compound is arranged (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 8, wherein the first transistor and the second transistor comprise field-effect transistors (FETs), wherein the first terminal is a gate terminal; wherein the second terminal is a source terminal; and wherein the third terminal is a drain terminal (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 9, wherein each of the first, second, third and fourth contact elements is attached to corresponding surfaces of the first and second semiconductor die using a conductive layer (figures 1 and 2; [0031-0039]); and
wherein the conductive layer comprises one element selected from the group consisting of:
aluminum, copper, gold, silver and tin ([0057]).
Saito teaches, in claim 10, wherein the fourth contact element is at least partially exposed to an outside for allowing a heat sink or heat spreader to be connected to a surface of the fourth contact element ( figures 1 and 12; [0093-0097]).
Saito teaches, in claim 11, wherein the first transistor is substantially identical to the second transistor (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 12, wherein the first semiconductor die is substantially identical to the second semiconductor die (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 13, wherein the first and/or second terminal of the first transistor are arranged at opposing ends of the package with respect to the first and/or second terminal of the second transistor, respectively, wherein the one or more leads corresponding to the first contact element and the second contact element extend in a direction opposite to a direction in which the one or more leads corresponding to the third contact element and the fourth contact element extend (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 14, a DC-DC converter comprising a packaged half-bridge circuit (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 15, a motor controller comprising a packaged half-bridge circuit (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 16, wherein the first transistor and the second transistor comprise bipolar junction transistors (BJTs);
wherein the first terminal is a base terminal;
wherein the second terminal is an emitter terminal; and wherein the third terminal is a collector terminal (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 17, wherein one of the first transistor and the second transistor is a field-effect transistor (FET), and another of the first transistor and the second transistor is a bipolar junction transistor (BJT) (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 18, wherein the package further comprises one or more leads extending, from the die pad, through and out of the solidified moulding compound to provide external access to the die pad (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 19, wherein the leads corresponding to the first, second, third and fourth contact elements are gull-wing shaped formed so that an end thereof is positioned on a plane that coincides with a plane on which the second surface of the die pad is arranged (figures 1 and 2; [0031-0039]).
Saito teaches, in claim 20, wherein the second contact element is a shared contact element stacked between the first semiconductor and the second semiconductor die (figures 1 and 2; [0031-0039]).
Response to Arguments
Applicant’s arguments, see the remarks, filed 02/02/26, with respect to the rejection(s) of claim(s) 1-19 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Saito et al. (US PGPub 2005/0224945, hereinafter referred to as “Saito”).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 May 29, 2026
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