CTNF 17/693,150 CTNF 97637 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-3, 6-8, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190088798 A1) hereinafter “Kim” in view of Ju et al. (US 20230260998 A1) hereinafter “Ju.” Regarding Claim 1 , Figures 1-3B and 19-20 of Kim teach: An integrated circuit structure (Paragraph 0021), comprising: a first vertical arrangement of horizontal nanowires (126); a second vertical arrangement of horizontal nanowires (128); a P-type (Paragraph 0032; Where the epitaxial layers include p-type impurities) gate stack (282) over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer (272) over a first gate dielectric (combination of 252 and 312), the first gate dielectric comprising a first dipole material layer (312; Figure 20); an N-type (Paragraph 0032; Where the epitaxial layers include n-type impurities) gate stack (284 and 184) over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer (274) over a second gate dielectric (combination of 254 and 314), the second gate dielectric comprising a second dipole material layer (314; Figure 19); and a dielectric wall (220) laterally between the P-type gate stack and the N-type gate stack, the dielectric wall comprising a single dielectric material layer Kim does not teach: the dielectric wall continuous from the P-type gate stack to the N-type gate stack and the single dielectric material layer in direct contact with the first gate dielectric of the P-type gate stack and with the second gate dielectric of the N-type gate stack. Figure 28 of Ju teaches: a multi-gate device (Paragraph 0008) with a dielectric fin (270A-1) continuous from a P-type gate stack (202A-2) to an N-type gate stack (202A-1); wherein the dielectric fin is in direct contact with the first gate dielectric (372 in the region of 202A-2) of the P-type gate stack and with the second gate dielectric (372 in the region of 202A-1) of the N-type gate stack. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric wall continuous from the P-type gate stack to the N-type gate stack and the single dielectric material layer in direct contact with the first gate dielectric of the P-type gate stack and with the second gate dielectric of the N-type gate stack because Ju teaches dielectric walls separate and/or isolate device features and/or transistor features within a transistor region from one another (Ju Paragraph 0031). Regarding Claim 2 , Figures 1-3B and 19-20 of Kim teach: the first dipole material layer (312) comprises an oxide of La (Paragraph 0110). Regarding Claim 3 , Figures 1-3B and 19-20 of Kim teach: the second dipole material layer (314) comprises an oxide of Al (Paragraph 0106). Regarding Claim 6 , Figures 1-3B and 19-20 of Kim teach: An integrated circuit structure (Paragraph 0021), comprising: a first vertical arrangement of horizontal nanowires (126); a second vertical arrangement of horizontal nanowires (128); a first P-type (Paragraph 0032; Where the epitaxial layers include p-type impurities) gate stack (282) over the first vertical arrangement of horizontal nanowires, the first P-type gate stack having a first P-type conductive layer (272) over a first gate dielectric (combination of 252 and 312), the first gate dielectric comprising a first dipole material layer (Figure 20; 312); a second P-type (Paragraph 0032; Where the epitaxial layers include p-type impurities.) gate stack (284 and 184) over the second vertical arrangement of horizontal nanowires, the second P-type gate stack having a second P-type conductive layer (274) over a second gate dielectric (254) comprising a second dipole material layer (Figure 19; 314), wherein the second P- type gate stack is different than the first P-type gate stack (Paragraph 0023; Where the first and second p-type gate stacks are in different voltage regions.); and a dielectric wall (220) laterally between the P-type gate stack and the P-type gate stack, the dielectric wall comprising a single dielectric material layer Kim does not teach: the dielectric wall continuous from the P-type gate stack to the P-type gate stack and the single dielectric material layer in direct contact with the first gate dielectric of the P-type gate stack and with the second gate dielectric of the P-type gate stack. Figure 28 of Ju teaches: a multi-gate device (Paragraph 0008) with a dielectric fin (270A-1) continuous from a P-type gate stack (202A-2) to an P-type gate stack (202B-1); wherein the dielectric fin is in direct contact with the first gate dielectric (372 in the region of 202A-2) of the P-type gate stack and with the second gate dielectric (372 in the region of 202B-1) of the P-type gate stack. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric wall continuous from the P-type gate stack to the P-type gate stack and the single dielectric material layer in direct contact with the first gate dielectric of the P-type gate stack and with the second gate dielectric of the P-type gate stack because Ju teaches dielectric walls separate and/or isolate device features and/or transistor features within a transistor region from one another (Ju Paragraph 0031). Regarding Claim 7 , Figures 1-3B and 19-20 of Kim teach: the first dipole material layer (312) comprises an oxide of La (Paragraph 0110). Regarding Claim 8 , Figures 1-3B and 19-20 of Kim teach: the second dipole material layer (314) comprises an oxide of Al (Paragraph 0106). Regarding Claim 11 , Figures 1-3B and 19-20 of Kim teach: An integrated circuit structure (Paragraph 0021), comprising: a first vertical arrangement of horizontal nanowires (126); a second vertical arrangement of horizontal nanowires (128); a first N-type (Paragraph 0032; Where the epitaxial layers include n-type impurities) gate stack (282) over the first vertical arrangement of horizontal nanowires, the first N-type gate stack having a first N-type conductive layer (272) over a first gate dielectric (combination of 252 and 312), the first gate stack comprising a first dipole material layer (Figure 20; 312); a second N-type (Paragraph 0032; Where the epitaxial layers include n-type impurities.) gate stack (284 and 184) over the second vertical arrangement of horizontal nanowires, the second N-type gate stack having a second N-type conductive layer (274) over a second gate dielectric (254) , the second gate dielectric comprising a second dipole material layer (Figure 19; 314), wherein the second N- type gate stack is different than the first N-type gate stack (Paragraph 0023; Where the first and second n-type gate stacks are in different voltage regions.); and a dielectric wall (220) laterally between the N-type gate stack and the N-type gate stack, the dielectric wall comprising a single dielectric material layer Kim does not teach: the dielectric wall continuous from the N-type gate stack to the N-type gate stack and the single dielectric material layer in direct contact with the first gate dielectric of the N-type gate stack and with the second gate dielectric of the N-type gate stack. Figure 28 of Ju teaches: a multi-gate device (Paragraph 0008) comprising an N-type transistor region (202A; Paragraph 0015) with a dielectric fin (270A-1) continuous from an N-type gate stack (202A-2) to an N-type gate stack (202A-1); wherein the dielectric fin is in direct contact with the first gate dielectric (372 in the region of 202A-2) of the N-type gate stack and with the second gate dielectric (372 in the region of 202A-1) of the N-type gate stack. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric wall continuous from the N-type gate stack to the N-type gate stack and the single dielectric material layer in direct contact with the first gate dielectric of the N-type gate stack and with the second gate dielectric of the N-type gate stack because Ju teaches dielectric walls separate and/or isolate device features and/or transistor features within a transistor region from one another (Ju Paragraph 0031). Regarding Claim 12 , Figures 1-3B and 19-20 of Kim teach: the first dipole material layer (312) comprises an oxide of La (Paragraph 0110). Regarding Claim 13 , Figures 1-3B and 19-20 of Kim teach: the second dipole material layer (314) comprises an oxide of Al (Paragraph 0106) . 07-21-aia AIA Claim s 4-5, 9-10, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190088798 A1) hereinafter “Kim” in view of Ju et al. (US 20230260998 A1) hereinafter “Ju” and Hsu et al. (US 20230120117 A1) hereinafter “Hsu.” Regarding Claim 4 , the combination of Kim and Ju teaches all of the limitations of the claimed invention as stated above. Kim does not teach: the first or the second dipole material layer has a thickness in the range of 1-3 Angstroms. Figure 19A of Hsu teaches: a nanostructure FET (100) with a dipole layer (144) formed over a dielectric layer (142) wherein the thickness of the dipole layer is in the range of 2-9 Angstroms (Paragraph 0068). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first or the second dipole material layer has a thickness in the range of 1-3 Angstroms because Hsu teaches a dipole layer with a thickness in the range of 2-9 Angstroms can change the threshold voltage of the device (Hsu Paragraph 0068). Further, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, 1-3 Angstroms, overlaps the range of Hsu, 2-9 Angstroms. Regarding Claim 5 , the combination of Kim and Ju teaches all of the limitations of the claimed invention as stated above. Kim does not teach: the first or the second dipole material layer has a thickness in the range of 4-6 Angstroms. Figure 19A of Hsu teaches: a nanostructure FET (100) with a dipole layer (144) formed over a dielectric layer (142) wherein the thickness of the dipole layer is in the range of 2-9 Angstroms (Paragraph 0068). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first or the second dipole material layer has a thickness in the range of 4-6 Angstroms because Hsu teaches a dipole layer with a thickness in the range of 2-9 Angstroms can change the threshold voltage of the device (Hsu Paragraph 0068). Further, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, 4-6 Angstroms, lies inside the range of Hsu, 2-9 Angstroms. Regarding Claim 9 , the combination of Kim and Ju teaches all of the limitations of the claimed invention as stated above. Kim does not teach: the first or the second dipole material layer has a thickness in the range of 1-3 Angstroms. Figure 19A of Hsu teaches: a nanostructure FET (100) with a dipole layer (144) formed over a dielectric layer (142) wherein the thickness of the dipole layer is in the range of 2-9 Angstroms (Paragraph 0068). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first or the second dipole material layer has a thickness in the range of 1-3 Angstroms because Hsu teaches a dipole layer with a thickness in the range of 2-9 Angstroms can change the threshold voltage of the device (Hsu Paragraph 0068). Further, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, 1-3 Angstroms, overlaps the range of Hsu, 2-9 Angstroms. Regarding Claim 10 , the combination of Kim and Ju teaches all of the limitations of the claimed invention as stated above. Kim does not teach: the first or the second dipole material layer has a thickness in the range of 4-6 Angstroms. Figure 19A of Hsu teaches: a nanostructure FET (100) with a dipole layer (144) formed over a dielectric layer (142) wherein the thickness of the dipole layer is in the range of 2-9 Angstroms (Paragraph 0068). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first or the second dipole material layer has a thickness in the range of 4-6 Angstroms because Hsu teaches a dipole layer with a thickness in the range of 2-9 Angstroms can change the threshold voltage of the device (Hsu Paragraph 0068). Further, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, 4-6 Angstroms, lies inside the range of Hsu, 2-9 Angstroms. Regarding Claim 14 , the combination of Kim and Ju teaches all of the limitations of the claimed invention as stated above. Kim does not teach: the first or the second dipole material layer has a thickness in the range of 1-3 Angstroms. Figure 19A of Hsu teaches: a nanostructure FET (100) with a dipole layer (144) formed over a dielectric layer (142) wherein the thickness of the dipole layer is in the range of 2-9 Angstroms (Paragraph 0068). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first or the second dipole material layer has a thickness in the range of 1-3 Angstroms because Hsu teaches a dipole layer with a thickness in the range of 2-9 Angstroms can change the threshold voltage of the device (Hsu Paragraph 0068). Further, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, 1-3 Angstroms, overlaps the range of Hsu, 2-9 Angstroms. Regarding Claim 15 , the combination of Kim and Ju teaches all of the limitations of the claimed invention as stated above. Kim does not teach: the first or the second dipole material layer has a thickness in the range of 4-6 Angstroms. Figure 19A of Hsu teaches: a nanostructure FET (100) with a dipole layer (144) formed over a dielectric layer (142) wherein the thickness of the dipole layer is in the range of 2-9 Angstroms (Paragraph 0068). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first or the second dipole material layer has a thickness in the range of 4-6 Angstroms because Hsu teaches a dipole layer with a thickness in the range of 2-9 Angstroms can change the threshold voltage of the device (Hsu Paragraph 0068). Further, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed range, 4-6 Angstroms, lies inside the range of Hsu, 2-9 Angstroms . 07-21-aia AIA Claim s 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190088798 A1) hereinafter “Kim” in view of Ju et al. (US 20230260998 A1) hereinafter “Ju” and Ma et al. (US 20200185501 A1) hereinafter “Ma.” Regarding Claim 16 , Figures 1-3B and 19-20 of Kim teach: An integrated circuit structure (Paragraph 0021), comprising: a first vertical arrangement of horizontal nanowires (126); a second vertical arrangement of horizontal nanowires (128); a P-type (Paragraph 0032; Where the epitaxial layers include p-type impurities) gate stack (282 and 182) over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer (272) over a first gate dielectric (combination of 252 and 312), the first gate dielectric comprising a first dipole material layer (312; Figure 20); an N-type (Paragraph 0032; Where the epitaxial layers include n-type impurities) gate stack (284 and 184) over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer (274) over a second gate dielectric (combination of 254 and 314), the second gate dielectric comprising a second dipole material layer (314; Figure 19); and a dielectric wall (220) laterally between the P-type gate stack and the N-type gate stack, the dielectric wall comprising a single dielectric material layer Kim does not teach: the dielectric wall continuous from the P-type gate stack to the N-type gate stack and the single dielectric material layer in direct contact with the first gate dielectric of the P-type gate stack and with the second gate dielectric of the N-type gate stack. Figure 28 of Ju teaches: a multi-gate device (Paragraph 0008) with a dielectric fin (270A-1) continuous from a P-type gate stack (202A-2) to an N-type gate stack (202A-1); wherein the dielectric fin is in direct contact with the first gate dielectric (372 in the region of 202A-2) of the P-type gate stack and with the second gate dielectric (372 in the region of 202A-1) of the N-type gate stack. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric wall continuous from the P-type gate stack to the N-type gate stack and the single dielectric material layer in direct contact with the first gate dielectric of the P-type gate stack and with the second gate dielectric of the N-type gate stack because Ju teaches dielectric walls separate and/or isolate device features and/or transistor features within a transistor region from one another (Ju Paragraph 0031). Kim does not teach: A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure Figures 18A-21 of Ma teach: a computing device (1400), comprising a board (Paragraph 0144) that utilizes components (Paragraph 0143) comprising integrated circuits (Paragraph 0143). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a computing device, comprising a board and a component coupled to the board because Ma teaches integrated circuit devices are commonly used in computing devices that include boards and one or more components (Ma Paragraph 0143). Regarding Claim 17 , the combination of Kim, Ju, and Ma teaches all of the limitations of the claimed invention as stated above. Kim does not teach: a memory coupled to the board. Figure 21 of Ma teaches: a memory (1404) coupled to the board (Paragraph 0144) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a memory coupled to the board because Ma teaches a memory device is commonly used in computing devices as suitable for the application (Ma Paragraph 0144). Regarding Claim 18 , the combination Kim, Ju, and Ma teaches all of the limitations of the claimed invention as stated above. Kim does not teach: a communication chip coupled to the board. Figure 21 of Ma teaches: a communication chip (1412) coupled to the board (Paragraph 0144) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a communication chip coupled to the board because Ma teaches a communication chip is commonly used in computing devices as suitable for the application (Ma Paragraph 0144). Regarding Claim 19 , the combination Kim, Ju, and Ma teaches all of the limitations of the claimed invention as stated above. Kim does not teach: a battery coupled to the board. Figure 21 of Ma teaches: a battery (1414) coupled to the board (Paragraph 0150) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a battery coupled to the board because Ma teaches a battery is used as a separate energy source (Ma Paragraph 0150). Regarding Claim 20 , the combination of Kim, Ju, and Ma teaches all of the limitations of the claimed invention as stated above. Kim does not teach: the component is a packaged integrated circuit die. Figure 20 of Ma teaches: a component is a packaged integrated circuit die (Paragraph 0139) It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the component be a packaged integrated circuit die because Ma teaches a package integrated circuit die is a common component in computing devices (Ma Paragraph 0140). Response to Arguments 07-38-02 Applicant’s arguments, see Applicant’s Remarks, filed 04/13/2026, with respect to the rejections of Claims 1, 6, and 11 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim and Ju. 07-38-02 Applicant’s arguments, see Applicant’s Remarks, filed 04/13/2026, with respect to the rejections of Claim 16 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim, Ju, and Ma. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HALEE CRAMER/Examiner, Art Unit 2891 /MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891 Application/Control Number: 17/693,150 Page 2 Art Unit: 2891 Application/Control Number: 17/693,150 Page 3 Art Unit: 2891 Application/Control Number: 17/693,150 Page 4 Art Unit: 2891 Application/Control Number: 17/693,150 Page 5 Art Unit: 2891 Application/Control Number: 17/693,150 Page 6 Art Unit: 2891 Application/Control Number: 17/693,150 Page 7 Art Unit: 2891 Application/Control Number: 17/693,150 Page 8 Art Unit: 2891 Application/Control Number: 17/693,150 Page 9 Art Unit: 2891 Application/Control Number: 17/693,150 Page 10 Art Unit: 2891 Application/Control Number: 17/693,150 Page 11 Art Unit: 2891 Application/Control Number: 17/693,150 Page 12 Art Unit: 2891 Application/Control Number: 17/693,150 Page 13 Art Unit: 2891 Application/Control Number: 17/693,150 Page 14 Art Unit: 2891 Application/Control Number: 17/693,150 Page 15 Art Unit: 2891
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