DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/2/2026 has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Chinese Application Serial Number 202111639302.X, filed on 12/29/2021.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Applicant's amendments on 05/22/2026 have been reviewed and entered. The Applicant has amended claims 15 and 21, canceled claim 35m, and added claim 36 as a new claim. Claims 15-25, 27-34, and 36 remain for examination.
Applicant’s amendment to claim 21 has overcome the objection previously set forth in the Final Office Action mailed on 3/25/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 21-25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-066 (US 2019/0288066 A1) in views of Lee-956 (US 2007/0034956 A1), Yan (CN 107819026 A) and Lu (US 2009/0194785 A1).
Regarding claim 21, Lee-066 teaches a method for manufacturing (Figs. 4A-F, [0077]) a semiconductor device (power semiconductor device, Fig. 4F, [0077]), comprising:
forming a first well region (first conductivity type drift region 200, Fig. 4B, [0079]) having a first conductivity type ([0079]: “first conductivity type”) in a substrate (comprising substrate 110, first conductivity type buried layer 130, second conductivity type buried layer 150, and active region 170, Fig. 4A, [0078]);
forming a second well region (second conductivity type body region 250, Fig. 4B, [0081]) having a second conductivity type ([0081]: “second conductivity type”) in the substrate (comprising substrate 110, first conductivity type buried layer 130, second conductivity type buried layer 150, and active region 170, Fig. 4A), wherein the first conductivity type ([0079]: first conductivity type is N-type) is different from the second conductivity type ([0081]: second conductivity type is P-type);
forming a gate structure (comprising gate insulating layer 310 and gate electrode 300, Fig. 4B, [0080]) over the first well region (first conductivity type drift region 200, Fig. 4B) and the second well region (second conductivity type body region 250, Fig. 4B);
forming a spacer (spacer 330, Fig. 4C, [0082]) on a sidewall (left and right sidewalls in Fig. 4C) of the gate structure (gate insulating layer 310 and gate electrode 300, Fig. 4C);
forming a source region (first conductivity type source region 430, Fig. 4C, [0082]) in the second well region (second conductivity type body region 250, Fig. 4C) and a first doped region of a drain region (first conductivity type drain region 410, Fig. 4C, [0082]) in the first well region (first conductivity type drift region 200, Fig. 4C), wherein the source region (first conductivity type source region 430, Fig. 4C) and the first doped region of the drain region (first conductivity type drain region 410, Fig. 4C) both have the first conductivity type (first conductivity type), the spacer (spacer 330, the portion on the right sidewall, Fig. 4C) is between the gate structure (gate insulating layer 310 and gate electrode 300, Fig. 4C) and the first doped region of the drain region (first conductivity type drain region 410, Fig. 4C) and laterally spaced apart from the first doped region (first conductivity type drain region 410, Fig. 4C) of the drain region (first conductivity type drain region 410, Fig. 4C) by the first well region (first conductivity type drift region 200, Fig. 4C);
forming a resist protective layer (protection layer 600, Fig. 4D, [0083]) to cover a sidewall (right sidewall, Fig. 4D) of the spacer (spacer 330, Fig. 4D), a portion of the first well region (first conductivity type drift region 200, Fig. 4D), and a portion of the first doped region of the drain region (first conductivity type drain region 410, Fig. 4C) and in direct contact with a portion (the portion of the first conductivity type drift region 200 between the spacer 330 and first conductivity type drain region 410, Fig. 4D) of the first well region (first conductivity type drift region 200, Fig. 4D).
Lee-066, however, does not teach that the method comprises
forming the source region and the first doped region of the drain region simultaneously;
forming a second doped region of the drain region in the first well region, wherein the second doped region of the drain region has the second conductivity type and in contact with the first doped region of the drain region; and
prior to forming the source region in the second well region, forming a third doped region in the substrate and overlapping the second well region, wherein the third doped region has a top surface lower than a top surface of the second well region, and a portion of the source region is embedded in the third doped region.
Yan, on the other hand, teaches an LDMOS transistor (Fig. 2, [0044]), which is analogous (with opposite conductivity types for individual regions) to the semiconductor device manufactured by the method of Lee-066 in that the first well region corresponds to drift region 2 (Fig. 2, [0049]), the second well region corresponds to body region 3 (Fig. 2, [0050]), source region corresponds to source region 6 (Fig. 2, [0052]), first doped region of the drain corresponds to drain region 7 (Fig. 2, [0053]). Yan further teaches that the semiconductor device also includes
a second doped region of the drain region (hole injection region 9, Fig. 2, [0054]) in the first well region (drift region 2, Fig. 2), wherein the second doped region of the drain region (hole injection region 9, Fig. 2) has the second conductivity type (P+-type, Fig. 2, [0039]) and in contact (see Fig. 2) with the first doped region of the drain region (drain region 7, Fig. 2).
Yan further teaches that including a hole injection region having a depth larger than the drain region 7 and located outside the drain region provides the benefit of reducing the drift region resistance and, consequently, the on-resistance ([0039]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Lee-066 according to the teachings of Yan, to form a second doped region of the drain region with the second conductivity type in the first well region, in contact with the first doped region of the drain region, as taught by Yan, which would provide the benefit of reducing the on-resistance of the semiconductor device.
Lee-066 and Yan, however, do not teach that the method comprises
forming the source region and the first doped region of the drain region simultaneously; and
prior to forming the source region in the second well region, forming a third doped region in the substrate and overlapping the second well region, wherein the third doped region has a top surface lower than a top surface of the second well region, and a portion of the source region is embedded in the third doped region.
Lee-956, on the other hand, teaches a method for manufacturing a semiconductor device (high voltage p-type metal-oxide semiconductor (HVP-MOS) device, Figs. 2-12, Abstract and [0017]) including a source region (source region 46, Fig. 8; [0030]) in the second well region (HVNW region 28, Fig. 8), a first doped region of a drain region (drain region 44, Fig. 8; [0030]) and a second doped region of the drain (N+ region 54, Fig. 8; [0031]) in the first well region (HVPW region 26, Fig. 6), wherein the method comprises
forming the source region (source region 46, Fig. 6) and the first doped region of the drain region (drain region 44, Fig. 6) simultaneously (Fig. 6 and [0030]).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor devices manufactured by the method of Lee-066 in view of Yan and Lee-956 are analogous (high voltage LDMOS devices) to each other, with conductivity types of analogous regions in Lee-066 in view of Yan and Lee-956 are flipped with respect to each other. Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would also realize that source region and the first doped region of the drain region in both Lee-066 in view of Yan and Lee 956 are formed by ion implantation (see Lee-066, [0082] and Lee-956, [0030]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the source region and first doped region of the drain region in Lee-066 in view of Yan simultaneously, as taught by Lee-956, to reduce the number of processing steps in the manufacturing process and the overall manufacturing time.
The combination of Lee-066, Yan and Lee-956, however, does not teach
prior to forming the source region in the second well region, forming a third doped region in the substrate and overlapping the second well region, wherein the third doped region has a top surface lower than a top surface of the second well region, and a portion of the source region is embedded in the third doped region.
Lu, on the other hand, teaches a lateral MOSFET structure (Fig. 17, [0101]), wherein
prior to forming the source region (n++ emitter region 5, Fig. 17, [0066] and [0101]: “The collector and the emitter of an IGBT structure are called a drain and a source, respectively, in the corresponding MOSFET structure” which is shown in Fig. 17) in the second well region (p-type body region 4 (analogous to the second well region), Fig. 17, [0105]), forming a third doped region (p+ low-resistivity region 41, Figs. 5-6, [0073]-[0074]: the p+ low-resistivity region 41 is formed before forming n++ emitter region 5) in the substrate (SOI substrate, Fig. 17, [0070]) and overlapping the second well region (p-type body region 4, Figs. 6 and 17), wherein the third doped region (p+ low-resistivity region 41, Fig. 6) has a top surface (top surface of the p+ low-resistivity region 41, Fig. 6) lower than a top surface of the second well region (top surface of p-type body region 4, Figs. 6 and 17), and a portion of the source region (n++ emitter region 5, Fig. 17) is embedded in the third doped region (p+ low-resistivity region 41, Fig. 17).
Lu further discloses that including forming a third doped region as disclosed by Lu provides the benefit of suppressing the latch-up phenomenon, and thereby increasing the short circuit ruggedness of the device manufactured ([0091]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include steps in the method of Lee-066 in views of Yan and Lee-956 for forming a third doped region as taught by Lu to be able to increase the short circuit ruggedness of the device manufactured.
Thus, the combination of Lee-066, Yan, Lee-956, and Lu meets all the limitations of claim 21.
Regarding claim 22, Lee-066 in views of Yan, Lee-956, and Lu teaches the method of claim 21, wherein
the combination of Lee-066, Yan, Lee-956, and Lu further teaches that the second doped region of the drain region (hole injection region 9 (see Yan, Fig. 2) included in the semiconductor device manufactured by the method Lee-066 according to the teachings of Yan; see claim 21 rejection above) is deeper than the first doped region of the drain region (see claim 21 rejection above).
Regarding claim 23, Lee-066 in views of Yan, Lee-956, and Lu teaches the method of claim 21, wherein
the combination of Lee-066, Yan, Lee-956, and Lu further teaches that the second doped region of the drain region (Yan’s hole injection region 9 introduced into the method of Lee-066 (see claim 21 rejection above)) is shallower (Yan discloses that the depth of the hole injection region 9 is less than the depth of the drift region 2 which is equivalent to first well conductivity type drift region 200 of Lee-066, [0054]) than the first well region (first conductivity type drift region 200 of Lee-066, Fig. 4F of Lee-066).
Regarding claim 24, Lee-066 in views of Yan, Lee-956, and Lu teaches the method of claim 21, wherein
the combination of Lee-066, Yan, Lee-956, and Lu further teaches that the second doped region of the drain region (Yan’s hole injection region 9 introduced into the method of Lee-066 (see claim 21 rejection above)) is deeper (Yan discloses that the depth of the hole injection region 9 larger than the depth of drain region 7 [0054]) than the source region (first conductivity type source region 430 of Lee-066, Fig. 4F: because the source region 430 and the first conductivity type drain region 410 have the sane depth in Lee-0066, in the method of Lee-066 modified by Yan, the second doped region of the drain is formed to be deeper than the source region.).
Regarding to claim 25, Lee-066 in views of Yan, Lee-956, and Lu teaches the method of claim 21, wherein
The combination of Lee-066, Yan, Lee-956, and Lu further teaches that the first doped region of the drain region (first conductivity type drain region 410, Fig. 4F of Lee-066) is between the gate structure (comprising gate insulating layer 310 and gate electrode 300, Fig. 4F of Lee-066) and the second doped region of the drain region (Yan’s hole injection region 9 introduced into the method of Lee-066 (see claim 21 rejection above) such that the hole injection region 9 is on the right side of the first conductivity type drain region 410 in Fig. 4F).
Regarding to claim 27, Lee-066 in views of Yan, Lee-956, and Lu teaches the method of claim 21, wherein
The combination of Lee-066, Yan, Lee-956, and Lu further teaches that the resist protective layer (protection layer 600, Fig. 4F, [0083]) is in contact with the first doped region of the drain region (first conductivity type drain region 410, Fig. 4F) but is spaced apart from the second doped region of the drain region (Yan’s hole injection region 9 is introduced on the right side of the first conductivity type drain region 410 in the semiconductor device manufactured by method of Lee-066 (see Fig. 4F and claim 21 rejection above). Since the resist protective layer reaches only to the left portion of the top surface of the first conductivity type drain region 410 in Fig. 4F, the resist protective layer is spaced apart from the second doped region of the drain in the semiconductor device of Lee-066 modified by the teachings of Yan.).
Allowable Subject Matter
Claims 15-20, 28-34, and 36 are allowed, where claims 15, 21, and 28 are independent claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 15-20 and 36, independent claim 15, now disclosing the limitation that “prior to forming the source region in the third well region, forming a third doped region in the substrate and overlapping the first well region and the third well region, wherein the third doped region has a top surface lower than a top surface of the third well region, and a portion of the source region is embedded in the third doped region”, overcame the 35 U.S.C. 103 rejection based on Lee-956 (US 2007/0034956 A1) in views of Wei (US 2009/0008711 A1) and Yan (CN 107819026 A) made in the final office action which was mailed on 3/25/2026.
Regarding relevant prior art, the combination of Lee-956, Wei, Yan, and a new prior art, Lu (US 2009/0194785 A1), is identified as the closest prior art to the invention disclosed in claim 15. Accordingly, Lee-956 teaches a method for manufacturing a semiconductor device (high voltage p-type metal-oxide semiconductor (HVP-MOS) device, Figs. 2-12, Abstract and [0017]), comprising:
forming a first well region (N+ buried layer 22, Fig. 2; [0025]) and a second well region (doped semiconductor layer 24, Fig. 3; [0026]) in a substrate (substrate 20, Figs. 2-3, [0025]);
forming a third well region (high-voltage n-well (HVNW) region 28, Fig. 4; para. 0027]) in the second well region (high-voltage p-well (HVPW) region 26, Fig. 4; [0027]: to associate the regions of Lee-956 to specific regions of the current application, the two parts of the doped semiconductor layer 24 were identified as second and third well regions, respectively, as above);
forming a gate structure (gate dielectric 60 and gate electrode 62, Fig. 8; [0038]) over the second well region (HVPW region 26, Fig. 8) and the third well region (HVNW region 28, Fig. 8), such that an interface of the second well region and the third well region (the interface between HVPW region 26 and HVNW region 28, Fig. 8) extends downward from the gate structure (a gate dielectric 60 and a gate electrode 62, Fig. 8);
performing a first implantation process (Fig. 6, [0030]) with first dopants (p-type dopant, [0030]) to form a source region (source region 46, Fig. 6; [0030]) in the third well region (HVNW region 28, Fig. 6; [0030]) and a first doped region (drain region 44, Fig. 6; [0030]) in the second well region (HVPW region 26, Fig. 6; [0030]); and
performing a second implantation process (Fig. 7, [0031]) with second dopants (n-type dopant, [0031]) having a conductivity type different from the first dopants (p-type dopant implantation, [0030]) to form a second doped region (N+ region 54, Fig. 7; [0031]) such that a drain region including the first doped region (drain region 44, Fig. 7) and the second doped region (N+ region 54, Fig. 7) is defined and the first doped region (drain region 44, Fig. 7) of the drain region is between the source region (source region 46, Fig. 7) and the second doped region (N+ region 54, Fig. 7) of the drain region; and
prior to forming the source region in the third well region, forming a third doped region in the substrate and overlapping the first well region and the third well region, wherein the third doped region has a top surface lower than a top surface of the third well region, and a portion of the source region is embedded in the third doped region.
Lee-956, however, does not teach that the first implantation process with first dopants and the second implantation with second dopants are performed after forming the gate structure, and
a vertical distance between a bottom surface of the first doped region of the drain region and a bottom surface of the second doped region of the drain region is less than a depth of the second doped region of the drain region and is greater than a distance between the bottom surface of the second doped region of the drain region and a bottom surface of the second well region, and
prior to forming the source region in the third well region, forming a third doped region in the substrate and overlapping the first well region and the third well region, wherein the third doped region has a top surface lower than a top surface of the third well region, and a portion of the source region is embedded in the third doped region.
Wei, on the other hand, teaches a method for manufacturing semiconductor device (high-voltage metal-oxide semiconductor (HVMOS) device, Figs. 2-9, Abstract and [0014]) wherein the method comprises
after forming the gate structure (gate dielectrics 50, gate electrodes 52 and spacers 54, Fig. 7, [0028]), performing a first implantation process (p-type impurity implantation, Fig. 8, [0029]) with first dopants (p-type, [0029]); and
performing a second implantation process (n-type impurity implantation, Fig. 9, [0030]) with second dopants (n-type, [0030]) having a conductivity type different from the first dopants (p-type, [0029]).
The device structures disclosed by Lee and Wei are similar, except that the drain region in Wei does not include a second area. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the method disclosed by Wei provides an alternative to the method of Lee in terms of forming the drain and source regions and the gate structure. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify Lee-956’s method of manufacturing such that the drain and source regions and the gate structure are formed by the method disclosed by Wei, which would provide the benefit of protecting channel region of the device, and stabilizing the channel resistance, due to the usage of the gate electrode as an extra mask during ion implantation for forming the source and drain regions (evidenced by Nishizawa (JP 2011100913 A, [0011] and [0020], see also claim 28 rejection below)).
Furthermore, Wei further discloses that “one skilled in the art will realize that the order of forming N +regions, P+ regions and gates is a matter of mere design choice.” ([0030], where N+ regions are formed by the second implantation and P+ regions are formed by the first implantation), which indicates that the first and second implantation processes in Lee-956’s method can be alternatively performed after forming the gate structure as disclosed by Wei. Therefore, a prima facie case of obviousness exists, because the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (MPEP 2144.04 (IV)), see also In reBurhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results)).
The combination of Lee-956 and Wei, however, does not teach that
a vertical distance between a bottom surface of the first doped region of the drain region and a bottom surface of the second doped region of the drain region is less than a depth of the second doped region of the drain region and is greater than a distance between the bottom surface of the second doped region of the drain region and a bottom surface of the second well region,
prior to forming the source region in the third well region, forming a third doped region in the substrate and overlapping the first well region and the third well region, wherein the third doped region has a top surface lower than a top surface of the third well region, and a portion of the source region is embedded in the third doped region.
Yan, on the other hand, teaches an LDMOS transistor (Fig. 2, [0044]), which is analogous (with opposite conductivity types for individual regions) to the semiconductor device manufactured by the method of Lee-956 in view of Wei in that the first well region corresponds to semiconductor substrate 1 (Fig. 2, [0049]), the second well region corresponds to drift region 2 (Fig. 2, [0049]), the third well region corresponds to body region 3 (Fig. 2, [0050]), source region corresponds to source region 6 (Fig. 2, [0052]), first doped region of the drain corresponds to drain region 7 (Fig. 2, [0053]) and the second doped region corresponds to hole injection region 9 (Fig. 2, [0054]). Yan further teaches that that in the LDMOS device of Yan
a vertical distance (see distance D1 in Illustrative Fig. 1 which is an annotated version of Yan’s Fig. 2) between a bottom surface of the first doped region of the drain region (drain region 7, Illustrative Fig. 1, [0053]) and a bottom surface (dashed horizontal line, Illustrative Fig. 1) of the second doped region of the drain region (hole injection region 9, Illustrative Fig. 1, [0054]) is less than a depth (D2, Illustrative Fig. 1) of the second doped region of the drain region (hole injection region 9, Illustrative Fig. 1) and is greater than a distance (D3, Illustrative Fig. 1) between the bottom surface of the second doped region of the drain region (hole injection region 9, Illustrative Fig. 1) and a bottom surface of the second well region (drift region 2, Illustrative Fig. 1, [0049]; also see [0027]: “A further improvement is that the knot depth of the hole injection region is less than or equal to the knot depth of the drift region”, meaning that the distance D3 can be as small as zero.).
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Yan further discloses that the depth of the hole injection region 9 being larger than the depth pf the drain region 7 provides the benefit of reducing the on-resistance when the device is turned on ([0025]), and a further improvement is that the knot depth of the hole injection region 9 is less than or equal to the knot depth of the drift region ([0027]: this implies that the D1 is larger than D3, as shown in Illustrative Fig. 1, as the depth of the hole injection layer 9 can be close to the depth of the drift region 2). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Lee-956 in view of Wei according to the teachings of Yan, to form the first doped region and second doped region such that a vertical distance between a bottom surface of the first doped region of the drain region and a bottom surface of the second doped region of the drain region is less than a depth of the second doped region of the drain region and is greater than a distance between the bottom surface of the second doped region of the drain region and a bottom surface of the second well region, which would provide the benefit of reducing the on-resistance of the semiconductor device.
The combination of Lee-956, Wei, and Yan, however, do not teach that
prior to forming the source region in the third well region, forming a third doped region in the substrate and overlapping the first well region and the third well region, wherein the third doped region has a top surface lower than a top surface of the third well region, and a portion of the source region is embedded in the third doped region.
Lu, on the other hand, teaches a lateral MOSFET structure (Fig. 17, [0101]), wherein
prior to forming the source region (n++ emitter region 5, Fig. 17, [0066] and [0101]: “The collector and the emitter of an IGBT structure are called a drain and a source, respectively, in the corresponding MOSFET structure” which is shown in Fig. 17) in the third well region (p-type body region 4 (analogous to the third well region), Fig. 17, [0105]), forming a third doped region (p+ low-resistivity region 41, Figs. 5-6, [0073]-[0074]: the p+ low-resistivity region 41 is formed before forming n++ emitter region 5) in the substrate (SOI substrate, Fig. 17, [0070]) and overlapping the third well region (p-type body region 4, Figs. 6 and 17), wherein the third doped region (p+ low-resistivity region 41, Fig. 6) has a top surface (top surface of the p+ low-resistivity region 41, Fig. 6) lower than a top surface of the third well region (top surface of p-type body region 4, Figs. 6 and 17), and a portion of the source region (n++ emitter region 5, Fig. 17) is embedded in the third doped region (p+ low-resistivity region 41, Fig. 17).
Lu further discloses that including forming a third doped region as disclosed by Lu provides the benefit of suppressing the latch-up phenomenon, and thereby increasing the short circuit ruggedness of the device manufactured ([0091]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include steps in the method of Lee-956 in views of Wei and Yan for forming a third doped region as taught by Lu to be able to increasing the short circuit ruggedness of the device manufactured.
The combination of Lee-956, Wei, Yan, and Lu however, fails to teach forming a third doped region … overlapping the first well region.
There has been no prior art identified that can, by itself or in combination with others, can render claim 15 anticipated or obvious. Therefore, claim 15 is allowed as the references of the prior art of record considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitation “forming a third doped region … overlapping the first well region”, when this limitation is further accompanied by the remaining limitations of claim 15.
Consequently, claims 16-20 and 36 are also allowed due to their dependency on allowed claim 15.
Regarding claims 28-34, independent claim 28 is allowed, as also indicated in the Final Office Action mailed on 3/25/2026, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that
“after forming the third well region, performing an etching process to the patterned conductive layer and the exposed portion of the gate dielectric layer to form a gate structure over the second well region and the third well region;
and
forming a source region in the third well region and a first doped region of a drain region in the second well region, wherein the source region and the first doped region of the drain region have a first conductivity type”
as recited in claim 28, in combination with remaining limitations of the claim.
Regarding the closest prior art, as also detailed in the Final Office Action, Lee-956 (US 2007/0034956 A1), Hwang (US 2002/0013029 A1) and Nishizawa teaches a method for manufacturing a semiconductor device (high voltage p-type metal-oxide semiconductor (HVP-MOS) device, Figs. 2-12, Abstract and [0017]), comprising:
forming a first well region (N+ buried layer 22, Fig. 2; [0025]) in a substrate (substrate 20, Fig. 2; [0025]);
forming a second well region (doped semiconductor layer 24, Fig. 3; [0026]) in the substrate (substrate 20, Fig. 3) and over the first well region (N+ buried layer 22, Fig. 3);
forming a source region (source region 46, Fig. 6; [0035]) in the third well region (high-voltage n-well (HVNW) region 28, Fig. 8) and a first doped region of a drain region (drain region 44, Fig. 6; [0035]) in the second well region (high-voltage p-well (HVNPW) region 26, Fig. 6), wherein the source region (source region 46, Fig. 6) and the first doped region of the drain region (drain region 44, Fig. 6) have a first conductivity type (p-type dopant, [0030]); and
forming a bulk region (N+ region 56, Fig. 7; [0031]) in the third well region (high-voltage n-well (HVNW) region 28, Fig. 7) and in contact with the source region (source region 46, Fig. 7), wherein the bulk region (N+ region 56, Fig. 7) has a second conductivity type (n-type dopant, [0031]) different from the first conductivity type (p-type dopant, [0030]).
Lee-956, however, does not teach the method for manufacturing a semiconductor device comprises
forming a gate dielectric layer and a conductive layer over the second well region;
patterning the conductive layer to expose a portion of the gate dielectric layer;
after patterning the conductive layer, forming a third well region in the second well region;
after forming the third well region, performing an etching process to the patterned conductive layer and the gate dielectric layer to form a gate structure over the second well region and the third well region; and
the bulk region that is deeper than the source region.
Hwang, on the hand, discloses a high-voltage device (Figs. 1a and 2), wherein the bulk region (P+ bulk region 8’, Fig. 2; [0013]) is deeper than the source region (N+ source region 7, Fig. 2; [0013]), to mitigate the lowering of the maximum operating voltage of the device due to latch-up phenomenon ([0013]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of manufacturing taught by Lee-956 to form a bulk region deeper than the source region, as disclosed by Hwang, to improve the maximum operating voltage of the semiconductor device (Hwang: [0013]).
Lee-956 and Hwang, however, do not teach that the method for manufacturing a semiconductor device comprises
forming a gate dielectric layer and a conductive layer over the second well region;
patterning the conductive layer to expose a portion of the gate dielectric layer;
after patterning the conductive layer, forming a third well region in the second well region;
after forming the third well region, performing an etching process to the patterned conductive layer and the gate dielectric layer to form a gate structure over the second well region and the third well region.
Nishizawa, on the other hand, teaches a method for manufacturing a semiconductor device (DMOS transistor, Figs. 9-13 and 6-8, [0030]), comprising:
forming (Fig. 9, [0030]) a gate dielectric layer (gate oxide film 6, Fig. 9, [0030]) and a conductive layer (gate electrode film 7, Fig. 9, [0030]) over the second well region (N-type silicon substrate 1, Fig. 9, [0030]);
patterning (Fig. 10, [0031]) the conductive layer (gate electrode film 7, Fig. 10) to expose a portion of the gate dielectric layer (gate oxide film 6, Fig. 10);
after patterning the conductive layer (gate electrode film 7, Fig. 10), forming (Figs. 10-11, [0031]-[0032]) a third well region (first body region 5 and second body region 9, Figs. 10-11, para.[0031]-[0032]) in the second well region (N-type silicon substrate 1, Figs. 10-11);
after forming the third well region (first body region 5 and second body region 9, Fig. 11), performing an etching process (Figs. 13 and 6, [0036]-[0037]) to the patterned conductive layer (gate electrode film 7A, Fig. 6, [0037]) and the exposed portion of the gate dielectric layer (gate oxide film 6, Fig. 6: gate oxide film 6 is not labeled in Fig. 6, please refer to Fig. 11; the exposed portion of the gate oxide film is removed in the exposed regions) to form a gate structure (comprising gate electrode film 7A and gate oxide film 6, Fig. 6) over the second well region (N-type silicon substrate 1, Fig. 6) and the third well region (first body region 5 and second body region 9, Fig. 6).
Nishizawa further discloses that forming the second well region, third well region and the gate structure by the method taught by Nishizawa has the advantages of (1) stabilizing the channel resistance by protecting the channel region by using the gate electrode as a mask during ion implantation ([0011] and [0020]), and (2) reducing the risk of misalignment of the doped regions and the photoresist mask ([0021] and [0023]). Therefore, the combination of Lee-956 in view of Hwang with Nishizawa would meet all the limitations of claim 28. However, such a combination is not feasible and lacks motivation due to following reasons: (1) the source region (source region 10, Fig. 12, [0023]) of Nishizawa is also motivated to be formed through the gate dielectric layer (gate oxide film 6, Fig. 12), which is different than the invention in claim 28; and (2) the thick gate dioxide layer on the drain side in Fig 6, prevents the first doped region of the drain in the method Lee-956 in view of Hwang to be formed next to the gate structure (see Fig. 8 of Lee-956). Therefore, combining the teachings of Lee-956 in view of Hwang with Nishizawa would lead structural changes in Lee-956 in view Hwang and motivates a method different than the one disclosed in claim 28.
There has been no other prior art identified that can, by itself or in combination of others, render the invention disclosed in claim 28 anticipated or obvious. Therefore, claim 28 is allowed.
Accordingly, claims 29-34 are also allowed, because these claims inherit the allowable subject matter from claim 28.
Response to Arguments
It has been acknowledged that the applicant amended claims 15 and 21, canceled claim 35, and added claim 36 as a new claim per response dated on 5/22/2026. Applicant’s arguments with respect to claims have been fully considered.
The Examiner agrees with the Applicant on that the amendments to claims 15 and 21 overcame their corresponding rejections made previously based on prior art Lee-956 (US 2007/0034956 A1) in views of Wei (US 2009/0008711 A1) and Yan (CN 107819026 A) for claim 15, and Lee-066 (US 2019/0288066 A1) in views of Lee-956 and Yan for claim 21.
Regarding independent claim 15, the full incorporation of previously objected claim 35 into claim 15, rendered claim 15 and all its dependent claims (claims 16-20 and 36) allowable, as detailed in the office action above.
While the Applicant also incorporated the subject matter of claim 35 in to independent claim 21, claim 21 fails to become allowable. As also indicated in the Advisory Action mailed on 6/8/2026, the subject matter of claim 35 is allowable when accompanied by all the limitations of claim 21 which claim 35 was depended on. However, claim 21 lack some of the limitations contained in claim 15. Particularly, there is no region analogous to first well region of claim 15 in claim 21 (first and second well regions of claim 21 correspond to second and third well regions of claim 15). Therefore, as detailed in the office action above, claim 21 failed to be allowable and is now rejected under new grounds based on Lee-066, Lee-956 and Yan of the final office action combined with a new prior art, Lu (US 2009/0194785 A1). Claims 22-25 and 27 which are dependent on claim 21 are also rejected by the combination of this new prior art and the prior art of the final office action.
For the purpose of compact prosecution, the Examiner recommends incorporating methodological or structural limitations similar to the ones which rendered independent claims 15 and 28 allowable in to claim 21.
The Examiner is available for an interview at Applicant's convenience if the Applicant would like
to discuss the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Anderson (US 2008/0042196 A1) teaches transistor with a third doped region
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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