DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/18/2026 has been entered.
Response to Arguments
Applicant's arguments filed 4/14/2026 have been fully considered but they are not persuasive.
Regarding Applicant’s argument that Bao fails to teach the amended limitation “wherein the mid-gap conductive layer of the N-type gate stack is on a portion of the P-type conductive layer of the P-type gate stack that is vertically over the first vertical arrangement of horizontal wires” of claim 1 on pages 7-10 of Applicant’s Remarks, Examiner respectfully disagrees.
As the claim is written, it is unknown how the “mid-gap conductive layer of the N-type gate stack is on a portion of the P-type conductive layer of the P-type gate stack that is vertically over the first vertical arrangement of horizontal wires” as it doesn’t appear as such in Applicant’s elected species. There is no portion of the mid-gap conductive layer existing in the region of the P-type gate stack in Applicant’s specification or drawings in area 104, as claim 1 as written appears to require. As such, this limitation will be treated as new matter, as described in the rejection to follow.
It is also unknown how the mid-gap conductive layer can be formed on a portion the P-type conductive layer of the P-type gate stack that is vertically over the first vertical arrangement of horizontal wires unless disposed of after the deposition of the P-type conductive layer. For the purposes of examination, claim 1 will be interpreted to read, “wherein a layer comprising the same material as the mid-gap conductive layer of the N-type gate stack is on a portion of the P-type conductive layer of the P-type gate stack that is vertically over the first vertical arrangement of horizontal wires”, which Bao does teach, as will be in the rejection to follow.
Regarding the Objections to the specification, it does not appear as though Applicant has either acknowledged or mitigated the issues set forth in the non-final of 8/26/25 and final of 2/18/2026, and thus the objections will be repeated below.
Drawings
The drawings are objected to because the element references do not appear to clearly point towards appropriate element. For example, reference 118 appears to point at both 118 and 116 in Fig. 1A in the area 106, and 118 and 112A in area 104. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Status of the Claims
Claims 1-20 are pending in the application and are currently being examined. Claims 1 and 13 have been amended. Claims 7-20 have been withdrawn per the 6/30/25 restriction election. No new claims have been added.
Specification
The disclosure is objected to because of the following informalities: in paragraph [0131], "a gate stacks" appears to be a typo.
Appropriate correction is required.
The use of the terms "Bluetooth", "Wi-Fi", "long term evolution (LTE)", etc., which each are a trade name or a mark used in commerce, have been noted in this application. The terms should be accompanied by the generic terminology; furthermore the terms should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term. THIS IS NOT AN EXHAUSTIVE LIST, PLEASE REVIEW THE SPECIFICATION AND CORRECT ALL INSTANCES OF IMPROPER USE OF TRADE NAMES AND MARKS (found predominately in [0151]).
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, it is unknown how the “mid-gap conductive layer of the N-type gate stack is on a portion of the P-type conductive layer of the P-type gate stack that is vertically over the first vertical arrangement of horizontal wires” as it doesn’t appear as such in Applicant’s elected Fig. 1A. There is no portion of the mid-gap conductive layer existing in the region of the P-type gate stack in the specification or drawings in area 104, as claim 1 as written appears to require. It is unknown how the mid-gap conductive layer can be formed on a portion the P-type conductive layer of the P-type gate stack that is vertically over the first vertical arrangement of horizontal wires unless disposed of after the deposition of the P-type conductive layer. For the purposes of examination, claim 1 will be interpreted to read, “wherein a layer comprising the same material as the mid-gap conductive layer of the N-type gate stack is on a portion of the P-type conductive layer of the P-type gate stack that is vertically over the first vertical arrangement of horizontal wires”.
Claims 2-6 are also rejected for being dependent upon rejected claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (US 9,997,519 B1, hereafter Bao) in view of Lai et al. (US 2023/0178601 A1, hereafter Lai).
Regarding claim 1, in Fig. 6B Bao teaches an integrated circuit structure, comprising:
a first vertical arrangement (see annotated Fig. 6B) of horizontal nanowires (215, column 6, line 14) ;
a second vertical arrangement (see annotated Fig. 6B) of horizontal nanowires (214, column 6, line 12);
a P-type gate stack (see annotated Fig. 6B) over the first vertical arrangement of horizontal nanowires (215), the P-type gate stack having a P-type conductive layer (WF2 metal layer 226 and bottom barrier layer 224/224’, column 6, line 56 and column 6 lines 46-49) over and in direct contact with a first gate dielectric comprising a high-k dielectric layer (218, column 5, lines 47-48) [226 is also a conductive material according to column 4 lines 52-54, column 7 lines 4-6, and column 5 lines 50-51, making it a part of the P-type conductive layer]; and
an N-type gate stack (see annotated Fig. 6B) over the second vertical arrangement of horizontal nanowires (214), the N-type gate stack having a mid-gap conductive layer (top capping layer 212, bottom barrier layer 220, and WF1 metal layer 222, column 5 line 18, column 5 lines 50-51, and column 5 line 61) over and in direct contact with a second gate dielectric (218, see Fig. 5B indicating 218 in both stacks) comprising the high-k dielectric layer (column 5, lines 47-48). [220 and 222 are also conductive materials according to column 4 lines 52-54, column 5 lines 50-51, and column 5 lines 60-61, making it a part of the N-type mid-gap conductive layer], wherein a layer (228, column 7 line 64) comprising the same material as the mid-gap conductive layer (layer 228 is described as comprising the same material as 212 in column 7 lines 5-8) of the N-type gate stack is on a portion of the P-type conductive layer (WF2 metal layer 226 and bottom barrier layer 224/224’) of the P-type gate stack that is vertically over the first vertical arrangement of horizontal wires (215).
Bao fails to teach a dipole material layer. However, Lai teaches a semiconductor device similar to Bao in Fig. 19A which includes a dipole material layer (106, [0059]). This dipole layer is added to the device to allow for the creation of differentials in the electrical potential of the overall gate structure [0059] of Lai. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Bao to include the dipole material as taught by Lai.
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Regarding claim 2, Bao in view of Lai teach the integrated circuit structure of claim 1. Bao further teaches the high-k dielectric layer (218, column 5, lines 47-48) comprises hafnium and oxygen. Column 5, lines 47-49 indicate layer 218 may be comprised of the same material as layer 206, which is said to be hafnium dioxide in column 6 lines 46-47.
Regarding claim 3, Bao in view of Lai teach the integrated circuit structure of claim 1. Lai further teaches in paragraph [0059] the dipole material layer (106, [0059]) comprises an oxide of La, Mg, Y, Ba or Sr.
Regarding claim 4, Bao in view of Lai teach the integrated circuit structure of claim 1. Lai further teaches in paragraph [0059] the dipole material layer has a thickness in the range of 1-3 Angstroms (paragraph [0059] recites a range of 1 Angstrom to 9 Angstroms).
Regarding claim 5, Bao in view of Lai teach the integrated circuit structure of claim 1. Lai further teaches in paragraph [0059] the dipole material layer has a thickness in the range of 4-6 Angstroms (paragraph [0059] recites a range of 1 Angstrom to 9 Angstroms)
Regarding claim 6, Bao in view of Lai teach the integrated circuit structure of claim 1. In Fig. 6B Bao further teaches the P-type conductive layer (WF2 metal layer 226 and bottom barrier layer 224/224’, column 6, line 56 and column 6 lines 46-49) of the P-type gate stack (see annotated Fig. 6B) further extends over the mid-gap conductive layer (top capping layer 212, bottom barrier layer 220, and WF1 metal layer 222, column 5 line 18, column 5 lines 50-51, and column 5 line 61) of the N-type gate stack (see annotated Fig. 6B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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