DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. As Examiner has not had a previous opportunity to examine these amendments, there is no position for Applicant to have previously addressed and therefore no position taken previously to defend. The applicability of the reference(s) to the amended elements is discussed in the claim rejections above for Applicants to now respond to.
Regarding the pending double patenting rejection, Applicant has amended claim 1 to sufficiently differentiate from U.S. Patent No. 12,295,170 B2 (hereafter Lavric), and thus the pending double patenting rejection is rescinded.
Regarding the Objections to the specification, it does not appear as though Applicant has mitigated the issues set forth in the non-final of 8/26/25, and thus the objections will be repeated below.
Status of the Claims
Claims 1-20 are pending in the application and are currently being examined. Claims 1 and 13 have been amended. Claims 7-20 have been withdrawn per the 6/30/25 restriction election. No new claims have been added.
Specification
The disclosure is objected to because of the following informalities: in paragraph [0131], "a gate stacks" appears to be a typo.
Appropriate correction is required.
The use of the terms "Bluetooth", "Wi-Fi", "long term evolution (LTE)", etc., which each are a trade name or a mark used in commerce, have been noted in this application. The terms should be accompanied by the generic terminology; furthermore the terms should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term. THIS IS NOT AN EXHAUSTIVE LIST, PLEASE REVIEW THE SPECIFICATION AND CORRECT ALL INSTANCES OF IMPROPER USE OF TRADE NAMES AND MARKS (found predominately in [0151]).
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (US 9,997,519 B1, hereafter Bao) in view of Lai et al. (US 2023/0178601 A1, hereafter Lai).
Regarding claim 1, in Fig. 6B Bao teaches an integrated circuit structure, comprising:
a first vertical arrangement (see annotated Fig. 6B) of horizontal nanowires (215, column 6, line 14) ;
a second vertical arrangement (see annotated Fig. 6B) of horizontal nanowires (214, column 6, line 12);
a P-type gate stack (see annotated Fig. 6B) over the first vertical arrangement of horizontal nanowires (215), the P-type gate stack having a P-type conductive layer (WF2 metal layer 226 and bottom barrier layer 224/224’, column 6, line 56 and column 6 lines 46-49) over and in direct contact with a first gate dielectric comprising a high-k dielectric layer (218, column 5, lines 47-48) [226 is also a conductive material according to column 4 lines 52-54, column 7 lines 4-6, and column 5 lines 50-51, making it a part of the P-type conductive layer]; and
an N-type gate stack (see annotated Fig. 6B) over the second vertical arrangement of horizontal nanowires (214), the N-type gate stack having a mid-gap conductive layer (top capping layer 212, bottom barrier layer 220, and WF1 metal layer 222, column 5 line 18, column 5 lines 50-51, and column 5 line 61) over and in direct contact with a second gate dielectric (218, see Fig. 5B indicating 218 in both stacks) comprising the high-k dielectric layer (column 5, lines 47-48). [220 and 222 are also conductive materials according to column 4 lines 52-54, column 5 lines 50-51, and column 5 lines 60-61, making it a part of the N-type mid-gap conductive layer].
Bao fails to teach a dipole material layer. However, Lai teaches a semiconductor device similar to Bao in Fig. 19A which includes a dipole material layer (106, [0059]). This dipole layer is added to the device to allow for the creation of differentials in the electrical potential of the overall gate structure [0059] of Lai. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Bao to include the dipole material as taught by Lai.
PNG
media_image1.png
485
815
media_image1.png
Greyscale
Regarding claim 2, Bao in view of Lai teach the integrated circuit structure of claim 1. Bao further teaches the high-k dielectric layer (218, column 5, lines 47-48) comprises hafnium and oxygen. Column 5, lines 47-49 indicate layer 218 may be comprised of the same material as layer 206, which is said to be hafnium dioxide in column 6 lines 46-47.
Regarding claim 3, Bao in view of Lai teach the integrated circuit structure of claim 1. Lai further teaches in paragraph [0059] the dipole material layer (106, [0059]) comprises an oxide of La, Mg, Y, Ba or Sr.
Regarding claim 4, Bao in view of Lai teach the integrated circuit structure of claim 1. Lai further teaches in paragraph [0059] the dipole material layer has a thickness in the range of 1-3 Angstroms (paragraph [0059] recites a range of 1 Angstrom to 9 Angstroms).
Regarding claim 5, Bao in view of Lai teach the integrated circuit structure of claim 1. Lai further teaches in paragraph [0059] the dipole material layer has a thickness in the range of 4-6 Angstroms (paragraph [0059] recites a range of 1 Angstrom to 9 Angstroms)
Regarding claim 6, Bao in view of Lai teach the integrated circuit structure of claim 1. In Fig. 6B Bao further teaches the P-type conductive layer (WF2 metal layer 226 and bottom barrier layer 224/224’, column 6, line 56 and column 6 lines 46-49) of the P-type gate stack (see annotated Fig. 6B) further extends over the mid-gap conductive layer (top capping layer 212, bottom barrier layer 220, and WF1 metal layer 222, column 5 line 18, column 5 lines 50-51, and column 5 line 61) of the N-type gate stack (see annotated Fig. 6B).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights