Prosecution Insights
Last updated: April 19, 2026
Application No. 17/694,330

FLIP CHIP DEVICE THROUGH PACKAGE VIA PLACEMENT

Non-Final OA §102§103
Filed
Mar 14, 2022
Examiner
YEMELYANOV, DMITRIY
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nxp B V
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
393 granted / 538 resolved
+5.0% vs TC avg
Strong +19% interview lift
Without
With
+18.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
43 currently pending
Career history
581
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
22.4%
-17.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I (Claims 1-10 and 20) in the reply filed on 05/13/2025 is acknowledged. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the first solder ball affixed to the first via at the bottom side of the mold compound.” of Claim 6 “a second solder ball affixed to a bottom side of the integrated circuit device.” of Claim 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Akkermans et al. (US 2009/0256752 A1). Regarding Claim 1, Akkerman (Fig. 1) discloses a flip chip device, comprising: a substrate (112, 109, 126) having a top side (top) and a bottom side (buttom); an integrated circuit device (162) affixed to the bottom side of the substrate (Fig. 1); a mold compound (128) applied to the bottom side of the substrate (Fig. 1); and a first via (124) affixed to the bottom side of the substrate (Fig. 1), wherein the first via passes through the mold compound (128) and is exposed at a bottom side of the mold compound (128) (Fig. 1), and wherein the first via (140) is coupled to a first terminal (122) of the integrated circuit device (”nterconnection(s) 122 (as appropriate) to one or more vias, such as via 124” [0033], (“the via 124 (pad 116)”) [0050]. Regarding Claim 2, Akkerman (Fig. 1) discloses the flip chip device of claim 1, further comprising: a second via (140) affixed to the bottom side of the substrate, (Fig. 1) wherein the second via (140) passes through the mold compound (128) and is exposed at the bottom side of the mold compound (128) (Fig. 1), and wherein the second via (140) is coupled to a second terminal (ground terminal on 162) of the integrated circuit device. (162) (“Pads may include ground pad 130 interconnected with ground plane 110 through ground via 140” [0033] “ At least one radio frequency chip, such as chip 162, is spaced inwardly from the feed line 114 and is coupled to the feed line 114 and the ground plane 110.”) [0045] Regarding Claim 3, Akkerman (Fig. 1) discloses the chip device of claim 2, wherein the first via (124) is configured for carrying a radio frequency signal of the integrated circuit device (162). (“Another metal layer is inward from substrate 112 and is used to implement the antenna feed line(s) 114, pads 116, 118, 120 for RF chip connections”) [0033] Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akkermans et al. (US 2009/0256752 A1) in view of Garcia et al. (US 2016/0056544 A1). Regarding Claim 4, Akkerman (Fig. 1) discloses the flip chip device of claim 3. the second terminall (ground terminal on 162) of the integrated circuit device. (162) Akkerman does not explicitly disclose that the second terminal is a shield terminal of the integrated circuit device. Garcia (Fig. 15) discloses that a ground terminal (ground plane 1130) serves as a ground shield [0072]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the flip chip device in Akkerman in view of Garcia such that the second terminal is a shield terminal of the integrated circuit device in order to isolate the RFIC chip from RF energy [0072, 0102] Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akkermans et al. (US 2009/0256752 A1) in view of Ryoo et al. (US 2019/0198995 A1). Regarding Claim 6, Akkerman discloses the flip chip device of claim 1, further comprising: Akkerman does not explicitly disclose a first solder ball affixed to the first via at the bottom side of the mold compound. Ryoo (Fig. 12, 13) discloses a first solder ball (1340) affixed to a first via at abottom side of a mold compound (Fig. 13) [0143] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the flip chip device in Akkerman in view of Ryoo a such that a first solder ball affixed to the first via at the bottom side of the mold compound in order to the baseband signal may be transmitted to the IC of the antenna module through the electrical connection structure [0165] Regarding Claim 7, Akkerman in view of Ryoo discloses the flip chip device of claim 6, further comprising: a second solder ball (1260b) affixed to a bottom side of the integrated circuit device. (1301b) (Ryoo) Regarding Claim 8, Akkerman in view of Ryoo discloses the flip chip device of claim 7, wherein the second solder ball (1290a) provides a ground terminal for the integrated circuit device (1300a) (Ryoo). The Examiner notes that regarding the recitation of “provides a ground terminal for the integrated circuit device”, the manner of operating the device does not differentiate an apparatus claim from the prior art. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987) See MPEP §2114. The recitation of “provides a ground terminal for the integrated circuit device” is an intended use language which does not differentiate the claimed device from the prior art device of Akkerman in view of Ryoo, who teaches the structure of the claim as described above. Regarding Claim 9, Akkerman in view of Ryoo discloses the flip chip device of claim 7, wherein the second solder ball (1290a) provides a thermal terminal for the integrated circuit device (1300a).(Fig. 13 Ryoo) The Examiner notes that regarding the recitation of “provides a ground terminal for the integrated circuit device”, the manner of operating the device does not differentiate an apparatus claim from the prior art. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987) See MPEP §2114. The recitation of “provides a ground terminal for the integrated circuit device” is an intended use language which does not differentiate the claimed device from the prior art device of Akkerman in view of Ryoo, who teaches the structure of the claim as described above. Regarding Claim 10, Akkerman discloses the flip chip device of claim 1. Akkerman does not explicitly disclose a passive device affixed to the bottom side of the substrate. Ryoo (Fig. 12, 13) discloses a passive device (a passive component 1350a) affixed to a bottom side of a substrate. (1250a) [0146] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the flip chip device in Akkerman in view of Ryoo a such that a passive device affixed to the bottom side of the substrate in order to provides an impedance to the IC [0146] Allowable Subject Matter Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner's statement of reasons for allowance: With regards to claim 20, none of the prior art teaches or suggests, alone or in combination, “a second integrated circuit device affixed to the bottom side of the substrate, wherein a first terminal of the first integrated circuit device is coupled to a first terminal of the second integrated circuit device;”…” a second via affixed to the bottom side of the substrate, wherein the second via passes through the mold compound and is exposed at the bottom side of the mold compound, and wherein the second via is coupled to a second terminal of the second integrated circuit device.” in the combination required by the claim. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DMITRIY YEMELYANOV/Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Mar 14, 2022
Application Filed
Feb 22, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+18.7%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allow rate.

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