DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed November 26, 2025 have been entered and considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 9054172 B2), in view of Ugajin (JP H0537043 A).
Regarding claim 1, Hung et al. teaches: An interconnect structure disposed over a substrate [300, Col. 5, Line 52, Fig. 9] comprising:
a dielectric layer [306, Col. 2, Lines 42-43, Fig. 9];
a first conductive feature [408, “source/drain region”, Col. 2, Lines 57-58, Fig. 9] disposed in the dielectric layer [306];
a second conductive feature [314, “first contact plug”, Col. 3, Line 54, Fig. 9] disposed over the first conductive feature [408], wherein the second conductive feature [314] comprises a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom; and a third conductive feature [330, “third contact plug”, Col. 5, Lines 15-16, Fig. 9] disposed over the dielectric layer [306] and adjacent the second conductive feature [314], wherein the third conductive feature [330] comprises a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, and wherein the second [314] and third conductive features [330] are partially overlapping in an axis substantially parallel to a major surface of the substrate [300].
Hung et al. does not teach:
one of the first and second angles is an acute angle, another of the first and second angles is an obtuse angle, and the first and second angles are supplementary.
Ugajin teaches:
one of the first [5, Abstract, Fig. 1] and second [7, Abstract, Fig. 1] angles is an acute angle, another of the first and second angles is an obtuse angle, and the first and second angles are supplementary.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ugajin into the teachings of Hung et al. to include one of the first and second angles is an acute angle, another of the first and second angles is an obtuse angle, and the first and second angles are supplementary, for the purpose of improving performance, efficiency, and versatility.
Regarding claim 2, Hung et al. and Ugajin teach the interconnect structure of claim 1.
Hung et al. further teaches:
wherein the third conductive feature [330] further comprises a barrier layer [324, Col. 4, Line 62, Fig. 9] and a conductive fill material [326, “second metal layer”, Col. 4, Line 63, Fig. 9].
Regarding claim 3, Hung et al. and Ugajin teach the interconnect structure of claim 2.
Hung et al. further teaches:
wherein the conductive fill material [326] and the second conductive feature [314] comprise different materials [Col. 5, Lines 26-28].
Regarding claim 8, Hung et al. and Ugajin teach the interconnect structure of claim 1.
Hung et al. and Ugajin disclose the above claimed subject matter.
However, Hung et al. does not teach:
wherein the first angle is an acute angle, and the second angle is an obtuse angle.
Ugajin teaches:
wherein the first angle [5, Abstract, Fig. 1] is an acute angle, and the second angle [7, Abstract, Fig. 1] is an obtuse angle.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ugajin into the teachings of Hung et al. and Ugajin to include wherein the first angle is an acute angle, and the second angle is an obtuse angle, for the purpose of defining the plurality of conductive features and improving symmetry within the device. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Regarding claim 9, Hung et al. and Ugajin teach the interconnect structure of claim 1.
Hung et al. and Ugajin disclose the above claimed subject matter.
However, Hung et al. does not teach:
wherein the first angle is an obtuse angle, and the second angle is an acute angle.
Ugajin teaches:
wherein the first angle [7, Abstract, Fig. 1] is an obtuse angle, and the second angle [5, Abstract, Fig. 1] is an acute angle.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ugajin into the teachings of Hung et al. and for Ugajin to include wherein the first angle is an obtuse angle, and the second angle is an acute angle, for the purpose of defining the plurality of conductive features and improving symmetry within the device. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Claim 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 9054172 B2), in view of Ugajin (JP H0537043 A) as applied to claim 2 above, and further in view of Chen et al. (CN 105810632 A).
Regarding claim 4, Hung et al. and Ugajin teach the interconnect structure of claim 2.
Hung et al. and Ugajin do not teach:
further comprising a glue disposed between the first conductive feature and the second conductive feature.
Chen et al. teaches:
further comprising a glue layer [110, “etch stop layer”, paragraph [0044], Fig. 1L] disposed between the first conductive feature [104, paragraph [0043], Fig. 1L] and the second conductive feature [142, paragraph [0077-0079], Fig. 1L].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Hung et al. and Ugajin to include further comprising a glue disposed between the first conductive feature and the second conductive feature, for the purpose of improving adhesion between layers.
Regarding claim 5, Hung et al., Ugajin and Chen et al. teach the interconnect structure of claim 4.
Hung et al. further teaches:
further comprising a dielectric spacer [406, “Spacer” Fig. 9] disposed between the second [314] and third conductive features [330] and between the third conductive feature [330] and the dielectric layer [306].
Regarding claim 6, Hung et al., Ugajin, and Chen et al. teach the interconnect structure of claim 5.
Hung et al. further teaches:
further comprising a protect layer [304, “CESL”, Col. 2, Lines 41-42, Fig. 9] disposed between the second conductive feature [314] and the dielectric spacer [406] and between the dielectric layer [306] and the dielectric spacer [406].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 9054172 B2), in view of Ugajin (JP H0537043 A), and Chen et al. (CN 105810632 A) as applied to claim 6 above, and further in view of Woo et al. (US 6509267 B1).
Regarding claim 7, Hung et al., Ugajin, and Chen et al. teach the interconnect structure of claim 6.
Hung et al., Ugajin and Chen et al. do not teach:
further comprising a cap layer disposed between the protect layer and the dielectric layer.
Woo et al. teaches:
further comprising a cap layer [46, Col. 9, Line 49, Fig. 2A] disposed between the protect layer [48, “hard mask layer”, Col. 9, Line 51, Fig. 2A] and the dielectric layer [44, Col. 9, Line 49, Fig. 2A].
It would have been obvious to one of ordinary skill in the art before the effective filing
date of the invention to incorporate the teachings of Woo et al. into the teachings of Hung et al.,
Ugajin, and Chen et al. to include further comprising a cap layer disposed between the
protect layer and the dielectric layer, for the purpose of protecting the underlying materials.
Claims 11-16, 21-22, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 9054172 B2), in view of Woo et al. (US 6509267 B1), and Bielefeld et al. (US 10483160 B2).
Regarding claim 11, Hung et al. teaches:
An interconnect structure disposed over a substrate [300], comprising:
a dielectric layer [306];
a second conductive feature [314] disposed over the first conductive feature [408], wherein the second conductive feature [314] comprises a first top and a first bottom, and
a third conductive feature [330] disposed over the dielectric layer [306] and adjacent the second conductive feature [314], wherein the third conductive feature [330] comprises a second top and a second bottom, wherein the first top of the second conductive feature [314] is located at a first level between the second top and the second bottom of the third conductive feature [330], and the second bottom of the third conductive feature [330] is located at a second level between the first top and the first bottom of the second conductive feature [314].
Hung et al. does not teach:
a first conductive feature disposed in the dielectric layer;
Woo et al. teaches:
a first conductive feature [36, Col. 9, Lines 23-33, Fig. 1i] disposed in the dielectric layer [14, Fig. 1a-1i].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Woo et al. into the teachings of Hung et al. to include a first conductive feature disposed in the dielectric layer, for the purpose of saving space, increasing density, enhancing efficiency of the device, and allowing for better current flow and connectivity thus improving performance. See also, MPEP 2144.04(IV)(C) Changes in Sequence of Adding Ingredients and MPEP 2144.04(VI)(C) Rearrangement of Parts.
Hung et al. and Woo et al. do not teach:
wherein the first bottom is located over a top surface of the dielectric layer.
Bielefeld et al. teaches:
wherein the first bottom [of Conductive Feature (203/204), Col. 11, Lines 25-51, Fig. 2E] is located over a top surface of the dielectric layer [202, Fig. 2E].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Bielefeld et al. into the teachings of Hung et al. and Woo et al. to include the wherein the first bottom is located over a top surface of the dielectric layer, for the purpose of enabling electrical flow through the device, improving signal quality and performance, reducing parasitic capacitance and power consumption. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
It should also be noted that the limitation of “wherein the first bottom is located over a top surface of the dielectric layer.”, can also be seen in Fig. 9 of Hung et al. (US 9054172 B2). The first bottom (of third contact plug [330]) located over a top surface of the dielectric layer [306]. This limitation can be applied to other conductive features within the device.
Regarding claim 12, Hung et al., Woo et al., and Bielefeld et al. teach the interconnect structure of claim 11.
Hung et al. further teaches:
further comprising an etch stop layer [316, Col. 4, Line 20, Fig. 9] disposed on the second [314] and third conductive features [330].
Regarding claim 13, Hung et al., Woo et al., and Bielefeld et al. teach the interconnect structure of claim 11.
Hung et al. further teaches:
wherein a distance between the first level and the second level ranges from about 25 percent of a height of the second conductive feature [314] and about 95 percent of the height.
Regarding claim 14, Hung et al., Woo et al., and Bielefeld et al. teach the interconnect structure of claim 11.
Hung et al. further teaches:
wherein the second conductive feature [314] further comprises a first sidewall, the third conductive feature [330] further comprises a second sidewall, and a distance between the first sidewall and the second sidewall ranges from about 0.5 times to about 1.5 times a width of the third conductive feature [330].
Regarding claim 15, Hung et al., Woo et al., and Bielefeld et al. teach the interconnect structure of claim 11.
Hung et al. further teaches:
further comprising a fourth conductive feature [328, “second contact plug”, Col. 5, Line 14, Fig. 9] disposed over the dielectric layer [306] and a fifth conductive feature [402, “a gate”, Col. 5, Lines 40-41, Fig. 9] disposed over the dielectric layer [306].
Regarding claim 16, Hung et al., Woo et al., and Bielefeld et al. teach the interconnect structure of claim 15.
Hung et al. further teaches: further comprising:
a protect layer [304] in contact with the fourth conductive feature [328] and the fifth conductive feature [402];
a dielectric spacer [406] disposed on the protect layer [304]; and
a dielectric fill material [404] disposed on the dielectric spacer [406], wherein the protect layer [304], the dielectric spacer [406], and the dielectric fill material [404] are disposed between the fourth conductive feature [328] and the fifth conductive feature [402].
Regarding claim 21, Hung et al. teaches:
An interconnect structure disposed over a substrate [300], comprising:
a first dielectric layer [306];
a second dielectric layer [308] disposed over the first dielectric layer [306] and the first conductive line [408];
a conductive via [402] disposed in the second dielectric layer [308];
a second conductive line [314] disposed over the conductive via [402], wherein the second conductive line [314] comprises a first top and a first bottom, and
a conductive feature [330] disposed over the second dielectric layer [308], wherein the conductive feature [330] comprises a second bottom located at a level between the first top and the first bottom of the second conductive line [314].
Hung et al. does not teach:
a first conductive line disposed in the first dielectric layer;
Woo et al. teaches:
a first conductive line [36, Col. 9, Lines 23-33, Fig. 1i] disposed in the first dielectric layer [14, Fig. 1a-1i].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Woo et al. into the teachings of Hung et al. to include a first conductive feature disposed in the dielectric layer, for the purpose of saving space, increasing density, enhancing efficiency of the device, and allowing for better current flow and connectivity thus improving performance. See also, MPEP 2144.04(IV)(C) Changes in Sequence of Adding Ingredients and MPEP 2144.04(VI)(C) Rearrangement of Parts.
Hung et al. and Woo et al. do not teach:
wherein the first bottom is located over a top surface of the dielectric layer.
Bielefeld et al. teaches:
wherein the first bottom [of Conductive Feature (203/204), Col. 11, Lines 25-51, Fig. 2E] is located over a top surface of the dielectric layer [202, Fig. 2E].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Bielefeld et al. into the teachings of Hung et al. and Woo et al. to include wherein the first bottom is located over a top surface of the dielectric layer, for the purpose of enabling electrical flow through the device, improving signal quality and performance, reducing parasitic capacitance and power consumption. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
It should also be noted that the limitation of “wherein the first bottom is located over a top surface of the dielectric layer.”, can also be seen in Fig. 9 of Hung et al. (US 9054172 B2). The first bottom (of third contact plug [330]) located over a top surface of the dielectric layer [306]. This limitation can be applied to other conductive features within the device.
Regarding claim 22, , Hung et al., Woo et al., and Bielefeld et al. teach the interconnect structure of claim 21.
Hung et al. further teaches:
wherein the conductive feature [330] further comprises a second top, wherein the first top of the second conductive line [314] is located at a level between the second top and the second bottom of the conductive feature [330].
Regarding claim 25, Hung et al., Woo et al., and Bielefeld et al. teach the interconnect structure of claim 16.
Hung et al. further teaches:
wherein the protect layer [304, Fig. 9] and the dielectric spacer [406, Fig. 9] are disposed between the second [314, Fig. 9] and third [330, Fig. 9] conductive features.
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 9054172 B2), in view of Woo et al. (US 6509267 B1), and Bielefeld et al. (US 10483160 B2) as applied to claim 21 above, and further in view of Howard et al. (US 6103612 A).
Regarding claim 23, Hung et al., Woo et al., and Bielefeld et al. teach the interconnect structure of claim 21.
Hung et al., Woo et al., and Bielefeld et al. do not teach:
further comprising a dielectric spacer disposed around the conductive feature.
Howard et al. teaches:
further comprising a dielectric spacer [48, Col. 8, Lines 27-29, Fig. 1] disposed around the conductive feature [54, “stud formed from an electrically conductive material”, Col. 8, Lines 42-43, Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Howard et al. into the teachings of Hung et al., Woo et al., and Bielefeld et al. to include further comprising a dielectric spacer disposed around the conductive feature, for the purpose of electrically isolating the conductive feature from certain areas of electrical activity.
Regarding claim 24, Hung et al., Woo et al., Bielefeld et al. and Howard et al. teach the interconnect structure of claim 23.
Hung et al., Woo et al., and Bielefeld et al. do not teach:
wherein the dielectric spacer is a conformal layer.
Howard et al. teaches:
wherein the dielectric spacer [48] is a conformal layer. [Col. 8, Lines 27-29].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Howard et al. into the teachings of Hung et al., Woo et al., and Bielefeld et al. to include wherein the dielectric spacer is a conformal layer, for the purpose of uniform thickness throughout the layer, resulting in low stress and excellent dielectric properties.
Response to Arguments
Applicant’s arguments, see page 1, Section: Claim Rejection – 35 U.S.C. 103, in remarks filed November 26, 2025, with respect to the rejections of claims 1-3 and 8-9 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ugajin (JP H0537043 A). Ugajin teaches: one of the first [5, Abstract, Fig. 1] and second [7, Abstract, Fig. 1] angles is an acute angle, another of the first and second angles is an obtuse angle, and the first and second angles are supplementary. One of ordinary skill in the art would have been motivated to modify primary reference Hung et al. (US 9054172 B2) with the limitation from Ugajin (JP H0537043 A) for the purpose of improving performance, efficiency, and versatility. It should be noted that supplementary angles are a known limitation in the art, and a well-known mathematical principle. Applicant has the burden of proof to explain as to what unexpected and unobvious results come from supplementary angles of features within the device. See MPEP 2144.04(IV)(B) Changes in Shape. See also, MPEP 716.02(b) Burden on Applicant, (I) Burden on Applicant to Establish Results are Unexpected and Significant, and MPEP 716.01(d) Weighing Objective Evidence.
Applicant's arguments on pages 1-2, Section: Claim Rejection – 35 U.S.C. 103, in remarks filed November 26, 2025, with respect to the rejections of claims 11-16, 21-22, and 25 under 35 U.S.C. §103, have been fully considered but they are not persuasive. Applicant argues that the combination of Hung et al. (US 9054172 B2) and Woo et al. (US 6509267 B1) would not be obvious. Examiner disagrees with Applicant for the following reasons: the limitation of “a first conductive feature disposed in the dielectric layer” is a known limitation in the art; a conductive feature disposed in a dielectric layer does not contribute any unexpected or unobvious results. See, MPEP 716.02(b) Burden on Applicant, (I) Burden on Applicant to Establish Results are Unexpected and Significant; MPEP 716.01(d) Weighing Objective Evidence; and MPEP 2144.04(VI)(C) Rearrangement of Parts. One of ordinary skill in the art would be motivated to modify the current prior art of record (Hung et al. US 9054172 B2) with the limitation from Woo et al. (US 6509267 B1) for the purpose of saving space, increasing density, enhancing efficiency of the device, and allowing for better current flow and connectivity thus improving performance.
Applicant's arguments on pages 2-3, Section: Claim Rejection – 35 U.S.C. 103, in remarks filed November 26, 2025, with respect to the rejections of claims 11-16, 21-22, and 25 under 35 U.S.C. §103, have been fully considered but they are not persuasive. Applicant argues that the combination of Hung et al. (US 9054172 B2) and Bielefeld et al. (US 10483160 B2) would not be obvious. Examiner disagrees with Applicant for the following reasons: the limitation of “wherein the first bottom is located over a top surface of the dielectric layer” is a known limitation in the art; a first bottom located over a top surface of a dielectric layer does not contribute any unexpected or unobvious results. See, MPEP 716.02(b) Burden on Applicant, (I) Burden on Applicant to Establish Results are Unexpected and Significant; MPEP 716.01(d) Weighing Objective Evidence; and MPEP 2144.04(VI)(C) Rearrangement of Parts. The limitation of a first bottom located over a top surface of a dielectric layer can also be seen in primary reference Hung et al. (US 9054172 B2). The first bottom (of third contact plug [330]) located over a top surface of the dielectric layer [306]. This limitation can be applied to other conductive features within the device. Applicant argues that secondary reference Bielefeld et al. (US 10483160 B2) teaches the limitation of “wherein the first bottom is located over a top surface of the dielectric layer” due to the presence of an air gap [171, Fig. 1J], and Hung et al and Woo et al. do not teach an air gap and therefore the references shouldn’t be combined. Examiner agrees with Applicant, however, Bielefeld et al., Fig. 2E discloses a device similar to that in Fig. 1J but without the air gap. By Applicant’s arguments, the limitation of “wherein the first bottom is located over a top surface of the dielectric layer” can be overcome by Bielefeld et al. (US 10483160 B2), Fig. 2E. One of ordinary skill in the art would be motivated to modify the current prior art of record (Hung et al. US 9054172 B2) with the limitation from Bielefeld et al. (US 10483160 B2) for the purpose of enabling electrical flow through the device, improving signal quality and performance, reducing parasitic capacitance and power consumption.
Applicant's arguments on page 3, Section: Claim Rejection – 35 U.S.C. 103, in remarks filed November 26, 2025, with respect to the rejections of claims 23-24 under 35 U.S.C. §103, have been fully considered but they are not persuasive. Applicant argues that claims 23-24 depend on independent claim 21, and claims 23-24 should now be in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
In summary, Applicant’s arguments regarding previously presented secondary reference Liao et al. (US 11302641 B2) are persuasive, however, the argued limitations of claims 1-3 and 8-9 can be overcome by newly cited source Ugajin (JP H0537043 A). Applicant’s arguments regarding secondary references Woo et al. (US 6509267 B1) and Bielefeld et al. (US 10483160 B2) are not persuasive for at least the reasons mentioned above. All claims directly or indirectly dependent on independent claims 1, 11 and 21 are rejected for at least the reasons mentioned above.
Conclusion
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/D.M.H./Examiner, Art Unit 2815 02/12/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815