DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/20/26 has been entered.
Claim Objections
Claim 17 is objected to because “and the both first and second” is a typographical error that should be changed to “and both the
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 10-16 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claim 10 recites the limitation “the back surface of the semiconductor chip is closer to the base than the front surface of the semiconductor chip is closer to the base”. The metes and bounds of the claimed limitation can not be determined for the following reasons: the limitation uses “closer” twice in an illogical way that makes it unclear what the geometric relationship between the back surface, the front surface, and the base is required to be.
Claims 11-16 depend from claim 10 and inherit its deficiencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-6, 10-11, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0057352 A1 (“Agarwal”).
Agarwal teaches, for example:
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[Annotated version of Fig. 13, having added the dotted oval underneath chip 305]
Agarwal teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A semiconductor package (see e.g. annotated version of Fig .13, above) on a base (e.g. 332), comprising:
a semiconductor chip (e.g. 305) comprising a first chip pad (the pads on the chips are not explicitly disclosed; rather, Agarwal merely teaches that the chip has interconnects 126, which may be solder bumps, see para 41; one of ordinary skill in the art would recognize that solder bumps on a chip connect to pads, and that the first chip pad could be the one connecting to e.g. the second-to-left interconnect 126 on chip 105 in Fig. 13) and a second chip pad (the pads on the chips are not explicitly disclosed; rather, Agarwal merely teaches that the chip has interconnects 126, which may be solder bumps, see para 41; one of ordinary skill in the art would recognize that solder bumps on a chip connect to pads, and that the second chip pad connects to e.g. the rightmost interconnect 126 on chip 105 in Fig. 13); and
a redistribution layer (RDL) structure (see dotted oval in annotated version of Fig. 13, above) partially covering the semiconductor chip and separated from the base by the semiconductor chip (see Fig. 13), wherein the RDL structure comprises:
a redistribution layer (RDL) trace (see longer trace laterally extending from left-to-right in dotted oval in annotated version of Fig. 13) having a first end (e.g. left end) and a second end (e.g. right end) on the same RDL trace, wherein the first end of the RDL trace is electrically coupled to the first chip pad (through the interconnect 126), and the second end of the RDL trace is electrically coupled to the second chip pad (through the interconnect 126), and
a first redistribution layer (RDL) pad (see pad/via on the bottom of the longer trace that laterally extends from left-to-right in the dotted oval),
wherein the first RDL pad is disposed on a first side of the RDL trace (e.g. bottom side) and both the first and second chip pads are disposed on a second side of the RDL trace that is opposite to the first side of the RDL trace (e.g. top side),
wherein an overlapping area between the RDL structure and the semiconductor chip is the same size as an area of the RDL structure in a top view (see Fig. 13, wherein the entirety of the interconnect structure falls within the lateral extent of the chip’s sidewalls).
2. The semiconductor device as claimed in claim 1, wherein a boundary of the RDL structure is located within a boundary of the semiconductor chip in a top view (see e.g. Fig. 13; because the boundaries of the RDL structure are within the lateral extent of the chip in side view in Fig. 13, they would be within the boundary in a top view).
4. The semiconductor device as claimed in claim 1, wherein the area of the RDL structure is greater than 50% but less than 100% of an area of the semiconductor chip in the top view (see Fig. 13).
5. The semiconductor device as claimed in claim 1, wherein the first redistribution layer (RDL) pad is electrically coupled to the RDL trace (see Fig. 13).
6. The semiconductor device as claimed in claim 5, wherein the first RDL pad is disposed between the first end and the second end of the RDL trace and within a boundary of the RDL trace (see Fig. 13).
10. A semiconductor package (see e.g. annotated version of Fig .13, above) disposed on a base (e.g. 332), comprising:
a semiconductor chip (e.g. 305) having a front surface (bottom of 305, as shown in Fig. 13) and a back surface (top of 305) opposite to the front surface,
wherein the back surface of the semiconductor chip is closer to the base than the front surface of the semiconductor chip is [[closer]] to the base (see Fig. 13; it is assumed that the second instance of “closer” is not actually desired by Applicant, based on the disclosed orientations in the Figures); and
a redistribution layer (RDL) structure (see dotted oval in annotated version of Fig. 13, above) disposed on the front surface of the semiconductor chip, overlapping and electrically coupled to a first chip pad (the pads on the chips are not explicitly disclosed; rather, Agarwal merely teaches that the chip has interconnects 126, which may be solder bumps, see para 41; one of ordinary skill in the art would recognize that solder bumps on a chip connect to pads, and that the first chip pad could be the one connecting to e.g. the second-to-left interconnect 126 on chip 105 in Fig. 13) and a second chip pad (the pads on the chips are not explicitly disclosed; rather, Agarwal merely teaches that the chip has interconnects 126, which may be solder bumps, see para 41; one of ordinary skill in the art would recognize that solder bumps on a chip connect to pads, and that the second chip pad connects to e.g. the rightmost interconnect 126 on chip 105 in Fig. 13) of the semiconductor chip,
wherein the RDL structure is disposed without overlapping a third chip pad (e.g. that which would connect to the leftmost 126 on chip 305 in Fig. 13) of the semiconductor chip,
wherein the RDL structure comprises:
a redistribution layer (RDL) trace (see longer trace laterally extending from left-to-right in dotted oval in annotated version of Fig. 13), and
a first redistribution layer (RDL) pad (see pad/via on the bottom of the longer trace that laterally extends from left-to-right in the dotted oval),
wherein the first RDL pad is disposed on a first side (e.g. bottom side) of the RDL trace and both the first and second chip pads are disposed on a second side (e.g. top side) of the RDL trace that is opposite to the first side of the RDL trace,
wherein an overlapping area between the RDL structure and the semiconductor chip is the same size as an area of the RDL structure in a top view (see Fig. 13, wherein the entirety of the interconnect structure falls within the lateral extent of the chip’s sidewalls).
11. The semiconductor device as claimed in claim 10, wherein the redistribution layer (RDL) trace has a first end and a second end on the same RDL trace, the first end of the RDL trace is electrically coupled to the first chip pad, and the second end of the RDL trace is electrically coupled to the second chip pad (see Fig. 13).
16. The semiconductor device as claimed in claim 10, wherein the third chip pad of the semiconductor chip is disposed between a sidewall of the RDL structure and a sidewall of the semiconductor chip (see Fig. 13).
17. A semiconductor package (see e.g. annotated version of Fig .13, above) disposed on a base (e.g. 332), comprising:
a semiconductor chip (e.g. 305) comprising
a first chip pad (the pads on the chips are not explicitly disclosed; rather, Agarwal merely teaches that the chip has interconnects 126, which may be solder bumps, see para 41; one of ordinary skill in the art would recognize that solder bumps on a chip connect to pads, and that the first chip pad could be the one connecting to e.g. the second-to-left interconnect 126 on chip 105 in Fig. 13),
a second chip pad (the pads on the chips are not explicitly disclosed; rather, Agarwal merely teaches that the chip has interconnects 126, which may be solder bumps, see para 41; one of ordinary skill in the art would recognize that solder bumps on a chip connect to pads, and that the second chip pad connects to e.g. the rightmost interconnect 126 on chip 105 in Fig. 13) and
a third chip pad (the pads on the chips are not explicitly disclosed; rather, Agarwal merely teaches that the chip has interconnects 126, which may be solder bumps, see para 41; one of ordinary skill in the art would recognize that solder bumps on a chip connect to pads, and that the second chip pad connects to e.g. the leftmost interconnect 126 on chip 105 in Fig. 13); and
a redistribution layer (RDL) structure (see dotted oval in annotated version of Fig. 13, above) overlapping a portion of the semiconductor chip and separated from the base by the semiconductor chip (see Fig. 13),
wherein the RDL structure is electrically coupled to the first chip pad and the second chip pad of the semiconductor chip (see Fig. 13),
wherein a sidewall of the RDL structure is disposed laterally between the first chip pad of the semiconductor chip and the third chip pad of the semiconductor chip (see Fig. 13), and
wherein the RDL structure comprises:
a redistribution layer (RDL) trace (see longer trace laterally extending from left-to-right in dotted oval in annotated version of Fig. 13), and
a first redistribution layer (RDL) pad (see pad/via on the bottom of the longer trace that laterally extends from left-to-right in the dotted oval),
wherein the first RDL pad is disposed on a first side (e.g. bottom side) of the RDL trace and both the first and second chip pads are disposed on a second side (e.g. top side) of the RDL trace that is opposite to the first side of the RDL trace,
wherein an overlapping area between the RDL structure and the semiconductor chip is the same size as an area of the RDL structure in a top view (see Fig. 13, wherein the entirety of the interconnect structure falls within the lateral extent of the chip’s sidewalls).
18. The semiconductor device as claimed in claim 17, wherein the RDL structure overlaps the first chip pad and the second chip pad of the semiconductor chip, without overlapping the third pad of the semiconductor chip (see Fig. 13).
19. The semiconductor device as claimed in claim 17, wherein the first chip pad and the second chip pad of the semiconductor chip are respectively in contact with a first end (e.g. left end) and a second end (e.g. right end) of the same first redistribution layer (RDL) trace of the RDL structure.
20. The semiconductor device as claimed in claim 17, wherein the first redistribution layer (RDL) pad is electrically coupled to the first RDL trace (see Fig. 13).
Allowable Subject Matter
Claim(s) 8-9 and 21 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 8, 9, or 21, including:
8. The semiconductor device as claimed in claim 5, further comprising: a bonding wire electrically coupled to the first RDL pad and a second RDL pad of the RDL structure.
9. The semiconductor device as claimed in claim 1, further comprising: a substrate between the base and the semiconductor chip, wherein the semiconductor chip is disposed on the substrate; and
a bonding wire electrically coupled to a third chip pad of the semiconductor chip and a bonding pad of the substrate,
wherein the third chip pad is exposed from the RDL structure.
21. The semiconductor device as claimed in claim 20, wherein the RDL structure further comprises: a second redistribution layer (RDL) pad overlapping a second RDL trace separated from the first RDL trace, wherein the second RDL pad is electrically coupled to the first RDL pad through a bonding wire.
The other claims each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim(s) 12-14 would be allowable if rewritten to overcome the rejection(s) under pre-AIA 35 U.S.C. 112, 2nd paragraph, set forth in this Office action, and if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 12, including:
12. The semiconductor device as claimed in claim 11, wherein the first redistribution layer (RDL) pad is electrically coupled to the first chip pad and the second chip pad of the semiconductor chip through the RDL trace, and electrically coupled to the third chip pad of the semiconductor chip through a bonding wire.
The other claims each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896