DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding the rejections under 35 USC 102 and 103, Applicant’s arguments and amendments have been fully considered but are moot as further search and consideration have prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20120025862A1 (“Chumakov”) in view of US 20190371726 A1 (“Liao”).
RE: Claim 1, Chumakov discloses A device (200, [0039], FIGs. 2a-2d) comprising:
a silicon wafer (combination of 201, 202; 201, 202 have the same configuration as 101, 102 which are made of silicon, [0044],[0008]) comprising:
a number of die (adjacent semiconductor chips, [0039]); and
a scribe area (scribe lines, [0017]; test structure is implemented in scribe lines, [0017]) between and mutually separating the number of die (test structure 270 is provided between adjacent semiconductor chips, [0039]; accordingly, the scribe lines would be between and mutually separate the chips/die), the scribe area between at least two die of the number of die (the scribe lines would be between chips which is plural and therefore the scribe lines would be between at least two chips/die) comprising
a test structure (270 in FIG. 2a) comprising:
a p-doped region (202D or 202K, The test structure 270 may comprise one or more interconnect chain structures 260A, 260B, [0039]; the chain structure 260B may be provided in the form of a generally P-type conductive path in the associated active regions, wherein, also in this case, the active regions 202D, 202K may be provided in the form of transistor-type regions, [0050], FIG. 2a);
an n-doped region (202B or 202F, the branch 260A may be provided so as to have a general N-type conductivity, wherein, for instance, the active regions 202B, 202F may be provided as transistor-like active regions, [0050], FIG. 2a) adjacent to the p-doped region;
a first contact (rightmost combination of 231, 242 over 202D or rightmost 231, 242 over 202K in 260B as shown in Annotated FIG. 2a below) electrically coupled to the p-doped region and extending from the p-doped region (FIG. 2a shows a first 231 extending from 202D or 202K; Chumakov teaches elements 231 may be provided so as to connect the plurality of active regions 202A . . . 202L with the plurality of metal regions 242, [0040], [0042]; a conductive path may be established in the interconnect chain structure 260A by means of the plurality of semiconductor regions 202A, 202B, 202G, 202E, 202R, the associated contact elements 231 and the corresponding metal regions 242, [0040]; accordingly, 231 are electrically coupled to and extend from active regions 202D, 202K),
a second contact (rightmost combination of 231, 242 over 202B or rightmost 231, 242 over 202F in 260A as shown in Annotated FIG. 2a below) electrically coupled to the n-doped region, extending from the n-doped region (FIG. 2a shows 231 are electrically coupled to and extend from active regions 202B, 202F), and proximate to the first contact defining a pair of contacts with the first contact (In combination, 231, 242 in each of 260A and 260B define a pair of contacts that are proximate to each other in FIG. 2a).
Chumakov does not explicitly disclose:
the first contact extending to a first free end,
the first free end including a first surface distal to the p-doped region;
the first surface exposed for scanning by a testing device to measure reflectivity of the first surface;
the second contact extending to a second free end,
the second free end including a second surface distal to the n-doped region;
the second surface exposed for scanning by the testing device to measure reflectivity of the second surface.
However, Chumakov discloses the semiconductor device 200 may comprise a test structure 270, which may be formed at any appropriate position in the semiconductor device 200. For example, the test structure 270 may be formed within a die region, i.e., within a portion of a semiconductor substrate, in and above which functional circuit portions are formed in accordance with the electrical configuration of the device 200, [0039].
Chumakov further discloses an appropriate dielectric material 241, such as a low-k dielectric material, an ultra low-k dielectric material and the like in which the metal regions 242 are laterally embedded, [0047].
Chumakov further discloses associated contact elements 231 and the corresponding metal regions 242, wherein appropriate contacts 243A, 244A may also be provided in order to enable electrical access of the interconnect chain structure 260A by means of electrical probes and the like, [0040].
Chumakov further discloses any contact open circuit may be detected in the chains 260A, 260B, thereby enabling quantitative evaluation of the probability of creating contact failures in actual device areas, [0051].
In the same field of endeavor, Liao discloses the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies.
Liao further discloses the redistribution structure RDL2 includes more layers of conductive lines and conductive vias. Then, a plurality of conductive connectors 280 are formed on the top surface of the conductive vias 270, and a solder cap 290 may be formed on the top of the conductive connectors 280. In some embodiments, the conductive connectors 280 may be solder bumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, micro bumps, or the like, [0054].
FIG. 28 shows conductive lines 250 and conductive vias 270 embedded in a dielectric layer 230, and conductive vias 270, exposed conductive connectors 280 and exposed solder caps 290 extending upward from the conductive lines 250, the conductive connectors 280 and solder caps 290 extending upward to free ends thereof and include top surfaces distal to the conductive lines 250 and conductive vias 270.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect vias, exposed conductive connectors, and exposed solder caps extending upward from respective metal regions 242, each solder cap extending to a free end thereof as taught by Liao in order to improve electrical access to the metal regions 242.
As a result, modified Chumakov discloses:
the first contact (From Chumakov: rightmost combination of 231, 242 over 202D or rightmost 231, 242 over 202K in 260B as shown in Annotated FIG. 2a below, in combination with a first via, a first exposed conductive connector, and a first exposed solder cap extending to a first free end thereof from Liao) extending to a first free end,
the first free end including a first surface distal to the p-doped region (As modified, the first free end of the first solder cap would include a top surface which would be distal to Chumakov’s 202D or 202K);
the first surface exposed for scanning by a testing device to measure reflectivity of the first surface (As modified, the top surface of the first solder cap would be exposed; further the limitation “for scanning by a testing device to measure reflectivity of the first surface,” is considered an intended use limitation. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations, see MPEP 2114; accordingly, since the top surface of the first solder cap is exposed, it satisfies the intended use limitation of being capable of being used for scanning by a testing device to measure reflectivity of its surface);
the second contact (From Chumakov: rightmost combination of 231, 242 over 202B or rightmost 231, 242 over 202F in 260A as shown in Annotated FIG. 2a below, in combination with a second via, a second exposed conductive connector, and a second exposed solder cap extending to a second free end thereof from Liao) extending to a second free end,
the second free end including a second surface distal to the n-doped region (As modified, the second free end of the second solder cap would include a top surface which would be distal to Chumakov’s 202B or 202F);
the second surface exposed for scanning by the testing device to measure reflectivity of the second surface (As modified, the top surface of the second solder cap would be exposed; further the limitation “for scanning by the testing device to measure reflectivity of the second surface,” is considered an intended use limitation. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations, see MPEP 2114; accordingly, since the top surface of the second solder cap is exposed, it satisfies the intended use limitation of being capable of being used for scanning by a testing device to measure reflectivity of its surface).
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Annotated FIG. 2a of Chumakov
RE: Claim 2, Chumakov in view of Liao discloses The device of claim 1 (see Annotated FIG. 2a below),
wherein the p-doped region (202D) extends in a first direction (Annotated FIG. 2a below shows 202D extending in a diagonal direction),
wherein the n-doped region (202B) extends in the first direction alongside the p-doped region (FIG. 2a shows 202B extending in the diagonal direction alongside 202D), and
wherein the test structure further comprises:
a third contact (From Chumakov: leftmost combination of 242, 231 over 202D in FIG. 2a; there are two 231 and two 242 extending from 202D in FIG. 2a in combination with a third via, a third exposed conductive connector, and a third exposed solder cap extending to a third free end thereof from Liao) electrically coupled to the p-doped region, extending from the p-doped region to a third free end (From Chumakov: leftmost 231 is electrically coupled to and extends from 202D, [0040]; As modified the third exposed solder cap extends to the third free end thereof), and separate from the first contact in the first direction (leftmost 242, 231 over 202D is separated from rightmost 242, 231 over 202D in the diagonal direction by 280 in FIG. 2a),
the third free end including a third surface distal to the p-doped region (As modified, the third free end of the third solder cap would include a top surface which would be distal to Chumakov’s 202D or 202K),
the third surface exposed for scanning by the testing device to measure reflectivity of the third surface (As modified, the top surface of the third solder cap would be exposed; Further, the limitation “for scanning by a testing device to measure reflectivity of the third surface,” is considered an intended use limitation. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations, see MPEP 2114; accordingly, since the top surface of the third solder cap is exposed, it satisfies the intended use limitation of being capable of being used for scanning by a testing device to measure reflectivity of its surface); and
a fourth contact (From Chumakov: leftmost combination of 231, 242 over 202B in FIG. 2a in combination with a fourth via, a fourth exposed conductive connector, and a fourth exposed solder cap extending to a fourth free end thereof from Liao) electrically coupled to the n-doped region, extending from the n-doped region to a fourth free end (leftmost 231 is electrically coupled to and extends from 202B, [0040]; As modified the fourth exposed solder cap extends to the fourth free end thereof), and proximate to the third contact relative to the first contact (leftmost 231, 242 over 202B is proximate leftmost 231,242 over 202D relative to rightmost 231, 242 over 202D in FIG. 2a) defining another pair of contacts with the third contact (As modified leftmost 231, 242, the fourth via, the fourth exposed conductive connector, the fourth exposed solder cap over 202B and leftmost 231, 242, the third via, a third exposed conductive connector, and the third exposed solder cap over 202D would define another pair of contacts),
the fourth free end including a fourth surface distal to the n-doped region (As modified, the fourth free end of the fourth solder cap would include a top surface which would be distal to Chumakov’s 202B),
the fourth surface exposed for scanning by the testing device to measure reflectivity of the fourth surface (As modified, the top surface of the fourth solder cap would be exposed; further the limitation “for scanning by the testing device to measure reflectivity of the fourth surface,” is considered an intended use limitation. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations, see MPEP 2114; accordingly, since the top surface of the fourth solder cap is exposed, it satisfies the intended use limitation of being capable of being used for scanning by a testing device to measure reflectivity of its surface).
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Annotated FIG. 2a from Chumakov
RE: Claim 3, Chumakov in view of Liao discloses The device of claim 2, wherein the test structure further comprises a buffer (230 / 233, [0046]-[0047], FIG. 2b Chumakov) between the first contact and the third contact and between the second contact and the fourth contact (elements 231 may be provided so as to connect the plurality of active regions 202A . . . 202L with the plurality of metal regions 242 through an interlayer dielectric material system, [0040]; 230 is an interlayer dielectric system, [0047]; FIG. 2b shows that contact elements 231 are positioned within the interlayer dielectric material system 230, 233, so dielectric material in 230, 233 provides a buffer between contacts 231).
RE: Claim 4, Chumakov in view of Liao discloses The device of claim 1 (see Annotated FIG. 2a below),
wherein the p-doped region is a first p-doped region (202K) that extends in a first direction (diagonal direction in FIG. 2a),
wherein the n-doped region is a first n-doped region (202F) that extends in the first direction alongside the first p-doped region (FIG. 2a shows 202F extending in the diagonal direction alongside 202K), and
wherein the test structure further comprises:
a second p-doped region (202D) extending in the first direction alongside the first n-doped region (FIG. 2a shows 202D extending in the diagonal direction alongside 202F);
a second n-doped region (202B) extending in the first direction alongside the second p-doped region (FIG. 2a shows 202B extending in the diagonal direction alongside 202D);
a third contact (From Chumakov: combination of 231, 242 over 202D as shown in Annotated FIG. 2a below in combination with a third via, a third exposed conductive connector, and a third exposed solder cap extending to a third free end thereof from Liao) electrically coupled to the second p-doped region and extending from the second p-doped region to a third free end (231, 242 over 202D in FIG. 2a is electrically coupled to and extends from 202D, [0040]; As modified, the third exposed solder cap extends to the third free end thereof),
the third free end including a third surface (As modified, the third free end of the third solder cap would include a top surface which would be distal to Chumakov’s 202D) distal to the second p- doped region,
the third surface exposed for scanning by the testing device to measure reflectivity of the third surface (As modified, the top surface of the third solder cap would be exposed; Further, the limitation “for scanning by the testing device to measure reflectivity of the third surface,” is considered an intended use limitation. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations, see MPEP 2114; accordingly, since the top surface of the third solder cap is exposed, it satisfies the intended use limitation of being capable of being used for scanning by a testing device to measure reflectivity of its surface); and
a fourth contact (From Chumakov: combination of 231, 242 over 202B as shown in Annotated FIG. 2a below in combination with a fourth via, a fourth exposed conductive connector, and a fourth exposed solder cap extending to a fourth free end thereof from Liao) electrically coupled to the second n-doped region, extending from the second n- doped region to a fourth free end (leftmost 231 is electrically coupled to and extends from 202B, [0040]; As modified the fourth exposed solder cap extends to the fourth free end thereof), and proximate to the third contact (231, 242 over 202B in FIG. 2a is electrically coupled to and extends from 202B, [0040] and is proximate to the third contact as shown in Annotated FIG. 2a below),
the fourth free end including a fourth surface (As modified, the fourth free end of the fourth solder cap would include a top surface which would be distal to Chumakov’s 202B) distal to the second n-doped region,
the fourth surface exposed for scanning by the testing device to measure reflectivity of the fourth surface (As modified, the top surface of the fourth solder cap would be exposed; further the limitation “for scanning by the testing device to measure reflectivity of the fourth surface,” is considered an intended use limitation. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations, see MPEP 2114; accordingly, since the top surface of the fourth solder cap is exposed, it satisfies the intended use limitation of being capable of being used for scanning by a testing device to measure reflectivity of its surface).
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Annotated FIG. 2a from Chumakov
RE: Claim 7, Chumakov in view of Liao discloses The device of claim 1, wherein the wafer further comprises a substrate (202) in which the p-doped region and the n-doped region are arranged (The test structure 270 may thus comprise the active regions 202A, 202B and also any other active regions, as shown in FIG. 2 a, within the semiconductor layer 202, [0048]; 202D, 202K, 202B, 202F are active regions, [0040]), the substrate being p-doped (202D, 202K are p-type, [0050]; accordingly, as 202D, 202K are in the substrate 202, the substrate is p-doped in these regions).
RE: Claim 9, Chumakov in view of Liao discloses The device of claim 1, wherein the test structure further comprises a buffer region between the p-doped region and the n-doped region (The active regions 202A . . . 202L may be provided in a semiconductor layer and may be laterally delineated by an isolation region 202I, such as a shallow trench isolation, as is also previously discussed with reference to the semiconductor device 100, [0040], see FIG. 2b which shows 202I between active regions 202A, 202B).
Claim(s) 5, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chumakov in view of Liao as applied to claim 1 and further in view of US20160233329A1 (“Cheng”).
RE: Claim 5, Chumakov in view of Liao discloses The device of claim 1 wherein the n-doped region comprises a first n- doped region (202B or 202F).
Chumakov in view of Liao does not explicitly disclose wherein the test structure further comprises a second n-doped region under the p-doped region.
However, Chumakov discloses the active regions 202B, 202F of the chain structure 260A may be provided in the form of a transistor-type configuration, [0052].
Chumakov further discloses the active regions 202D and 202K in combination with the conductive line 281B may form a transistor configuration for the chain structure 260B, [0052].
Chumakov further discloses a substrate 201 and semiconductor layer 202 is above the substrate 201, [0044] and that The test structure 270 may thus comprise the active regions 202A, 202B and also any other active regions, as shown in FIG. 2 a, within the semiconductor layer 202, [0048]; 202D, 202K, 202F are active regions, [0040].
Accordingly, active regions 202D, 202K are in semiconductor layer 202, and the substrate 201 is under 202D, 202K.
In the same field of endeavor, Cheng discloses a silicon substrate 1 inside which a differently doped semiconductor composite structure 10 having a longitudinal vertical arrangement is disposed, [0046].
Cheng further discloses composite structure 10 is a multi-level structure formed by transversely alternating n-type semiconductor and p-type semiconductor. The semiconductor composite structure occupies the entire silicon substrate in the transverse direction, [0044].
Cheng further discloses The space charge region formed by the P-type doped semiconductor layers and the N-type doped semiconductor layers introduced in the silicon substrate serves as a high-voltage-resistance layer inserted in the conductive silicon substrate, which improves the voltage resistance of the silicon substrate and hence improves the breakdown voltage of the whole device, [0008].
FIGs. 3-4 of Cheng show multiple p-type regions and n-type regions under the channel 4, wherein an n-type region and a p-type region are under each of the source electrode 6, gate electrode 8, and drain electrode 7.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate 201 in Chumakov to include the composite structure including transversely alternating n-type semiconductor and p-type semiconductor as taught by Cheng in order to improve the voltage resistance of the silicon substrate. As a result, a second n-doped region in the substrate 201 would be under 202D or 202K.
RE: Claim 8, Chumakov in view of Liao discloses The device of claim 1, wherein the p-doped region comprises a first p-doped region (202D or 202K).
Chumakov in view of Liao does not explicitly disclose wherein the test structure further comprises a second p-doped region under the first p-doped region and the n-doped region.
However, Chumakov discloses the active regions 202B, 202F of the chain structure 260A may be provided in the form of a transistor-type configuration, [0052].
Chumakov further discloses the active regions 202D and 202K in combination with the conductive line 281B may form a transistor configuration for the chain structure 260B, [0052].
Chumakov further discloses a substrate 201 and semiconductor layer 202 is above the substrate 201, [0044] and that The test structure 270 may thus comprise the active regions 202A, 202B and also any other active regions, as shown in FIG. 2 a, within the semiconductor layer 202, [0048]; 202D, 202K, 202B, 202F are active regions, [0040].
Accordingly, active regions 202D, 202K, 202B, 202F are in semiconductor layer 202, and the substrate 201 is under 202D, 202K, 202B, 202F.
In the same field of endeavor, Cheng discloses a silicon substrate 1 inside which a differently doped semiconductor composite structure 10 having a longitudinal vertical arrangement is disposed, [0046].
Cheng further discloses composite structure 10 is a multi-level structure formed by transversely alternating n-type semiconductor and p-type semiconductor. The semiconductor composite structure occupies the entire silicon substrate in the transverse direction, [0044].
Cheng further discloses The space charge region formed by the P-type doped semiconductor layers and the N-type doped semiconductor layers introduced in the silicon substrate serves as a high-voltage-resistance layer inserted in the conductive silicon substrate, which improves the voltage resistance of the silicon substrate and hence improves the breakdown voltage of the whole device, [0008].
FIGs. 3-4 of Cheng show multiple p-type regions and n-type regions under the channel 4, wherein an n-type region and a p-type region are under each of the source electrode 6, gate electrode 8, and drain electrode 7.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate 201 in Chumakov to include the composite structure including transversely alternating n-type semiconductor and p-type semiconductor as taught by Cheng in order to improve the voltage resistance of the silicon substrate. As a result, a second p-doped region in the substrate 201 would be under 202D, 202K, 202B, 202F.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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