DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 1 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 18 recite “the portion of the cap layer other than the detector active area is monolithic”. There is insufficient antecedent basis for this limitation in the claims, as no portion of the cap layer has been defined.
Claim 1 recites “a low break down voltage”. The underlined portions render the claim indefinite.
The term "low break down voltage" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Furthermore, there is no objective consensus in the art for what speed is considered a low break down voltage. For examination purposes, the Examiner will interpret the claim in light of the specification and claim 2, which requires that the low break down voltage is within 2% of 40 volts.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-13, 15-17, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Forrest (US Patent No. 4,857,982), Sim (US 2020/0313022), Chacinski et al. (“Chancinski” US 2016/0172523), Pan et al. (“Pan” US 2009/0121305), Yang (CN 109346552 A), and Sun et al. (“Sun” US 2025/0015222).
Regarding claim 1, Forrest discloses a photodiode structure (Figure 2), comprising:
a substrate layer (38) comprising strongly-doped indium phosphide (InP) (column 7, lines 12-16);
a buffer layer (40) disposed over the substrate layer and (38) comprising InP (column 7, lines 19-21), wherein the buffer layer (40) is either undoped or doped a same type as the substrate layer (38) (column 7, lines 19-21);
an absorption layer (42) disposed over the buffer layer (40) and comprising indium gallium arsenide (InGaAs) (38) (column 7, lines 19-21), wherein the absorption layer (42) is undoped or mildly doped the same type as the buffer layer (40, column 7, lines 23-25);
a plurality of transition layers (44, split into a plurality of InGaAsP layers) disposed over the absorption layer (42), the plurality of transition layers (44) comprising quaternary indium gallium arsenide phosphide (InGaAsP) (col. 7, lines 25-27)…;
a charge control layer (46A, column 7, lines 29-32 ) [disposed over the last transition layer and] comprising doped InP, wherein the charge control layer (46A) is doped the same type as the substrate layer (38);
a charge layer (lower portion of 46B) disposed over the charge control layer (46A) and comprising InP (column 7, lines 64-67, note there is a typo: the first “46A” that appears in the cited sentence should read “46B”), wherein the charge layer (46B) is undoped or lightly doped the same type as the substrate layer (38);
a cap layer (upper portion of 46B within the inner ring 54) disposed over the charge layer (lower portion of 46B) and comprising InP (column 7, lines 64-67), wherein the cap layer is undoped or mildly doped the same type as the substrate layer (38);
a monolithic detector active area (portion of 50 within layer 46B, i.e. 50 minus the portion within layer 48, shown in Figure 2, thus comprises one, continuous piece of material and is monolithic) disposed within the charge layer (lower portion of 46B) and the cap layer (upper portion of 46B within the inner ring 54), the detector active area (portion of 50 within layer 46B) comprising a strongly-doped material (column 7, lines 51-54), wherein the detector active area [comprises silicon and] is doped an opposite type as the substrate layer (38), the detector active area extending through the cap layer (upper portion of 46B within the inner ring 54) and into the charge layer (lower portion of 46B) to a depth thereby defining a multiplication region (portion of 48 between upper surface of 46A and lower surface of active area 50) of the charge layer (lower portion of 46B) between the detector active area (50) and the charge control layer (46A), wherein the detector active area (50) includes a shape that does not have any sharp edges within the charge layer (lower portion of 46B) and the cap layer (upper portion of 46B within the inner ring 54, the detector active area, portion of 50 within layer 46B, does not have any sharp edges at the border between the detector active area and the charge layer and the cap layer, see Figure 2, rather the layers are separated by a smooth, curved line denoted by the dashed line in Figure 2) to prevent electric field concentration (column 10, lines 11-15);
an anode (52, column 7, lines 33-35) disposed over the detector active area (50, shown in Figure 2); and
a cathode (32, column 7, lines 16-19) having an optical opening (see Figure 2), the cathode (32) disposed over the substrate layer (38) on an opposite side thereof as the buffer layer (40),
wherein the portion of the cap layer (upper portion of 46B within the inner ring 54) other than the detector active area (portion of 50 within layer 46B) is monolithic (see Figure 2, which shows the cap layer, which is the upper portion of 46B within the inner ring 54, is a one piece, continuous material, thus is monolithic).
Forrest does not explicitly disclose a plurality of transition layers … transitioning from a first transition layer in contact with the absorption layer having a higher concentration of gallium arsenide (GaAs) to a last transition layer having a higher concentration of phosphorus (P).
Sim discloses, however, a plurality of transition layers (9, para. [0043]) … transitioning from a first transition layer (lowest portion of 9) in contact with the absorption layer (7, para. [0043]) having a higher concentration of gallium arsenide (GaAs) to a last transition layer (uppermost portion of 9) having a higher concentration of phosphorus (P) (because Sim discloses layer 9 as a “grading” layer and discloses that the grading layer 9 is a multi-layer serves to smooth the bandgap difference between the InGaAs light absorption layer 7 and the InP electric field control layer 11 due to various bandgaps in the stacked structure disclosed, one having ordinary skill in the art would recognize that the grading layer 9 has different concentrations of P and GaAs from one side to the other, the side of the grading layer 9 in contact with the InGaAs light absorption layer 7 would have a higher concentration of GaAs in order to match the bandgap at the interface between the light absorption layer and the grading layer 9, and the side of the grading layer 9 in contact with the InP electric field control layer 11 would have a higher concentration of P in order to match the bandgap at the interface between the electric field control layer 11 and the grading layer 9).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Sim into the teachings of Forrest to include a plurality of transition layers … transitioning from a first transition layer in contact with the absorption layer having a higher concentration of gallium arsenide (GaAs) to a last transition layer having a higher concentration of phosphorus (P) for the purpose of filling a bandgap difference between the light absorption layer and the field control layer (Sim, para. [0043]).
Further, Chacinski discloses (para. [0035], [0037]) that a grading layer between two layers having different bandgaps (AlGaAs and GaAs) has a grading concentration of, in this case, aluminum (which could easily be applied to GaAs and P in Forrest and Sim), being essentially zero on the side of the grading layer in contact with the GaAs layer and gradually increasing until reaching the concentration of aluminum on the AlGaAs layer. Thus, it is apparent and obvious that in the art, “grading layer” implies that the purpose of the layer is to gradually change the concentrations of the elements therein to smooth the lattice transition from one layer to another adjacent layer in a photosensitive device. Additionally, Chacinski discloses that the grading layer increases transport velocity of hole carriers in the photodetector (Chacisnki, para. [0035]).
Forrest does not disclose wherein the detector active area comprises silicon.
Forrest does not disclose wherein the detector active area comprises silicon, rather only that it is a strongly doped p-type area of an InP material layer, see Figure 2.
Pan discloses, however, that a p-type III-V compound semiconductor material (such as InP) typically includes an acceptor dopant of Group IV, such as silicon (see para. [0040]).
Thus, it would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Pan into the teachings of Forrest to include a silicon acceptor donor of an InP compound semiconductor layer, such as the InP layer of which the detector active area of Forrest is comprised, since silicon may be used to dope the InP in order to form a p+ type region of a material, as evidenced by Pan (see para. [0040]), thereby arriving at the limitation requiring the detector active area to comprise silicon. Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Forrest does not disclose that the charge control layer includes a thickness and carrier concentration configured to achieve a low break down voltage.
However, Yang discloses on pages 3 and 7 (of the provided machine translation) an n-doped charge control layer (13) that includes a thickness of 400nm. Additionally, Sun discloses an n-type InP field control layer 40 with a charge density of 2.4E12/cm2 to 4.8E12/cm2 (see para. [0034]).
Although Yang and Sun do not explicitly disclose a low break down voltage, Applicant has disclosed that a thickness of the charge control layer that varies from 50nm-1500nm (see page 12), that the carrier concentration of the charge control layer can be optimized to keep the total charge density 2-4E12/cm-2, and ultimately that these characteristics of the charge control layer tune the break down voltage to about 40 volts, which would also be apparent to a person having ordinary skill in the art. Yang discloses an n-type InP charge control layer with a thickness of 400nm, and Sun discloses an n-type InP field control layer 40 with a charge density of 2.4E12/cm2 to 4.8E12/cm2. Thus the combination of the thickness and charge density (which determine the carrier concentration) characteristics of the charge control layers of Yang and Sun would result in a device with a charge control layer having a thickness and carrier concentration that achieves a low break down voltage (within 2% of 40 volts) given the characteristics of the layers.
Further, Yang discloses that those skilled in the art, according to the actual device needs, the thickness and doping concentration of corresponding design may be adjusted (see page 5 of the provided machine translation of Yang). Tuning the carrier concentration, charge density, and thicknesses of layers in a photodiode is a known method in the art which yields the predictable result of achieving a desired break down voltage. As such, it would have been obvious to one having ordinary skill in the art to adjust thicknesses, carrier concentrations, and charge densities of layers in the device, specifically here the charge control layer, in order to achieve the predictable result of desired low break down voltage (within 2% of 40 volts) or other desired characteristics. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 2, Forrest further discloses a cathode dielectric (34, column 7, lines 16-19) disposed in the optical opening (shown in Figure 2), and
the combination of teachings above teaches wherein the low breakdown voltage is within 2% of 40 volts (see above with regards to the low breakdown voltage of claim 1).
Regarding claim 3, Forrest further discloses an anode dielectric (62, column 8, lines 15-17) disposed between the anode (52) and the cap layer (upper portion of 46B within the inner ring 54, shown in Figure 2).
Regarding claim 4, Forrest discloses wherein the anode dielectric (62) extends over a portion of the detector active area (portion of 50 within layer 46B, shown in Figure 2).
Regarding claim 6, Forrest does not disclose wherein the detector active area (portion of 50 within layer 46B) has a semi ellipsoidal shape.
Sim discloses, however, the photodiode structure of claim 6, wherein the detector active area (31, para. [0045], Figure 2A) has semi ellipsoidal shape (“circular shape in plan view”, para. [0045]).
It would have been obvious to one of ordinary skill in the art to incorporate the teachings of Sim into the teachings of Forrest to include wherein the detector active area has a semi ellipsoidal shape for the purpose of preventing edge breakdown and mitigate electric field concentration (Sim, para. [0045]).
Regarding claim 7, Forrest does not disclose wherein the detector active area (portion of 50 within layer 46B) has a hemispherical shape.
Sim discloses, however, the photodiode structure of claim 6, wherein the detector active area (31, para. [0045], Figure 2A) has a hemispherical shape (“circular shape in plan view”, para. [0045]).
It would have been obvious to one of ordinary skill in the art to incorporate the teachings of Sim into the teachings of Forrest to include wherein the detector active area has a hemispherical shape for the purpose of preventing edge breakdown and mitigate electric field concentration (Sim, para. [0045]).
Regarding claim 8, Forrest discloses wherein the photodiode structure (Figure 2) forms an avalanche photodiode (col. 5, lines 37-38).
Forrest does not explicitly disclose a carrier concentration or the charge density of the charge control layer, but discloses a thickness between 0.12 and 0.13 microns (see claim 23 below).
However, Sun discloses an n-type InP charge control layer (40) with a thickness of 150nm to 300nm and a charge density between 2-5E12cm-2 (see para. [0034]). Applicant has disclosed that the charge control layer of the present invention can have a thickness between 50nm and 1500nm (see page 12) to achieve a charge density of 2-4E12/cm2.
Thus, it would have been obvious to one having ordinary skill in the art to include the thickness of the charge control layer of Sun into the teachings of Forrest in order to achieve the predictable result of the claimed charge density of the charge control layer, as well as to regulate electric field distribution and prevent edge breakdown (Sun, para. [0034]).
Regarding claim 9, Forrest discloses an avalanche photodetector comprising:
a plurality of pixels (Figure 2), each pixel comprising a photodiode structure as recited in claim 1 (Figure 2).
It is the position of the Office that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, which Applicant has not disclosed. Further, one having ordinary skill in the art would recognize that merely forming a plurality of the same pixel to create an array of photodetectors/photodiodes is a very common practice in the art.
Regarding claim 10, Forrest discloses wherein the avalanche photodetector is configured to sense at least one wavelength between about 400 nm and about 2600 nm (col. 2, lines 9-11).
Regarding claim 11, Forrest discloses the avalanche photodetector (Figure 2) of claim 9, wherein the photodiode structure of each pixel further comprises a cathode dielectric (34, column 7, lines 16-19) disposed in the optical opening (see Figure 2).
Regarding claim 12, Forrest discloses the avalanche photodetector (Figure 2) of claim 11, wherein the photodiode structure of each pixel further comprises an anode dielectric (62, column 8, lines 15-17) disposed between the anode (52) and the cap layer (upper portion of 46B within the inner ring 54) (shown in Figure 2).
Regarding claim 13, Forrest discloses the avalanche photodetector (Figure 2) of claim 12, wherein the anode dielectric (62, column 8, lines 15-17) extends over a portion of the detector active area (portion of 50 within layer 46B, shown in Figure 2).
Regarding claim 15, Forrest does not disclose wherein the detector active area (portion of 50 within layer 46B) has a semi ellipsoidal shape.
Sim discloses, however, the photodiode structure of claim 6, wherein the detector active area (31, para. [0045], Figure 2A) has semi ellipsoidal shape (“circular shape in plan view”, para. [0045]).
It would have been obvious to one of ordinary skill in the art to incorporate the teachings of Sim into the teachings of Forrest to include wherein the detector active area has a semi ellipsoidal shape for the purpose of preventing edge breakdown and mitigate electric field concentration (Sim, para. [0045]).
Regarding claim 16, Sim discloses wherein the detector active area (31, para. [0045], Figure 2A) of each pixel has a hemispherical shape (“circular shape in plan view”, para. [0045]).
It would have been obvious to one of ordinary skill in the art to incorporate the teachings of Sim into the teachings of Forrest to include wherein the detector active area has a hemispherical shape for the purpose of preventing edge breakdown and mitigate electric field concentration (Sim, para. [0045]).
Regarding claim 17, Forrest discloses wherein the photodiode structure of each pixel (Figure 2) forms an avalanche photodiode (col. 5, lines 37-38).
Regarding claim 22, Forrest discloses wherein the avalanche photodetector is configured to sense at least one wavelength between about 1000 nm and about 1700 nm (col. 2, lines 9-11).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Forrest, Sim, Chacinski, Yang, Sun, and Pan as applied to claim 1 above, and further in view of Davis et al. (“Davis” US Patent No. 5,343,055).
Regarding claim 23, Forrest discloses wherein the multiplication region (lower portion of 48 between detector area 50 and 46A) has a thickness between the detector active area (50) and the charge control layer (46A) of about 0.12 microns to about 0.13 microns (col. 7, lines 35-41 discloses the “slab” 48 is embedded at an underside of detector area 50 and has a thickness in the range of 1000-5000 Angstroms, which equates to 0.1-0.5 microns, the multiplication region constitutes about the lower half portion of the slab 48, thus the prior art thickness range overlaps with the claimed range).
Note that the range disclosed by Forrest overlaps the claimed range. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the thickness of the multiplication region to be a result effective variable affecting the “field for avalanche multiplication near the p-n junction” (see Davis, col. 1, lines 19-30). Thus, it would have been obvious to modify the device of Forrest to have the thickness of the multiplication region within the claimed range in order to tune the field near the p-n junction, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Linga (US Patent No. 8,441,032) and Pan et al. (“Pan” US 2009/0121305).
Regarding claim 18, Linga discloses an avalanche photodiode structure (10, Figure 1) comprising:
a substrate layer (12) comprising strongly-doped indium phosphide (InP);
a charge layer (lower portion of 22, defined by a horizontal line bisecting the regions 33, Figure 1, column 7, lines 37-46, see also annotated Figure 1 of Linge below) comprised of undoped InP (column 7, line 42);
a cap layer (upper portion of 22, defined by a horizontal line bisecting the regions 33, see annotated Figure 1 below) disposed over the charge layer (lower portion of 22, see Figure 2, and annotated Figure 1 below)
a monolithic detector active area (leftmost region 33, Figure 1, column 7, line 44, comprises a single, continuous region of material, thus is monolithic) disposed within the charge layer (lower portion of 22, see annotated Figure 1 below) and the cap layer (upper portion of 22, see annotated Figure 1 below) forming a junction with the charge layer (lower portion of 22, column 8, lines 58-59) and having edges configured to prevent edge breakdown (curved edges of 33 are shown in Figure 1), and wherein a location of the junction is controlled through a doped region (column 8, lines 56-59); and
a charge control layer (20, column 7, lines 37-46) comprising doped InP (column 7, line 42), wherein the charge control layer (20) includes a thickness and carrier concentration configured to achieve a predetermined gain (see Figure 4 which shows the gain of the device, which is directly related to the photocurrent), and break down voltage (column 8, lines 34-40) of within 2% of 40 volts (col. 10, lines 28-37, the thickness of the charge control layer 20 of Linga is disclosed as being one micron thick, or 1000nm, which is within the disclosed range of the charge control layer thickness that achieve a break down voltage of within 2% of 40 volts, which is 50nm-1500nm, see page 12 of the instant specification),
wherein the portion of the cap layer (upper portion of 22) other than the detector active area (leftmost 33) is monolithic (see annotated Figure 1 below, since the cap layer portion other than the detector active area portion comprises one, continuous material it is considered monolithic).
Linga does not disclose wherein the detector active area comprises silicon, rather only that it is a strongly doped p-type area of an InP material layer.
Pan discloses, however, that a p-type III-V compound semiconductor material (such as InP) typically includes an acceptor dopant of Group IV, such as silicon (see para. [0040]).
Thus, it would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Pan into the teachings of Linga to include a silicon acceptor donor of an InP compound semiconductor layer, such as the InP layer of which the detector active area of Linga is comprised, since silicon may be used to dope the InP in order to form a p+ type region of a material, as evidenced by Pan (see para. [0040]), thereby arriving at the limitation requiring the detector active area to comprise silicon. Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
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Response to Arguments
Applicant' s arguments with respect to claims 1 and 18 have been considered but are moot because the new ground of rejection does not rely on interpretation of the references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The Examiner notes, regarding Applicant’s statement that Linga does not disclose a separate cap layer disposed over the multiplication layer (mapped to the claimed charge layer), that claim 18 does not explicitly require the cap layer to be a separate structure from the charge layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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