MULTIPLIER

Application No. 17/698,068

• Filed: Mar 18, 2022
• Examiner: VILLANUEVA, MARKUS ANTHONY
• Art Unit: 2151
• Tech Center: 2100 — Computer Architecture & Software
• Assignee: Huawei Technologies Co., Ltd.
• OA Round: 2 (Final)

Office Action

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Response to Amendment
The amendment filed 05 December 2025 has been entered. Applicant’s amendments to the specification have overcome the abstract, specification, and drawings objections, and amendments to the claims have overcome the 35 USC 112(b) rejections previously set forth in the Non-Final Office Action mailed 08 September 2025.

Specification
The disclosure is objected to because of the following informalities: in [00112] the specification reads “a first mask 342 and a second mask 344”, however, this section appears to be directed to the mask circuit “540” in Fig. 9A which illustrates the first mask as “542” and the second mask as “544”.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: “unmasked” as recited in claim 1 - ln. 12, claim 13 – ln. 2, and claim 19 – ln. 15.
Appropriate correction is required.

Claim Construction
Regarding claim 1, the preamble is given patentable weight. Claim 5 contains the limitation “the multiplier” in the body, which is referring to the limitations as recited in the preamble of claim 1. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of the multiplier comprising the multiplicator input end, mask circuit, multiplicand input end, and multiplication operation circuit. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight.

Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.

The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.

Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent claims 1, 13, and 19 recite the limitation “the first multiplicand and the second multiplicand are unmasked”. The specification appears to disclose the first multiplicand and second multiplicand in [0078, 0080], but does not include a description of the first multiplicand and second multiplicand as “unmasked”. See MPEP 2173.05(i) Negative Limitations.
Claims 2-12 inherit the same deficiency by reasons of dependence on claim 1. Claims 14-18 inherit the same deficiency by reasons of dependence on claim 13. Claim 20 inherits the same deficiency by reasons of dependence to claim 19.

Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.

Claims 1-9, 11-20 are rejected under 35 U.S.C. 101 because the claimed invention
is directed to a judicial exception (i.e., an abstract idea) without significantly more.

Regarding claim 1, under the Alice Framework Step 1 analysis, the claim falls
within the four statutory categories of patentable subject matter: an apparatus.
Under the Alice Framework Step 2A Prong 1 analysis, the claim recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
wherein the multiplicator data comprises a first multiplicator and a second multiplicator, and a sum of a bit width of the first multiplicator and a bit width of the second multiplicator is less than a bit width of the multiplicator input end;
mask the second multiplicator in the multiplicator data to obtain a first mask result, and mask the first multiplicator in the multiplicator data to obtain a second mask result;
wherein a sum of a bit width of the first multiplicand and a bit width of the second multiplicand is less than a bit width of the multiplicand input end, and the first multiplicand and the second multiplicand are unmasked; and
perform a multiplication operation on the first mask result and the first multiplicand to obtain a result of multiplying the first multiplicator and the first multiplicand, and perform a multiplication operation on the second mask result and the second multiplicand to obtain a result of multiplying the second multiplicator and the second multiplicand.

See specification describing the multiplicator data ([0077], [0086]). See specification describing masking ([0079], [00112]). See specification describing the sum ([0077-0078]). See specification describing the multiplication operation ([0080-0082]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a multiplicator input end configured to receive multiplicator data, a mask circuit, a multiplicand input end configured to receive a first multiplicand and a second multiplicand, a multiplication operation circuit, a multiplier, and output the result of multiplying the first multiplicator and the first multiplicand and output the result of multiplying the second multiplicator and the second multiplicand. A multiplicator input end, mask circuit, a multiplicand input end, a multiplication operation circuit, and a multiplier are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The receiving and outputting limitations are examples of insignificant extra-solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. The receiving and outputting limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (for receiving: See MPEP 2106.05(d)(II)(iv): Storing and retrieving information in memory; for outputting: See MPEP 2106.05(d)(II)(i): Receiving or transmitting data over a network). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 1 is ineligible.

Under the Alice Framework Step 2A Prong 2 analysis, claim 2 recites the combination of the following additional elements: the multiplication operation circuit comprises a Booth encoder. The multiplication operation circuit comprising a Booth encoder is recited at a high level of generality, and is an example of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 2 is ineligible.

Under the Alice Framework Step 2A Prong 1 analysis, claim 3 recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
perform a partial product calculation based on an encoding result generated by the Booth encoder;
accumulate a plurality of partial products generated by the partial product calculation circuit.

See specification describing the performing a partial product calculation ([0084], [00114]). See specification describing accumulating a plurality of partial products ([0085], [00115-00116]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a partial product calculation circuit and an accumulator. A partial product calculation circuit and an accumulator are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 3 is ineligible.

Under the Alice Framework Step 2A Prong 1 analysis, claim 4 recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
perform Booth encoding on the first multiplicand to obtain at least one first encoding result, and perform Booth encoding on the second multiplicand to obtain at least one second encoding result;
calculate at least one first partial product of the at least one first encoding result and the first mask result, and calculate at least one second partial product of the at least one second encoding result and the second mask result; and
perform accumulation on the at least one first partial product to obtain the result of multiplying the first multiplicator and the first multiplicand, and perform accumulation on the at least one second partial product to obtain the result of multiplying the second multiplicator and the second multiplicand.

See specification describing performing Booth encoding ([0071-0074], [0083], [0094-0099], [00113]). See specification describing the performing a partial product calculation ([0084], [00114]). See specification describing accumulating a plurality of partial products ([0085], [00115-00116]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the booth encoder comprises a plurality of sub-encoders, a partial product calculation circuit, and an accumulator. The booth encoder comprises a plurality of sub-encoders, a partial product calculation circuit, and an accumulator are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 4 is ineligible.

Under the Alice Framework Step 2A Prong 1 analysis, claim 5 recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
add the result of multiplying the first multiplicator and the first multiplicand and the result of multiplying the second multiplicator and the second multiplicand; and
use a result of adding the result of multiplying the first multiplicator and the first multiplicand and the result of multiplying the second multiplicator and the second multiplicand in a convolutional neural network process.

See specification describing performing the adding ([0070], [00107], [00116-00117]). See specification describing using in a convolutional neural network process ([0011], [0028], [0070]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: an adder. The adder is recited at a high level of generality, and is an example of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 5 is ineligible.

Under the Alice Framework Step 2A Prong 1 analysis, claim 6 recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
shift the result of multiplying the first multiplicator and the first multiplicand and the result of multiplying the second multiplicator and the second multiplicand.

See specification describing performing the shift ([00119-00120]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a shifter. The shifter is recited at a high level of generality, and is an example of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 6 is ineligible.

Under the Alice Framework Step 2A Prong 1 analysis, claim 7 recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
data comprises the first multiplicand located at a less significant bit of, the second multiplicand located at a more significant bit, one extended bit of 0 inserted at an end of a least significant bit of the first multiplicand, and another bit set to 0 other than the first multiplicand, the second multiplicand, and the extended bit in the multiplicand input end; and
the multiplicator data comprises: the first multiplicator located at the less significant bit, the second multiplicator located at the more significant bit, and another bit set to 0 other than the first multiplicator and the second multiplicator, wherein a position of the first multiplicator is the same as a position of the first multiplicand, and a position of the second multiplicator is the same as a position of the second multiplicand.

See specification describing multiplicand extension by 0 ([0071], [0073], [0090-0091]). See specification describing the multiplicator data ([0079], [00111-00112]).For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the multiplicand input end and the multiplicator input end. The multiplicand input end and the multiplicator input end are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 7 is ineligible.

Under the Alice Framework Step 2A Prong 1 analysis, claim 8 recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
the first multiplicand and the second multiplicand are separated by at least one bit of 0, the first multiplicator and the second multiplicator are separated by at least one bit of 0;
output data of a most significant bit of the first multiplicand to a most significant bit of, and output data 0 to a least significant bit and that encodes an idle bit, wherein the idle bit is a bit set to 0 between the first multiplicand and the second multiplicand.

See specification describing separating ([0071], [0083], [0093]). See specification describing the output data ([0047], [00107], [00119]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a selector, first sub-encoder, and a sub-encoder that is adjacent to the first sub-encoder. The selector, first sub-encoder, and a sub-encoder that is adjacent to the first sub-encoder are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 8 is ineligible.

Under the Alice Framework Step 2A Prong 1 analysis, claim 9 recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
wherein a most significant bit of the first multiplicand is adjacent to a least significant bit of the second multiplicand, a most significant bit of the first multiplicator is adjacent to a least significant bit of the second multiplicator;
output data of the most significant bit of the first multiplicand to a most significant bit, and output data 0 to a least significant bit, and that encodes the second multiplicand.

See specification describing adjacency ([00118], [00134-00135]). See specification describing the output data ([0047], [00107], [00119]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: a selector, first sub-encoder, and a second sub-encoder wherein the second sub-encoder is a sub-encoder that is adjacent to the first sub-encoder. The selector, first sub-encoder, and a second sub-encoder wherein the second sub-encoder is a sub-encoder that is adjacent to the first sub-encoder are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 9 is ineligible.

Under the Alice Framework Step 2A Prong 2 analysis, claim 11 recites the combination of the following additional elements: a switch, wherein the switch is configured to: when in an on state, activate the mask circuit; and when in an off state, disable the mask circuit. The switch is recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). The activating and disabling limitations are examples of insignificant extra-solution activity. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. The activating and disabling limitations described above as an insignificant extra-solution activity are also well-understood, routine, or conventional (See Horowitz, P., & Hill, W. (2015). The art of electronics (3rd ed.). Cambridge University Press. (hereinafter “Horowitz”), Pg. 184, Col. 2, Sec. 3.4.4, Para. 1, turning or off power). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 11 is ineligible.

Under the Alice Framework Step 2A Prong 1 analysis, claim 12 recites
Mathematical Concepts. The claim recites Mathematical Calculations, which is
specifically identified as an exemplar in the Mathematical Concepts grouping of abstract
ideas:
mask the first multiplicator and mask the second multiplicator to output the second and first mask results.

See specification describing masking ([0079-0080], [0088]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the mask circuit comprises two AND gates. The mask circuit comprises two AND gates are recited at a high level of generality, and are examples of generic computing elements, and/or merely generally linked to a particular technological environment (see MPEP 2106.05(h)(vi): Limiting the abstract idea of collecting information, analyzing it, and displaying certain results of the collection analysis to data related to the electric power grid, because limiting application of the abstract idea to power-grid monitoring is simply an attempt to limit the use of the abstract idea to a particular technological environment). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B Analysis, the additional elements recited above, taken alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 Analysis, the claim recites additional elements which are examples of generic computing elements that result in “apply it” on a computer. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 12 is ineligible.

Claims 13-18 are directed to a method that would be practiced by the device of claims 1-6. The claims 13-18 analysis similarly applies to claims 1-6, and claims 13-18 are equally rejected.

Claims 19-20 are directed to a system that recites similar limitations to the device of claims 1, 3, respectively. The claims 1, 3 analysis similarly applies to claims 19-20, and claims 19-20 are equally rejected.

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

Claims 1-4, 6-10, 12-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over A. Danysh and D. Tan, "Architecture and implementation of a vector/SIMD multiply-accumulate unit," in IEEE Transactions on Computers, vol. 54, no. 3, pp. 284-293, March 2005, doi: 10.1109/TC.2005.41. (hereinafter “Danysh”) in view of US 20090248779 A1 Brooks et al. (hereinafter “Brooks”).

Regarding claim 1, Danysh teaches a multiplier comprising:
a multiplicator input end (Fig. 9 right-hand-side, arrow into Multiplier “* Vector Masking (zero insert) * Vector Sign Extension”; Fig. 1, section where multiplier (B) is input), configured to receive (Pg. 285, Col. 2, Sec. 2.2, Para. 1, inputting multiplier (B) operand) multiplicator data (Fig. 9, Multiplier B[63:0]; Fig. 1, multiplier (B)), wherein the multiplicator data comprises a first multiplicator (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) and a second multiplicator (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed), and a sum of a bit width of the first multiplicator and a bit width of the second multiplicator (Fig. 10, B[7:0] vector 0 plus B[15:8] vector 1 in 8-bit mode equals 16 bits for the bit width; Fig. 10, B[15:0] vector 0 plus B[31:16] vector 1 in 16-bit mode equals 32 bits for the bit width;) is less than a bit width of the multiplicator input end (Fig. 9, 64 bit data as represented by operand B[63:0], arrow into Multiplier “* Vector Masking (zero insert) * Vector Sign Extension”; Pg. 284, Col. 1, Sec. 1, Para. 1);
a mask circuit (Fig. 9 right-hand-side, Multiplier “* Vector Masking (zero insert) * Vector Sign Extension” box), configured to mask (Pg. 285, Col. 2, Sec. 2.2, Para. 1; Pg. 286, Col. 1, Para. 2; Pg. 287, Col. 2, Para. 1) the second multiplicator in the multiplicator data to obtain a first mask result (Fig. 10, B[15:8] and “0” in vector 1 in 8-bit mode and B[31:16] and “0” in vector 1 in 16-bit mode as an example before the sign extensions operations are performed), and mask the first multiplicator in the multiplicator data to obtain a second mask result (Fig. 10, B[7:0] and “0” in vector 0 in 8-bit mode and B[15:0] and “0” in vector 0 in 16-bit mode as an example before the sign extensions operations are performed);
a multiplicand input end (Fig. 9 left-hand-side, arrow into Multiplicand “* Vector Masking and Muxing * Vector Sign Extension * Vector Sign Encoding * Vector Twos Complement Increment”; Fig. 1, section where multiplicand (A) is input), configured to receive (Pg. 285, Col. 2, Sec. 2.2, Para. 1, inputting multiplicand (A) operand) a first multiplicand and a second multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)), wherein a sum of a bit width of the first multiplicand and a bit width of the second multiplicand is less than a bit width of the multiplicand input end (Fig. 9, 64 bit data as represented by operand A; Pg. 284, Col. 1, Sec. 1, Para. 1); and
a multiplication operation circuit (Fig. 9, Radix-4 Booth Recoder, Booth Muxes, Partial Products stage, and vector final carry propagate adder (CPA) (not pictured in Fig. 9, illustrated in Fig. 1) described in Pg. 289, Col. 1-2, Sec. 2.4), configured to perform a multiplication operation (Fig. 9, Booth Muxes, Pg. 286, Col. 2, Sec. 2.2.2, Para 1-3) on the first mask result (Fig. 9, output from Radix-4 Booth Recoder; Fig. 10, B[15:8] and “0” in vector 1 in 8-bit mode and B[31:16] and “0” in vector 1 in 16-bit mode as an example before the sign extensions operations are performed) and the first multiplicand (Fig. 9, “vectorized” multiplicand output) to obtain a result of multiplying the first multiplicator and the first multiplicand (Fig. 8, pp0-pp3, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2), and perform a multiplication operation (Fig. 9, Booth Muxes, Pg. 286, Col. 2, Sec. 2.2.2, Para 1-3) on the second mask result (Fig. 9, output from Radix-4 Booth Recoder; Fig. 10, B[7:0] and “0” in vector 0 in 8-bit mode and B[15:0] and “0” in vector 0 in 16-bit mode as an example before the sign extensions operations are performed) and the second multiplicand (Fig. 9, “vectorized” multiplicand output) to obtain a result of multiplying the second multiplicator and the second multiplicand (Fig. 8, pp4-pp7, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2), and output (output from Partial Products stage [Fig. 9] and vector final carry propagate adder (CPA) (not pictured in Fig. 9, illustrated in Fig. 1) described in Pg. 289, Col. 1-2, Sec. 2.4, to “result (R)” in Fig. 1; Pg. 287, Col. 2, Para. 2; Fig. 18, R, Pg. 289, Col. 2, Para. 1) the result of multiplying the first multiplicator and the first multiplicand (Fig. 8, pp0-pp3, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2) and output (output from Partial Products stage [Fig. 9] and vector final carry propagate adder (CPA) (not pictured in Fig. 9, illustrated in Fig. 1) described in Pg. 289, Col. 1-2, Sec. 2.4, to “result (R)” in Fig. 1; Pg. 287, Col. 2, Para. 2; Fig. 18, R, Pg. 289, Col. 2, Para. 1) the result of multiplying the second multiplicator and the second multiplicand (Fig. 8, pp4-pp7, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2).
Although Danysh teaches the multiplicand (A) generally, it appears they are silent with expressing the specific portioning of bits based on the various vector modes as was taught with such great detail with respect to the multiplier (B) (Fig. 10).
However, it would have been obvious to modify by one of ordinary skill in the art before the effective filing date given the finite number of ways to partition the multiplicand (A) data for calculations. In practicality, there are only a finite number of reasonable ways to partition 64 bits of data, so it would have been obvious to try splitting multiplicand (A) data similarly to how multiplier (B) data was partitioned (Fig. 10, 8-bit increments for vectors 0-7 in 8-bit mode, 16-bit increments for vectors 0-3 in 16-bit mode, 32-bit increments for vectors 0-2 in 32-bit mode), where the first multiplicand is (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed), the second multiplicand is (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed), and the sum of the bit width of the first and the second (Fig. 10, B[7:0] vector 0 plus B[15:8] vector 1 in 8-bit mode equals 16 bits for the bit width; Fig. 10, B[15:0] vector 0 plus B[31:16] vector 1 in 16-bit mode equals 32 bits for the bit width) is less than the multiplicand input end (Fig. 9, 64 bit data as represented by operand B; Pg. 284, Col. 1, Sec. 1, Para. 1). Danysh’s vector MAC architecture utilizes the “shared subtree” or the “shared segmentation” method for computations. Implementing these methods assists with data alignment where the shared segmentation segments based on the size of the smallest element or subword (Pg. 284, Col. 1, Sec. 1, Para. 1), and the shared subtree arranges partial products to overlap (Pg. 285, Col. 1, Para. 2). It would have been obvious to one of ordinary skill in the art to implement multiplicand (A) with the same partitioning as multiplier (B) for alignment purposes when generating partial products correctly, and further to achieve the benefits of utilizing the specific shared methods (Pg. 292, Sec. 5, Para. 2).
Danysh is silent with disclosing the first multiplicand and the second multiplicand are unmasked.
Brooks discloses the first multiplicand and the second multiplicand are unmasked (Fig. 3A ‘Unmasked’ [0059], [0063-0064], [0067]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Danysh’s multiplier with Brooks’ unmasked feature because they are in the claimed invention’s same field of endeavor of multiplier architecture ([abstract]). It would have been obvious to one of ordinary skill in the art to implement the unmasked feature, as doing assists with determining proper positioning and alignment of operands for later operations ([0063-0064]), ensuring accuracy and correctness of the calculations. In practicality, there are only a finite number of reasonable states the multiplicators and multiplicands are capable of being in: masked or unmasked. Thus, making this modification would have been obvious to try, yielded predictable results, and been beneficial as Danysh’s multiplier now has support for unmasking operand values that can assist with proper alignment of operands for later calculations.

Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Danysh teaches wherein the multiplication operation circuit (see claim 1 mapping) comprises:
a Booth encoder (Fig. 9, Radix-4 Booth Recoder, Pg. 285, Sec. 2.2.1, bridging to Pg. 286, Col. 1-2).

Regarding claim 3, in addition to the teachings addressed in the claim 2 analysis, the rejection of claim 2 is incorporated and Danysh teaches wherein the multiplication operation circuit (see claim 1 mapping) further comprises:
a partial product calculation circuit (Fig. 9, Booth Muxes), configured to perform a partial product calculation (Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2) based on an encoding result generated by the Booth encoder (Fig. 9, Radix-4 Booth Recoder output (buffered), Pg. 285, Sec. 2.1.1, Col. 1, Para. 1, bridging to Pg. 286, Col. 1, Para. 1-3); and
an accumulator (Fig. 1, Final Carry-Propagate Adder (CPA), Pg. 289, Col. 1-2, Sec. 2.4, Vector Final Carry Propagate Adder (CPA)), configured to accumulate (Pg. 292, Col. 1, Para. 1, the remaining partial products) a plurality of partial products generated by the partial product calculation circuit (Fig. 1, output from PPRT; Fig. 8, pp0-pp31, Fig. 16, final PPs).

Regarding claim 4, in addition to the teachings addressed in the claim 3 analysis, the rejection of claim 3 is incorporated and Danysh teaches wherein:
the Booth encoder (see claim 2 mapping) comprises a plurality of sub-encoders (Fig. 14 and Fig. 15, logical gates (NOT gates followed by NAND gates)), configured to perform Booth encoding on the first multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)) to obtain at least one first encoding result (Fig. 14 and Fig. 15, outputs from Booth Recoder; Fig. 9, Radix-4 Booth Recoder output (buffered), Pg. 285, Sec. 2.1.1, Col. 1, Para. 1, bridging to Pg. 286, Col. 1, Para. 1-3), and perform Booth encoding on the second multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)) to obtain at least one second encoding result (Fig. 14 and Fig. 15, outputs from Booth Recoder; Fig. 9, Radix-4 Booth Recoder output (buffered), Pg. 285, Sec. 2.1.1, Col. 1, Para. 1, bridging to Pg. 286, Col. 1, Para. 1-3);
the partial product calculation circuit (see claim 3 mapping) is further configured to calculate at least one first partial product (Fig. 16, Final PPs derived from the output from Booth Muxes in Fig. 9; Fig. 8, pp0-pp31, Fig. 16, pp0-p15…) of the at least one first encoding result and the first mask result (Fig. 9, output from Radix-4 Booth Recoder which were masked previously; Fig. 10, B[15:8] and “0” in vector 1 in 8-bit mode and B[31:16] and “0” in vector 1 in 16-bit mode as an example before the sign extensions operations are performed), and calculate at least one second partial product (Fig. 16, Final PPs derived from the output from Booth Muxes in Fig. 9; Fig. 8, pp0-pp31, Fig. 16, pp0-p15…) of the at least one second encoding result and the second mask result (Fig. 9, output from Radix-4 Booth Recoder which were masked previously; Fig. 10, B[15:8] and “0” in vector 1 in 8-bit mode and B[31:16] and “0” in vector 1 in 16-bit mode as an example before the sign extensions operations are performed); and
the accumulator (see claim 3 mapping) is further configured to perform accumulation (Pg. 292, Col. 1, Para. 1, the remaining partial products) on the at least one first partial product (Fig. 16, Final PPs derived from the output from Booth Muxes in Fig. 9; Fig. 8, pp0-pp31, Fig. 16, pp0-p15…) to obtain the result of multiplying the first multiplicator and the first multiplicand (Fig. 8, pp0-pp3, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2), and perform accumulation (Pg. 288, Sec. 2.3, Col. 2, Para. 1-2) on the at least one second partial product (Fig. 16, Final PPs derived from the output from Booth Muxes in Fig. 9; Fig. 8, pp0-pp31, Fig. 16, pp0-p15…) to obtain the result of multiplying the second multiplicator and the second multiplicand (Fig. 8, pp4-pp7, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2).
Although Danysh teaches the multiplicand (A) generally, it appears they are silent with expressing the specific portioning of bits (first and second multiplicand) based on the various vector modes as was taught with such great detail with respect to the multiplier (B) (Fig. 10).
However, it would have been obvious to modify by one of ordinary skill in the art before the effective filing date given the finite number of ways to partition the multiplicand (A) data for calculations. In practicality, there are only a finite number of reasonable ways to partition 64 bits of data, so it would have been obvious to try splitting multiplicand (A) data similarly to how multiplier (B) data was partitioned (Fig. 10, 8-bit increments for vectors 0-7 in 8-bit mode, 16-bit increments for vectors 0-3 in 16-bit mode, 32-bit increments for vectors 0-2 in 32-bit mode), where the first multiplicand is (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) and the second multiplicand is (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed). Danysh’s vector MAC architecture utilizes the “shared subtree” or the “shared segmentation” method for computations. Implementing these methods assists with data alignment where the shared segmentation segments based on the size of the smallest element or subword (Pg. 284, Col. 1, Sec. 1, Para. 1), and shared subtree arranges partial products to overlap (Pg. 285, Col. 1, Para. 2). It would have been obvious to one of ordinary skill in the art to implement multiplicand (A) with the same partitioning as multiplier (B) for alignment purposes when generating partial products correctly, and further to achieve the benefits of utilizing the specific shared methods (Pg. 292, Sec. 5, Para. 2).

Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Danysh teaches further comprising:
a shifter, and wherein the shifter is configured to:
shift the result of multiplying the first multiplicator and the first multiplicand (Fig. 8, pp0-pp3, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2) and the result of multiplying the second multiplicator and the second multiplicand (Fig. 8, pp4-pp7, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2).
Although Danysh teaches the multiplicand (A) generally, it appears they are silent with expressing the specific portioning of bits (first and second multiplicand) based on the various vector modes as was taught with such great detail with respect to the multiplier (B) (Fig. 10).
However, it would have been obvious to modify by one of ordinary skill in the art before the effective filing date given the finite number of ways to partition the multiplicand (A) data for calculations. In practicality, there are only a finite number of reasonable ways to partition 64 bits of data, so it would have been obvious to try splitting multiplicand (A) data similarly to how multiplier (B) data was partitioned (Fig. 10, 8-bit increments for vectors 0-7 in 8-bit mode, 16-bit increments for vectors 0-3 in 16-bit mode, 32-bit increments for vectors 0-2 in 32-bit mode), where the first multiplicand is (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed), the second multiplicand is (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed). Danysh’s vector MAC architecture utilizes the “shared subtree” or the “shared segmentation” method for computations. Implementing these methods assists with data alignment where the shared segmentation segments based on the size of the smallest element or subword (Pg. 284, Col. 1, Sec. 1, Para. 1), and shared subtree arranges partial products to overlap (Pg. 285, Col. 1, Para. 2). It would have been obvious to one of ordinary skill in the art to implement multiplicand (A) with the same partitioning as multiplier (B) for alignment purposes when generating partial products correctly, and further to achieve the benefits of utilizing the specific shared methods (Pg. 292, Sec. 5, Para. 2).
In an alternative embodiment, Danysh teaches a shifter (Fig. 20, shift), and wherein the shifter is configured to shift (Pg. 290, Sec. 3.1, Col. 1, Para. 1, bridging to Pg. 291, Col. 1, Para. 1; Pg. 291, Col. 1, Sec. 3.3).
It would have been obvious to modify with the alternative embodiment as the alternative embodiment describes using recursive or divide-and-conquer methods which involve building wider vector elements out of narrower ones, and then adding the results together (Pg. 290, Sec. 3.1, Para. 1). Making this modification would be beneficial, as by being able to implement the architecture by effectively “unrolling the loop” is extremely effective and useful when vector multiples are required utilizing a minimal amount of hardware (Pg. 290, Sec. 3.1, Para. 1). Thus, a person skilled in the art would recognize that modifying Danysh’s original architecture with the alternative embodiment would give the system more flexibility and result in having greater use in other applications.

Regarding claim 7, in addition to the teachings addressed in the claim 4 analysis, the rejection of claim 4 is incorporated and Danysh teaches wherein:
data in the multiplicand input end (Fig. 9, 64 bit data as represented by operand A; Pg. 284, Col. 1, Sec. 1, Para. 1) comprises the first multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)) located at a less significant bit of the multiplicand input end, the second multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)) located at a more significant bit of the multiplicand input end, one extended bit of 0 inserted at an end of a least significant bit of the first multiplicand, and another bit set to 0 other than the first multiplicand, the second multiplicand, and the extended bit in the multiplicand input end (Fig. 9 left-hand-side, arrow into Multiplicand “* Vector Masking and Muxing * Vector Sign Extension * Vector Sign Encoding * Vector Twos Complement Increment”; Fig. 1, section where multiplicand (A) is input);
and the multiplicator data (Fig. 9, Multiplier B[63:0]; Fig. 1, multiplier (B)) comprises:
the first multiplicator (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) located at the less significant bit of the multiplicator input end (Fig. 10, vector 0 containing the [7:0] bits in 8-bit mode, and [15:0] bits in 16-bit mode, where bit 0 is the LSB and 63 is the MSB), the second multiplicator (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) located at the more significant bit of the multiplicand input end (Fig. 10, vector 1 containing the [15:8] bits in 8-bit mode, and [31:16] bits in 16-bit mode, where bit 0 is the LSB and 63 is the MSB), and another bit set to 0 other than the first multiplicator and the second multiplicator in the multiplicator input end (Fig. 10, “0” inserted at right-hand-side of vectors in 8 and 16 bit mode, Pg. 286, Col. 1, Para. 2), wherein a position (Fig. 8, pp0-pp3; Fig. 6, vector0; Fig. 5, vector0; Fig. 3, vector0; Fig. 2, vector0) of the first multiplicator (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) in the multiplicator input end (Fig. 9 right-hand-side, arrow into Multiplier “* Vector Masking (zero insert) * Vector Sign Extension”; Fig. 1, section where multiplier (B) is input) is the same as a position of the first multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)) in the multiplicand input end, and a position (Fig. 8, pp4-pp7; Fig. 6, vector1; Fig. 5, vector1; Fig. 3, vector1; Fig. 2, vector1) of the second multiplicator (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) in the multiplicator input end is the same as a position of the second multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)) in the multiplicand input end (Fig. 9 left-hand-side, arrow into Multiplicand “* Vector Masking and Muxing * Vector Sign Extension * Vector Sign Encoding * Vector Twos Complement Increment”; Fig. 1, section where multiplicand (A) is input).
Although Danysh teaches the multiplicand (A) generally, it appears they are silent with expressing the specific portioning of bits (first and second multiplicand) based on the various vector modes as was taught with such great detail with respect to the multiplier (B) (Fig. 10).
However, it would have been obvious to modify by one of ordinary skill in the art before the effective filing date given the finite number of ways to partition the multiplicand (A) data for calculations. In practicality, there are only a finite number of reasonable ways to partition 64 bits of data, so it would have been obvious to try splitting multiplicand (A) data similarly to how multiplier (B) data was partitioned (Fig. 10, 8-bit increments for vectors 0-7 in 8-bit mode, 16-bit increments for vectors 0-3 in 16-bit mode, 32-bit increments for vectors 0-2 in 32-bit mode), where the first multiplicand is (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed), the second multiplicand is (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed). Further, it would have been obvious to try the particular location, positioning, and extending techniques on multiplicand (A) data similarly to how multiplier (B) data was applied: the first multiplicand located at a less significant bit (Fig. 10, vector 0 containing the [7:0] bits in 8-bit mode, and [15:0] bits in 16-bit mode, where bit 0 is the LSB and 63 is the MSB), the second multiplicand located at a more significant bit (Fig. 10, vector 1 containing the [15:8] bits in 8-bit mode, and [31:16] bits in 16-bit mode, where bit 0 is the LSB and 63 is the MSB), one extended bit of 0 inserted at an end of a least significant bit of the first multiplicand (Fig. 10, “0” inserted in vector0; Pg. 286, Col. 1, Para. 2), another bit set to 0 other than the first multiplicand (Fig. 10, “0” inserted in vector1; Pg. 286, Col. 1, Para. 2), the same position as the first multiplicand (Fig. 8, pp0-3 for vector0; Fig. 6, vector0; Fig. 5, vector0; Fig. 3, vector0; Fig. 2, vector0), and the same position as the second multiplicand (Fig. 8, pp4-7 for vector1; Fig. 6, vector1; Fig. 5, vector1; Fig. 3, vector1; Fig. 2, vector1). Danysh’s vector MAC architecture utilizes the “shared subtree” or the “shared segmentation” method for computations. Implementing these methods and particular features assists with data alignment where the shared segmentation segments based on the size of the smallest element or subword (Pg. 284, Col. 1, Sec. 1, Para. 1), and shared subtree arranges partial products to overlap (Pg. 285, Col. 1, Para. 2). It would have been obvious to one of ordinary skill in the art to implement multiplicand (A) with the same partitioning as multiplier (B) for alignment purposes when generating partial products correctly, and further to achieve the benefits of utilizing the specific shared methods (Pg. 292, Sec. 5, Para. 2).

Regarding claim 8, in addition to the teachings addressed in the claim 7 analysis, the rejection of claim 7 is incorporated and Danysh teaches further comprising:
a selector (Fig. 14, “select multiplicand bits or hot ones” Muxes; Fig. 15, “select multiplicand bits or hot ones” 6:1 Mux; Pg. 288, Col. 1, Para. 2, Col. 2, Para. 1), wherein the first multiplicand and the second multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)) are separated by at least one bit of 0, the first multiplicator (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) and the second multiplicator (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) are separated by at least one bit of 0 (Fig. 10, “0” bit in vector1), and wherein the selector is configured to:
output data of a most significant bit of the first multiplicand to a most significant bit (Fig. 14, left-hand-side of inverter and NAND gate configuration output of multiplicand masking; Pg. 287, Col. 2, Para. 1) of a corresponding first sub-encoder (Fig. 14, far-left 2:1 Mux), and output data 0 to a least significant bit of a sub-encoder (Fig. 14, far-right 2:1 Mux with 0 and ‘hot one’ inputs) that is adjacent (Fig. 14, muxes in a row) to the first sub-encoder (Fig. 14, far-left 2:1 Mux) and that encodes an idle bit, wherein the idle bit is a bit set to 0 (Fig. 14, “0”) between the first multiplicand and the second multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)).
Although Danysh teaches the multiplicand (A) generally, it appears they are silent with expressing the specific portioning of bits (first and second multiplicand) based on the various vector modes as was taught with such great detail with respect to the multiplier (B) (Fig. 10).
However, it would have been obvious to modify by one of ordinary skill in the art before the effective filing date given the finite number of ways to partition the multiplicand (A) data for calculations. In practicality, there are only a finite number of reasonable ways to partition 64 bits of data, so it would have been obvious to try splitting multiplicand (A) data similarly to how multiplier (B) data was partitioned (Fig. 10, 8-bit increments for vectors 0-7 in 8-bit mode, 16-bit increments for vectors 0-3 in 16-bit mode, 32-bit increments for vectors 0-2 in 32-bit mode), where the first multiplicand is (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed), the second multiplicand is (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed). Further, it would have been obvious to try the particular separating techniques on multiplicand (A) data similarly to how multiplier (B) data was applied: separated by at least one bit of 0 (Fig. 10, “0” bit in vector1, in vector0). Danysh’s vector MAC architecture utilizes the “shared subtree” or the “shared segmentation” method for computations. Implementing these methods and particular features assists with data alignment where the shared segmentation segments based on the size of the smallest element or subword (Pg. 284, Col. 1, Sec. 1, Para. 1), and shared subtree arranges partial products to overlap (Pg. 285, Col. 1, Para. 2). It would have been obvious to one of ordinary skill in the art to implement multiplicand (A) with the same partitioning as multiplier (B) for alignment purposes when generating partial products correctly, and further to achieve the benefits of utilizing the specific shared methods (Pg. 292, Sec. 5, Para. 2).

Regarding claim 9, in addition to the teachings addressed in the claim 7 analysis, the rejection of claim 7 is incorporated and Danysh teaches further comprising:
a selector (Fig. 14, “select multiplicand bits or hot ones” Muxes; Fig. 15, “select multiplicand bits or hot ones” 6:1 Mux; Pg. 288, Col. 1, Para. 2, Col. 2, Para. 1), wherein a most significant bit of the first multiplicand is adjacent to a least significant bit of the second multiplicand (Fig. 9, A[63:0]; Fig. 1, multiplicand (A)), a most significant bit of the first multiplicator (Fig. 10,

S

0

in vector0) is adjacent to a least significant bit of the second multiplicator (Fig. 10, “0” in vector1), and wherein the selector is configured to:
output data of the most significant bit of the first multiplicand to a most significant bit (Fig. 14, left-hand-side of inverter and NAND gate configuration output of multiplicand masking; Pg. 287, Col. 2, Para. 1) of a corresponding first sub-encoder (Fig. 14, far-left 2:1 Mux), and output data 0 to a least significant bit of a second sub-encoder (Fig. 14, far-right 2:1 Mux with 0 and ‘hot one’ inputs), wherein the second sub-encoder is a sub-encoder that is adjacent (Fig. 14, muxes in a row) to the first sub-encoder and that encodes the second multiplicand (Pg. 287, Col. 2, Para. 1-2).
Although Danysh teaches the multiplicand (A) generally, it appears they are silent with expressing the specific portioning of bits (first and second multiplicand) based on the various vector modes as was taught with such great detail with respect to the multiplier (B) (Fig. 10).
However, it would have been obvious to modify by one of ordinary skill in the art before the effective filing date given the finite number of ways to partition the multiplicand (A) data for calculations. In practicality, there are only a finite number of reasonable ways to partition 64 bits of data, so it would have been obvious to try splitting multiplicand (A) data similarly to how multiplier (B) data was partitioned (Fig. 10, 8-bit increments for vectors 0-7 in 8-bit mode, 16-bit increments for vectors 0-3 in 16-bit mode, 32-bit increments for vectors 0-2 in 32-bit mode), where the first multiplicand is (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed), the second multiplicand is (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed). Further, it would have been obvious to try the particular adjacency techniques on multiplicand (A) data similarly to how multiplier (B) data was applied: wherein most significant bit of the first multiplicand (Fig. 10,

S

0

in vector0) is adjacent to a least significant bit of the second multiplicand (Fig. 10, “0” in vector1). Danysh’s vector MAC architecture utilizes the “shared subtree” or the “shared segmentation” method for computations. Implementing these methods and particular features assists with data alignment where the shared segmentation segments based on the size of the smallest element or subword (Pg. 284, Col. 1, Sec. 1, Para. 1), and shared subtree arranges partial products to overlap (Pg. 285, Col. 1, Para. 2). It would have been obvious to one of ordinary skill in the art to implement multiplicand (A) with the same partitioning as multiplier (B) for alignment purposes when generating partial products correctly, and further to achieve the benefits of utilizing the specific shared methods (Pg. 292, Sec. 5, Para. 2).

Regarding claim 10, in addition to the teachings addressed in the claim 4 analysis, the rejection of claim 4 is incorporated and Danysh teaches further comprising:
a partial product sub-circuit (Fig. 16, Partial Product Reduction Tree; Fig. 1, PPRT; Pg. 288, Col. 2, Sec. 2.3, Para. 1-2) comprises a plurality of first partial product sub-circuits (Fig. 16, 4:2 CSA with inputs pp0-pp3 and direct connections to other 4:2 CSA below it), a plurality of second partial product sub-circuits (Fig. 16, 4:2 CSA with inputs pp7-pp4 and direct connections to other 4:2 CSA below it), and a plurality of third partial product sub-circuits (Fig. 16, 4:2 CSA with inputs pp8-pp11 and direct connections to other 4:2 CSA below it), wherein
the plurality of first partial product sub-circuits are configured to respectively calculate a plurality of first partial products (Fig. 16, outputs from the 4:2 CSA with inputs pp0-pp3) based on the first mask (Fig. 9, output from Radix-4 Booth Recoder; Fig. 10, B[15:8] and “0” in vector 1 in 8-bit mode and B[31:16] and “0” in vector 1 in 16-bit mode as an example before the sign extensions operations are performed) result by using a plurality of encoding results of the first multiplicand as control signals (Fig. 14, 5:1 Mux utilizing booth selects as computed in previous stage; Pg. 286, Col. 2, Sec. 2.2.2, Para. 2-4; Pg. 287, Col. 2, Para. 1-2);
the plurality of second partial product sub-circuits are configured to respectively calculate a plurality of second partial products (Fig. 16, outputs from the 4:2 CSA with inputs pp7-pp4) based on the second mask (Fig. 9, output from Radix-4 Booth Recoder; Fig. 10, B[7:0] and “0” in vector 0 in 8-bit mode and B[15:0] and “0” in vector 0 in 16-bit mode as an example before the sign extensions operations are performed) result by using a plurality of encoding results of the second multiplicand as control signals (Fig. 14, 5:1 Mux utilizing booth selects as computed in previous stage; Pg. 286, Col. 2, Sec. 2.2.2, Para. 2-4; Pg. 287, Col. 2, Para. 1-2);
the plurality of third partial product sub-circuits are configured to respectively calculate a plurality of third partial products (Fig. 16, outputs from the 4:2 CSA with inputs pp8-pp11) based on data in the multiplicator input end (Pg. 285, Col. 2, Sec. 2.2, Para. 1, inputting multiplier (B) operand) by using idle bits as control signals (Fig. 14, “0” in far-left mux; Fig. 10, “0” inserted at LSB at the end of vector0), wherein the idle bits are bits set to 0 in the multiplicand input end (Fig. 14, far-left 2:1 Mux, “0” as computed in previous stage); and
the accumulator (Fig. 1, Final Carry-Propagate Adder (CPA), Pg. 289, Col. 1-2, Sec. 2.4, Vector Final Carry Propagate Adder (CPA)) is configured to accumulate (Pg. 292, Col. 1, Para. 1, the remaining partial products) the plurality of first partial products (Fig. 16, outputs from the 4:2 CSA with inputs pp0-pp3), the plurality of second partial products (Fig. 16, outputs from the 4:2 CSA with inputs pp7-pp4), and the plurality of third partial products (Fig. 16, outputs from the 4:2 CSA with inputs pp8-pp11).
Although Danysh teaches the multiplicand (A) generally, it appears they are silent with expressing the specific portioning of bits (first and second multiplicand) based on the various vector modes as was taught with such great detail with respect to the multiplier (B) (Fig. 10).
However, it would have been obvious to modify by one of ordinary skill in the art before the effective filing date given the finite number of ways to partition the multiplicand (A) data for calculations. In practicality, there are only a finite number of reasonable ways to partition 64 bits of data, so it would have been obvious to try splitting multiplicand (A) data similarly to how multiplier (B) data was partitioned (Fig. 10, 8-bit increments for vectors 0-7 in 8-bit mode, 16-bit increments for vectors 0-3 in 16-bit mode, 32-bit increments for vectors 0-2 in 32-bit mode), where the first multiplicand is (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed), the second multiplicand is (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed). Danysh’s vector MAC architecture utilizes the “shared subtree” or the “shared segmentation” method for computations. Implementing these methods assists with data alignment where the shared segmentation segments based on the size of the smallest element or subword (Pg. 284, Col. 1, Sec. 1, Para. 1), and shared subtree arranges partial products to overlap (Pg. 285, Col. 1, Para. 2). It would have been obvious to one of ordinary skill in the art to implement multiplicand (A) with the same partitioning as multiplier (B) for alignment purposes when generating partial products correctly, and further to achieve the benefits of utilizing the specific shared methods (Pg. 292, Sec. 5, Para. 2).

Regarding claim 12, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Danysh teaches wherein the mask circuit (see claim 1 mapping) comprises:
two AND gates (Fig. 14 and Fig. 15, NAND gate “Mask for LSB tuple for each multiplier in vector”; Note: a NAND gate is simply an AND gate followed by an inverter gate, merely performs the logical inverse of an AND gate), and the two AND gates are configured to respectively mask (Pg. 288, Col. 1, Para. 2, Col. 2, Para. 1) the first multiplicator (Fig. 10, B[15:8] and “0” in vector 1 in 8-bit mode and B[31:16] and “0” in vector 1 in 16-bit mode as an example before the sign extensions operations are performed) and mask the second multiplicator (Fig. 10, B[7:0] and “0” in vector 0 in 8-bit mode and B[15:0] and “0” in vector 0 in 16-bit mode as an example before the sign extensions operations are performed) to output the second and first mask results (Fig. 9, output of Multiplier “* Vector Masking (zero insert) * Vector Sign Extension”; Fig. 14 and Fig. 15, output of NAND gate).
Although Danysh discloses utilizing only one NAND gate for the masking functionality on each of the vectors(Fig. 14 and Fig. 15, “Mask for LSB tuple for each multiplier in vector”), they are silent with explicitly disclosing a second NAND gate, to total to two NAND gates, to perform the masking functionality.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to add a second NAND gate, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.

Claims 13-16, 18 are directed to a method that would be practiced by the device of claims 1-4, 6. The claims 13-16, 18 analysis similarly applies to claims 1-4, 6, and claims 13-16, 18 are equally rejected.

Claims 19-20 are directed to a system that recites similar limitations to the device of claims 1, 3, respectively. The claims 1, 3 analysis similarly applies to claims 19-20, and claims 19-20 are equally rejected.

Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Danysh in view of Brooks as applied to claims 1 and 13 above, and further in view of US 11409692 B2 Das Sarma et al. (hereinafter “Das Sarma”).

Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Danysh teaches further comprising:
an adder (Fig. 16, one of the 4:2 CSA; Pg. 288, Col. 2, Sec. 2.3, Para. 1-2), and wherein the adder is configured to:
add (Pg. 288, Col. 2, Sec. 2.3, Para. 1-2, the partial products, which contain the results of the multiplication of the first and second, are terms added for generating the final result, final sum and carry) the result of multiplying the first multiplicator and the first multiplicand (Fig. 8, pp0-pp3, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2) and the result of multiplying the second multiplicator and the second multiplicand (Fig. 8, pp4-pp7, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2); and
the multiplier is further configured to a result of adding (Fig. 8, pp32, Pg. 285, Col. 1, Para. 3, Col. 2, Para. 1; Fig. 16, 4:2 CSA combing previous 4:2 CSA results of pp0-3 and pp4-7, Pg. 288, Col. 2, Sec. 2.3, Para. 1-2) the result of multiplying the first multiplicator and the first multiplicand (Fig. 8, pp0-pp3, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2) and the result of multiplying the second multiplicator and the second multiplicator (Fig. 8, pp4-pp7, Pg. 287, Col. 1, Para. 2, Col. 2, Para. 1-2).
Although Danysh teaches the multiplicand (A) generally, it appears they are silent with expressing the specific portioning of bits (first and second multiplicand) based on the various vector modes as was taught with such great detail with respect to the multiplier (B) (Fig. 10).
However, it would have been obvious to modify by one of ordinary skill in the art before the effective filing date given the finite number of ways to partition the multiplicand (A) data for calculations. In practicality, there are only a finite number of reasonable ways to partition 64 bits of data, so it would have been obvious to try splitting multiplicand (A) data similarly to how multiplier (B) data was partitioned (Fig. 10, 8-bit increments for vectors 0-7 in 8-bit mode, 16-bit increments for vectors 0-3 in 16-bit mode, 32-bit increments for vectors 0-2 in 32-bit mode), where the first multiplicand is (Fig. 10, B[7:0] in vector 0 in 8-bit mode and B[15:0] in vector 0 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed) and the second multiplicand is (Fig. 10, B[15:8] in vector 1 in 8-bit mode and B[31:16] in vector 1 in 16-bit mode as an example before the masking (zero insertion) and sign extensions operations are performed). Danysh’s vector MAC architecture utilizes the “shared subtree” or the “shared segmentation” method for computations. Implementing these methods assists with data alignment where the shared segmentation segments based on the size of the smallest element or subword (Pg. 284, Col. 1, Sec. 1, Para. 1), and shared subtree arranges partial products to overlap (Pg. 285, Col. 1, Para. 2). It would have been obvious to one of ordinary skill in the art to implement multiplicand (A) with the same partitioning as multiplier (B) for alignment purposes when generating partial products correctly, and further to achieve the benefits of utilizing the specific shared methods (Pg. 292, Sec. 5, Para. 2).
Danysh is silent with disclosing using in a convolutional neural network process.
Brooks, and the combination of Danysh in view of Brooks are silent with disclosing using in a convolutional neural network process.
Das Sarma discloses using in a convolutional neural network process (co. 30 ln. 45-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Danysh in view of Brooks’ modified multiplier with Das Sarma’s convolutional process feature because they are in the claimed invention’s same field of endeavor of multipliers (co. 27 ln. 59-67, co. 28 ln. 1-2). It would have been obvious to one of ordinary skill in the art to implement the convolutional process feature, as doing so would provide a greater range of applications the modified multiplier can be used in, such as processing for machine learning and artificial intelligence uses (co. 1 ln. 22-52). Making this modification would have been obvious to try and would be beneficial as Danysh in view of Brooks’ modified multiplier now has support for use in other applications, thus providing greater usability and flexibility of application-use.

Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Danysh in view of Brooks as applied to claim 1 above, and further in view of Horowitz.

Regarding claim 11, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Danysh teaches further comprising:
a switch, wherein the switch is configured to: when in an on state, activate the mask circuit (Fig. 9 right-hand-side, Multiplier “* Vector Masking (zero insert) * Vector Sign Extension” box); and when in an off state, disable the mask circuit.
Although Danysh teaches the mask circuit, it appears they are silent with disclosing a switch to activate it when in an on state, and to disable it when in an off state. Further, Brooks and the combination of Danysh in view of Brooks are silent with disclosing a switch to activate it when in an on state, and to disable it when in an off state.
Horowitz teaches a switch (Pg. 184, Col. 2, Sec. 3.4.4, Para. 1, FET switch) that activates when in an on state (Pg. 184, Col. 2, Sec. 3.4.4, Para. 1, turning on power), and disables when in an off state (Pg. 184, Col. 2, Sec. 3.4.4, Para. 1, turning off power).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Danysh in view of Brooks’ modified multiplier with Horowitz’s switch because they are in the claimed invention’s same field of endeavor of digital circuit design (Pg. 184, Col. 2, Sec. 3.4.4, Para. 1). It would have been obvious to one of ordinary skill in the art to implement the switch, as it allows the designers to effectively control whether the masking circuit is required to be used or not, by activating or not (Pg. 184, Col. 2, Sec. 3.4.4, Para. 1). Making this modification would be beneficial, as Danysh in view of Brooks’ multiplier now has support for optimization, making it more power efficient by turning off the masking circuit when it’s not required and thus reduces computational complexity when not required to make those calculations.

Response to Arguments
Drawings. The drawings objections have been withdrawn based on the amendments to the drawings.

Specification. The specification objections have been withdrawn based on the amendments to the Abstract and specification.

35 USC 112(b). The rejections have been withdrawn based on the amendment to the claims.

35 USC 101. Applicant argues the following in substance.
Applicant asserts that, the invention of claim 1 integrates an alleged exception into a practical application by providing an improvement in the functioning of a computer, or an improvement to other technology or technical field In particular, the specification teaches the following improvements resulting from the above recited features of claim 1 such as the mask circuit (Remarks p. 16). Therefore, the multiplier 500 can be adapted to multiplication operations of a plurality of low bit width multiplicators and a plurality of low bit width multiplicands in different data formats, thereby resolving a problem of a hardware resource waste caused because a single multiplier can process a multiplication operation of only one data format (Remarks p. 17). The invention of claim 1 provides a technological solution to a technological problem and thus is directed to significantly more than an abstract idea. For example, the specification discusses at least the following technological problems regarding wasted resources and reduced efficiency and also regarding how to simultaneously implement a plurality of low bit width multiplication operations (Remarks p. 18).

Examiner respectfully disagrees. The purported improvements are a direct result of the mathematical concepts. No additional element or combination of additional element is claimed that result in the purported improvement beyond the mathematical steps. It is the abstract idea, the manner of applying mathematical relationships of masking that results in the purported improvement of the multiplier being adapted to different data formats, as further described in the specification in [0079-0080], [00112]. This is also further evidenced in Applicant’s Remarks filed 12/05/2025 p. 19, ⁋ 2, where Applicant credits masking with resulting in the purported improvement. Thus, configuring the multiplier to be adapted based on the masking beforehand is a direct consequence of the mathematics, the abstract idea, and therefore, the improvements, and the structures of the mask circuit and multiplier, flow from the abstract idea.
See MPEP 2106.05(a)(II). “It is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology.” See also MPEP 2106.05. An inventive concept "cannot be furnished by the unpatentable law of nature (or natural phenomenon or abstract idea) itself."

Applicant asserts that, the specifically recited features of claim 1 and its dependents provide the above technological solutions to technological problems. In this regard, claim 1 is similar to the claims found patent eligible in DDR Holdings, LLC, which were determined to be rooted in computer technology in order to overcome a problem specifically arising in the realm of computer technology (Remarks p. 19).
Examiner respectfully disagrees. The claims in the cited case are unlike those in the instant application. The additional elements recited in claim 1 are analyzed recited at a high level of generality, result in merely “apply it”, merely generally linked to a particular technological environment, and/or examples of an insignificant extra-solution activity. The courts have also identified limitations that did not integrate a judicial exception into a practical application: Merely reciting the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f); Adding insignificant extra-solution activity to the judicial exception, as discussed in MPEP § 2106.05(g); and generally linking the use of a judicial exception to a particular technological environment or field of use, as discussed in MPEP § 2106.05(h). See MPEP 2106.04(d)(I).

35 USC 103. Applicant’s arguments, see Remarks p. 19, filed 12/05/2025, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Brooks and in view of Das Sarma, as necessitated by the amendment.

Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is [phone]. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151

/James Trujillo/Supervisory Patent Examiner, Art Unit 2151

Prosecution Timeline

• Mar 18, 2022: Application Filed
• Apr 28, 2022: Response after Non-Final Action
• Sep 03, 2025: Non-Final Rejection — §101, §103, §112
• Dec 05, 2025: Response Filed
• Feb 24, 2026: Final Rejection — §101, §103, §112 (current)