Prosecution Insights
Last updated: April 19, 2026
Application No. 17/698,365

MICROELECTRONIC ASSEMBLIES INCLUDING STIFFENERS

Final Rejection §102
Filed
Mar 18, 2022
Examiner
BULLARD-CONNOR, GENEVIEVE GRACE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
43%
Grant Probability
Moderate
3-4
OA Rounds
3y 5m
To Grant
53%
With Interview

Examiner Intelligence

Grants 43% of resolved cases
43%
Career Allow Rate
3 granted / 7 resolved
-25.1% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
61 currently pending
Career history
68
Total Applications
across all art units

Statute-Specific Performance

§103
48.2%
+8.2% vs TC avg
§102
32.7%
-7.3% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 21-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lo et al. (“Lo” US 2022/0068736). Regarding claim 21, Lo discloses: A microelectronic assembly (Figure 31), comprising: a substrate (222); and a microelectronic subassembly (150) coupled to the substrate (222) by interconnects (142, see Figures 27 and 31), the microelectronic subassembly (150) including: an interposer (102) having a surface (upper surface in Figures 11 and 31); a first die (50) coupled to the surface of the interposer (102, see Figure 31); a second die (124) coupled to the surface of the interposer (102, see Figure 31); a first stiffener (120) coupled to the surface of the interposer (102) along a perimeter of the interposer (plan view of 118, 120 along perimeter of interposer 102 is shown in Figures 4B, 12B, material 120 adheres material 118 to the interposer 102, thus would be stacked directly under with the same pattern as 118), the first stiffener (120) having a first material (para. [0044] discloses 120 as comprising an adhesive or a metallic material, since the materials both strengthen the package, 120 is considered as a stiffener component); and a second stiffener (118) on the first stiffener (120, see Figure 11), the second stiffener (118) having a second material different from the first material (para. [0044] discloses stiffener 118 as comprising silicon oxide [a known component of glass, i.e. silica], silicon, aluminum oxide [a known ceramic material], aluminum nitride [another known ceramic material], which are different from materials disclosed for stiffener 120). Regarding claim 22, Lo discloses: The microelectronic assembly of claim 21, further comprising: an insulating material (134, para. [0048]) around the first and second dies (50, 124, see Figure 11). Regarding claim 23, Lo discloses: The microelectronic assembly of claim 21, wherein a material of the first stiffener (120) includes glass, silicon, a metal, a metal alloy, or a ceramic (para. [0044] discloses 120 as comprising an adhesive or a metallic material), and a material of the second stiffener includes glass, silicon, a metal, a metal alloy, or a ceramic (para. [0044] discloses stiffener 118 as comprising silicon oxide [a known component of glass, i.e. silica], silicon, aluminum oxide [a known ceramic material], aluminum nitride [another known ceramic material]). Regarding claim 24, Lo discloses: The microelectronic assembly of claim 21, wherein an overall thickness of the first stiffener and the second stiffener (118, 120) is equal to between 20% and 120% of a thickness of the first die (50) or the second die (124, see Figure 31 and para. [0044] discloses that the stiffener has the same height as IC die 50 as measured from the top surface of 104, thus the components have the same thickness as measured from the top surface of 104). Regarding claim 25, Lo discloses: The microelectronic assembly of claim 22, wherein the insulating material (134) includes a dielectric material or a mold material (para. [0048] discloses 134 as a molding compound, a polymer, an epoxy, etc.). Regarding claim 26, Lo discloses: The microelectronic assembly of claim 21, further comprising: an underfill material (144, composed of a polymeric material, see para. [0053], [0051], and [0024] disclosing that material 144 may be the same composition as material 140, and 140 may be the same composition as material 64, which comprises a polymeric material, which is a known insulating underfill material in the art) around the interconnects (142). Regarding claim 27, Lo discloses: The microelectronic assembly of claim 21, further comprising: a circuit board (400) coupled to the substrate (222, see Figure 31). Response to Arguments Applicant's arguments filed November 10 2025 have been fully considered but they are not persuasive. Applicant asserts that one of ordinary skill in the art would not construe the attaching structure 120 of Lo as a stiffener because it is “neither the ordinary nor customary understanding of a ‘stiffener’.” The examiner respectfully disagrees. Lo’s attaching structure being specifically an adhesive material is only one of the possible materials Lo has disclosed for the attaching structure. Lo also discloses, in para. [0044], that the attaching structure 120 can also be a metallic material (specifically, one or more metal pillars with metal cap layers) which Applicant has explicitly disclosed as a material that can be used for a stiffener structure (see para. [0038] of the instant application). Therefore, it is the examiner’s position that Applicant has narrowly construed Lo’s attaching structure 120 to the claimed first stiffener to reference only the embodiment of Lo where the attaching structure 120 is an adhesive. However, the examiner clearly stated in the Office action (see pages 5-6) that the attaching structure 120 of Lo can comprise an adhesive material or a metallic material. Further, if Applicant is alleging that the attaching structure 120 of Lo does not provide strength to a semiconductor package, and thus should not be construed as a stiffener structure, the examiner respectfully disagrees. It is well known in the art that the purpose of an adhesive between two layers of a semiconductor package is to increase adhesion between said layers, thus increasing the reliability and overall strength of the package. In contrast, a package with two materials, that do not adhere well, in direct face contact with each other, without an adhesive therebetween, the strength of the package would overall be reduced as delamination would be more likely to occur. Applicant has further requested that the examiner provide evidence of “common usage among those of skill in the art demonstrating the propriety of labeling Lo’s attaching structure 118 [sic] (e.g., adhesives) a ‘stiffener’.” Accordingly, the examiner would like to reference several documents that use an adhesive material, specifically an epoxy material (the attaching structure 120 of Lo as an adhesive can comprise an epoxy material, see para. [0045]) as a stiffener in a semiconductor package: US Patent No. 11,854,930 (Tsai et al.) discloses the use of an epoxy sheet to reduce package warpage, see col 4, lines 58-63 “a multi-layer laminate epoxy sheet that functions as a mold cap for package warpage,” see multi-layer laminate epoxy sheet 200 in Figures 1 and 2. US Patent Application Publication US 2020/0411448 (Goh et al.) discloses that “the conductive stiffener may be formed with polymers, polymer-metals, and/or polymer-ceramic composites (e.g., metal-filled or ceramic-filled polymers or resins, epoxy molding compounds, etc.),” in para. [0028], see conductive stiffener 120 in Figure 1. US Patent Application Publication US 2014/0048951 (Lin et al.) discloses that the stiffener 41 “can include ceramic material, metal material or epoxy-based laminate” in para. [0054]-[0055], see stiffener 41 in Figure 2. US Patent Application Publication US 2012/0018871 (Lee et al.) discloses that the supporter 310 “may be formed of an epoxy resin having high rigidity” in para. [0077], see supporter 310 in Figure 1. Therefore, it is abundantly clear that an adhesive material is customarily used in the art as a stiffener for a semiconductor package. Applicant’s arguments are not found persuasive and the rejection is maintained. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 18, 2022
Application Filed
Jan 05, 2023
Response after Non-Final Action
Aug 19, 2025
Non-Final Rejection — §102
Nov 10, 2025
Response Filed
Nov 20, 2025
Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12525517
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Jan 13, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
43%
Grant Probability
53%
With Interview (+10.0%)
3y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allow rate.

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