Prosecution Insights
Last updated: April 19, 2026
Application No. 17/698,430

MICROELECTRONIC ASSEMBLIES INCLUDING STIFFENERS

Non-Final OA §103
Filed
Mar 18, 2022
Examiner
BULLARD-CONNOR, GENEVIEVE GRACE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
3 (Non-Final)
43%
Grant Probability
Moderate
3-4
OA Rounds
3y 5m
To Grant
53%
With Interview

Examiner Intelligence

Grants 43% of resolved cases
43%
Career Allow Rate
3 granted / 7 resolved
-25.1% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
61 currently pending
Career history
68
Total Applications
across all art units

Statute-Specific Performance

§103
48.2%
+8.2% vs TC avg
§102
32.7%
-7.3% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 14 2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 7, 9, 12-13, 15, 17-19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (“Lo” US 2022/0068736) and Pon et al. (“Pon” US 2020/0118941). Regarding claim 1, Lo discloses a microelectronic assembly (Figure 31), comprising: a substrate (within package component 220, the substrate includes the wafer 102 of stacked structure 150, redistribution structure 222, encapsulants 134/220, and stiffener structure 118), including: a core (encapsulants 134/220, labeled in Figures 22 and 31); a first stiffener (118 outer ring portion, see plan view of the stiffener 118 in Figure 12B, where the outer portion of 118 is the first stiffener) in the core (134/220, see Figure 31), wherein the first stiffener (118 outer portion) is along a perimeter of the core (134/220, see Figures 12B and 31); and a second stiffener (118 inner portion, see plan view of the stiffener 118 in Figure 12B) in the core (134/220, see Figure 31), wherein the second stiffener (118 inner portion) is along a perimeter of the core (134/220, see Figures 12B and 31) and is [separated from and] concentric with the first stiffener (118 outer portion, see Figure 12B, since the first and second stiffeners are inner and outer portions of the same ring structure, they are thus concentric); and a die (50) electrically coupled to the substrate (102/222/134/220/118, see electrical coupling to at least the interconnections of wafer 102, and the redistribution structure 222 of the substrate) and having a footprint (here footprint is the vertical projection of the surface area of the die 50), wherein the first and second stiffeners (118, inner and outer portions) are entirely outside of the footprint of the die (50, see Figure 12B which shows the vertical projection of the die 50 being within the boundaries of the stiffener structures). Lo does not disclose that the second stiffener is separated from the first stiffener. However, Pon discloses in Figures 3C and 3E a stiffener structure (reinforcement rings 330/3301) that can be between buildup layers 310A-310C (see para. [0046] and Figure 3C) and comprise one or more concentric rings on the same surface in the package (see para. [0046]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Pon into the teachings of Lo to include two concentric, separated stiffener structures in the package layers for the purpose of providing structural support within the package at several stress points therein. The structural arrangement was known in the prior art and one skilled in the art could have combined the separated, concentric stiffeners as taught by Pon into the teachings of Lo with no change in their respective functions, and the combination would have yielded the predictable result of providing structural support to different parts of the core of the package to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 2, Lo discloses wherein the first stiffener (118 outer portion) is a continuous ring along a perimeter of the core (134/220, see Figures 12B and 31). Regarding claim 7, Lo discloses wherein a thickness of the first stiffener (118 outer portion) is between 0.1 millimeters and 1.4 millimeters (Lo discloses in para. [0056] a thickness of the stiffener structure being between 50 and 800 microns, i.e. 0.05 and 0.8 millimeters, which overlaps with the claimed thickness range). The Examiner notes that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Regarding claim 9, Lo discloses wherein a material of the first stiffener (118 outer portion) includes silicon, glass, a metal, an amorphous metal alloy, or a ceramic (see para. [0044] discloses that the stiffener 118 may be made of silicon, a dielectric material, aluminum nitride, which is a known ceramic material, or the life, or a combination thereof). Regarding claim 12, Lo discloses a microelectronic assembly (Figure 31), comprising: a substrate (within package component 220, the substrate includes the wafer 102 of stacked structure 150, redistribution structure 222, encapsulants 134/220, and stiffener structure 118) having a first surface (lower surface of the redistribution portion 222 of the substrate) and an opposing second surface (upper surface of the wafer portion 102 of the substrate), the substrate (102/222/134/220/118) including: a core (encapsulants 134/220); a first stiffener (118 outer portion) within the core (134/220, see Figures 12B and 31) along a perimeter of the core (see Figures 12B and 31); and a second stiffener (118 inner portion) in the core (134/220, see Figures 12B and 31), wherein the second stiffener (118 inner portion) is along a perimeter of the core (see Figures 12B and 31) and is [separated from and] concentric with the first stiffener (118 outer portion, see Figure 12B, since the first and second stiffeners are inner and outer portions of the same ring structure, they are thus concentric); a die (50) electrically coupled to the second surface (upper surface of the wafer portion 102 of the substrate, see electrical connection in at least Figures 11 and 31) of the substrate (102/222/134/220/118) and having a footprint (here footprint is the vertical projection of the surface area of the die 50), wherein the first and second stiffeners (118, inner and outer portions) are entirely outside of the footprint of the die (50, see Figure 12B which shows the vertical projection of the die 50 being within the boundaries of the stiffener structures); and a circuit board (400, see Figure 31) electrically coupled to the first surface of the substrate (lower surface of redistribution portion 222, see electrical contacts therebetween providing electrical coupling). Lo does not disclose that the second stiffener is separated from the first stiffener. However, Pon discloses in Figures 3C and 3E a stiffener structure (reinforcement rings 330/3301) that can be between buildup layers 310A-310C (see para. [0046] and Figure 3C) and comprise one or more concentric rings on the same surface in the package (see para. [0046]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Pon into the teachings of Lo to include two concentric, separated stiffener structures in the package layers for the purpose of providing structural support within the package at several stress points therein. The structural arrangement was known in the prior art and one skilled in the art could have combined the separated, concentric stiffeners as taught by Pon into the teachings of Lo with no change in their respective functions, and the combination would have yielded the predictable result of providing structural support to different parts of the core of the package to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 13, Lo discloses wherein the first stiffener (118 outer portion) is a continuous ring along a perimeter of the core (134/220, see Figures 12B and 31). Regarding claim 15, Lo discloses wherein a material of the first stiffener (118 outer portion) includes silicon, glass, a metal, an amorphous metal alloy, or a ceramic (see para. [0044] discloses that the stiffener 118 may be made of silicon, a dielectric material, aluminum nitride, which is a known ceramic material, or the life, or a combination thereof). Regarding claim 17, Lo discloses a method for fabricating a microelectronic assembly (Figure 31), the method comprising: forming a first stiffener (118 outer portion) in a core (134/220) of a substrate (within package component 220, the substrate includes the wafer 102 of stacked structure 150, redistribution structure 222, encapsulants 134/220, and stiffener structure 118), wherein the substrate (102/222/134/220/118) includes a first surface (lower surface of redistribution portion 222 of the substrate) and an opposing second surface (upper surface of wafer portion 102 of the substrate), and wherein the first stiffener (118 outer portion) is along a perimeter of the core (134/220) of the substrate (102/222/134/220/118, see Figures 12B and 31) and is configured to mitigate warpage (see para. [0018]); forming a second stiffener (118 inner portion) in the core (134/220) of the substrate (102/222/134/220/118), wherein the second stiffener (118 inner portion) is along a perimeter of the core (134/220) of the substrate (102/222/134/220/118, see Figures 12B and 31) and is [separated from and] concentric with the first stiffener (118 outer portion, see Figure 12B, since the first and second stiffeners are inner and outer portions of the same ring structure, they are thus concentric); and electrically coupling a die (50), having a footprint (here footprint is the vertical projection of the surface area of the die 50), to the second surface of the substrate (upper surface of the wafer portion 102 of the substrate, see electrical connection in at least Figures 11 and 31) positioned such that the first and second stiffeners (118) are entirely outside of the footprint of the die (50, see Figure 12B which shows the vertical projection of the die 50 being within the boundaries of the stiffener structures). Lo does not disclose that the second stiffener is separated from the first stiffener. However, Pon discloses in Figures 3C and 3E a stiffener structure (reinforcement rings 330/3301) that can be between buildup layers 310A-310C (see para. [0046] and Figure 3C) and comprise one or more concentric rings on the same surface in the package (see para. [0046]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Pon into the teachings of Lo to include two concentric, separated stiffener structures in the package layers for the purpose of providing structural support within the package at several stress points therein. The structural arrangement was known in the prior art and one skilled in the art could have combined the separated, concentric stiffeners as taught by Pon into the teachings of Lo with no change in their respective functions, and the combination would have yielded the predictable result of providing structural support to different parts of the core of the package to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 18, Lo discloses wherein a material of the first stiffener (118 outer portion) includes silicon, glass, a metal, an amorphous metal alloy, or a ceramic (see para. [0044] discloses that the stiffener 118 may be made of silicon, a dielectric material, aluminum nitride, which is a known ceramic material, or the life, or a combination thereof). Regarding claim 19, Lo discloses wherein the first stiffener (118 outer portion) is a continuous ring along a perimeter of the core (134/220, see Figures 12B and 31). Regarding claim 21, Lo discloses wherein a material of the second stiffener (118 inner portion) includes glass, silicon, a metal, a metal alloy, or a ceramic (see para. [0044] discloses that the stiffener 118 may be made of silicon, a dielectric material, aluminum nitride, which is a known ceramic material, or the life, or a combination thereof). Regarding claim 22, Lo discloses wherein the second stiffener (118 inner portion) is a continuous ring along a perimeter of the core (134/220, see Figures 12B and 31). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lo and Pon as applied to claim 1 above, and further in view of Mok (US 2020/0163218). Regarding claim 8, Lo discloses vias (216) in the core (134/220), but does not explicitly disclose plated through hole vias. Mok discloses in Figures 1 and 2, however, a core (11) further including a plated through hole (PTH) via (7, see Figures 1 and 2, and para. [0094] which discloses the through hole 7 can be a plated through hole, see also para. [0018]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Mok into the teachings of Lo to include the plated through hole vias for the purpose of aiding in heat dissipation (Mok, para. [0094]). Further, it would have been obvious to one having ordinary skill in the art to substitute one known element (plated through-hole vias of Mok) for another known equivalent element (vias of Lo) resulting in the predictable result of providing electrical connection between parts of an electronic package. See MPEP 2143 (I)(B). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lo and Pon as applied to claim 9 above, and further in view of Sinha et al. (“Sinha” 2022/0077076). Regarding claim 10, Lo does not explicitly disclose that the first stiffener structure includes or is made of a metal, or an amorphous metal alloy. Sinha discloses, however, a stiffener structure (reinforcement structure 230a) that includes a metal, or an amorphous metal alloy (see para. [0034]], which discloses suitable metallic materials to use for the stiffener 230a). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Sinha into the teachings of Lo to include a metallic material for the first stiffener structure for the purpose of utilizing a material with a high Young’s modulus for strengthening the semiconductor package (see para. [0034] of Sinha). Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07. Response to Arguments Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Mar 18, 2022
Application Filed
Jan 05, 2023
Response after Non-Final Action
Aug 25, 2025
Non-Final Rejection — §103
Nov 10, 2025
Response Filed
Nov 20, 2025
Final Rejection — §103
Jan 14, 2026
Request for Continued Examination
Jan 24, 2026
Response after Non-Final Action
Feb 17, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12525517
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Jan 13, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
43%
Grant Probability
53%
With Interview (+10.0%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allow rate.

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