DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/05/2026 has been entered.
Status of Application
In response to Office action mailed 12/09/2025, Applicants amended claims 1, 13 and 19 in the response filed 03/05/2026
Claim(s) 1-5 and 7-24 are pending examination.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 and 7-24 have been considered but are moot because the arguments do not apply to the new combination of references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 7-10, 12-13, 19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yasukawa et al. (PG Pub 2021/0183782; hereinafter Yasukawa) and Hwang et al. (PG Pub 2019/0057949; hereinafter Hwang).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 1 provided above, Yasukawa teaches a multi-die apparatus 1 comprising:
a mold material 32,33,34,35,36 (para [0058]);
a first integrated circuit die 22 within the mold material (see Fig. 1);
a second integrated circuit die 12 within the mold material above the first integrated circuit die (see Fig. 1);
one or more metal layers 14,15,16 within the mold material, the metal layers defining horizontal traces 15 between the first integrated circuit die and the second integrated circuit die (see Fig. 1); and
Although, Yasukawa teaches the horizontal traces 15 of the metal layers 14,15,16, he does not explicitly teach “one or more passive electrical components formed at least partially by traces within the metal layers.”
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In the same field of endeavor, refer to Fig. 1 and the Examiner’s mark-up of Fig. 2 (emphasis on Fig. 2) provided above, Hwang teaches a semiconductor package comprising: one or more passive electrical components 500 formed at least partially by traces 510 (112 of Fig. 1), 530 (122 of Fig. 1) within metal layers 112,122,132,142 (see Fig. 1 and Fig. 2).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the traces of Yasukawa to form a capacitor, as taught by Hwang, to “provide various functions, such as decoupling, filtering, and/or resonance damping” (para [0036]).
Regarding claim 3, refer to the cited figures above, the combination of Yasukawa and Hwang teach the one or more passive electrical components 500-Hwang includes a capacitor (para [0036]) formed by a portion of a first layer (14 of Yasukawa = 510 of Hwang) of the one or more metal layers, a portion of a second layer (16 of Yasukawa = 530 of Hwang) of the one or more metal layers, and a dielectric material (520 of Hwang) between the portions of the first layer and the second layer that define the capacitor (see Fig. 2).
Regarding claim 7 and claim 8, refer to the cited figures above, the combination of Yasukawa and Hwang teach (Regarding claim 7) the first integrated circuit die 22 comprises active circuitry (bottom of die), and the second integrated circuit die 12 comprises active circuitry (bottom of die) (see Fig. 1); and
(Regarding claim 8) wherein the first integrated circuit die 22 comprises a processor (para [0073]) and the second integrated circuit die 12 comprises one or more of a processor, memory circuitry, a voltage regulator, and a power management integrated circuit (PMIC (para [0062]).
Regarding claim 9 and claim 10, refer to the cited figures above, the combination of Yasukawa and Hwang teach
(Regarding claim 9) the first integrated circuit die 22 comprises active circuitry (bottom of die), and the second integrated circuit die 12 comprises active circuitry (bottom of die) (see Fig. 1); and
(Regarding claim 10) wherein the first integrated circuit die 22 comprises a processor (para [0073]) and the second integrated circuit die 12 comprises passive power delivery circuitry (para [0062]).
Regarding claim 12, refer to the cited figures above, the combination of Yasukawa and Hwang teach the metal layers 14,15,16 within the mold material 32,36 comprise one or more traces 14,16 to interconnect the first integrated circuit die and the second integrated circuit die (para [0060]).
Regarding claim 13, refer to the Examiner’s mark-up of Fig. 1 provided above, Yasukawa teaches an integrated circuit assembly 1 comprising:
a multi-die complex 1 comprising:
a mold material 32,33,34,35,36;
a first integrated circuit die 22 within the mold material (see Fig. 1);
a second integrated circuit die 12 within the mold material above the first integrated circuit die (see Fig. 1);
one or more metal layers 14,15,16 within the mold material (see Fig. 1), the metal layers defining horizontal traces 14,16 between the first integrated circuit die and the second integrated circuit die (see Fig. 1).
Although, Yasukawa teaches the multi-die complex and the traces within the mold material, he does not explicitly teach a package substrate; and one or more passive electrical components formed at least partially by traces within the metal layers.
In the same field of endeavor, refer to Fig. 1 and the Examiner’s mark-up of Fig. 2 (emphasis on Fig. 2) provided above, Hwang teaches a semiconductor package comprising: a package substrate 394; and one or more passive electrical components 500 formed at least partially by traces 510 (112 of Fig. 1), 530 (122 of Fig. 1) within metal layers 112,122,132,142 (see Fig. 1 and Fig. 2).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the traces of Yasukawa to form a capacitor, as taught by Hwang, to “provide various functions, such as decoupling, filtering, and/or resonance damping” (para [0036]). In addition, it would have been advantageous to couple the multi-die complex of Yasukawa to the package substrate of Hwang, to thereby provide the desired transmission of signals.
Regarding claim 15, refer to the cited figures above, the combination of Yasukawa and Hwang teach the one or more passive electrical components 500-Hwang includes a capacitor (para [0036]) formed by a portion of a first layer (14 of Yasukawa = 510 of Hwang) of the one or more metal layers 14,15,16, a portion of a second layer (16 of Yasukawa = 530 of Hwang) of the one or more metal layers, and a dielectric material (520 of Hwang) between the portions of the first layer and the second layer that define the capacitor (see Fig. 2).
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Regarding claim 19, refer to the Examiner’s mark-up of Fig. 31 provided above, Yasukawa teaches a computing system 10a comprising:
memory 61; and
a processor (annotated “processor” in Fig. 31) comprising a multi-die integrated circuit apparatus, the multi-die integrated circuit apparatus (annotated “apparatus” in Fig. 31) comprising:
a mold material 31-36;
a first integrated circuit die 22 within the mold material (see Fig. 31);
a second integrated circuit die 12 within the mold material above the first integrated circuit die (see Fig. 31);
one or more metal layers 14-16 within the mold material (see Fig. 31), the metal layers defining horizontal traces between the first integrated circuit die and the second integrated circuit die (see Fig. 31).
Although, Yasukawa teaches the horizontal traces 15 of the metal layers 14,15,16, he does not explicitly teach “one or more passive electrical components formed at least partially by traces within the metal layers.”
In the same field of endeavor, refer to Fig. 1 and the Examiner’s mark-up of Fig. 2 (emphasis on Fig. 2) provided above, Hwang teaches a semiconductor package comprising: one or more passive electrical components 500 formed at least partially by traces 510 (112 of Fig. 1), 530 (122 of Fig. 1) within metal layers 112,122,132,142 (see Fig. 1 and Fig. 2).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the traces of Yasukawa to form a capacitor, as taught by Hwang, to “provide various functions, such as decoupling, filtering, and/or resonance damping” (para [0036]).
Regarding claim 21, refer to the cited figures above, the combination of Yasukawa and Hwang teach the one or more passive electrical components 500-Hwang includes a capacitor (para [0036]) formed by a portion of a first layer (14 of Yasukawa = 510 of Hwang) of the one or more metal layers, a portion of a second layer (16 of Yasukawa = 530 of Hwang) of the one or more metal layers, and a dielectric material (520 of Hwang) between the portions of the first layer and the second layer that define the capacitor (see Fig. 2).
Claim(s) 2, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yasukawa and Hwang, as applied to claim 1, claim 13 and claim 19 respectively above, and further in view of Liu et al. (PG Pub 2019/0200454; hereinafter Liu).
Regarding claim 2, refer to the cited figures above, the combination of Yasukawa and Hwang teach the one or more passive electrical components 500-Hwang includes a capacitor formed in a layer of the one or more metal layers (see Fig. 2 above).
Hwang does not explicitly teach the one or more passive electrical components includes an inductor.
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In the same field of endeavor, refer to Fig. 3a and Fig. 3b-provided above, Liu teaches a three- dimensional inductor-capacitor apparatus 399 comprising: one or more passive electrical components 200 includes a inductor-capacitor (para [0024]) formed in a layer of one or more metal layers 210,220,230,240.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the traces of Yasukawa form a portion of the inductor, as taught by Liu, to minimize the distance between the passive device and the dies, as taught by Liu, to reduce the package size (para [0005]).
Regarding claim 14, refer to the cited figures above, the combination of Yasukawa and Hwang teach the one or more passive electrical components 500-Hwang includes a capacitor formed in a layer of the one or more metal layers (see Fig. 2 above).
Hwang does not explicitly teach the one or more passive electrical components includes an inductor.
In the same field of endeavor, refer to Fig. 3a and Fig. 3b-provided above, Liu teaches a three- dimensional inductor-capacitor apparatus 399 comprising: one or more passive electrical components 200 includes a inductor-capacitor (para [0024]) formed in a layer of one or more metal layers 210,220,230,240.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the traces of Yasukawa form a portion of the inductor, as taught by Liu, to minimize the distance between the passive device and the dies, as taught by Liu, to reduce the package size (para [0005]).
Regarding claim 20, refer to the cited figures above, the combination of Yasukawa and Hwang teach the one or more passive electrical components 500-Hwang includes a capacitor formed in a layer of the one or more metal layers (see Fig. 2 above).
Hwang does not explicitly teach the one or more passive electrical components includes an inductor.
In the same field of endeavor, refer to Fig. 3a and Fig. 3b-provided above, Liu teaches a three- dimensional inductor-capacitor apparatus 399 comprising: one or more passive electrical components 200 includes a inductor-capacitor (para [0024]) formed in a layer of one or more metal layers 210,220,230,240.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the traces of Yasukawa form a portion of the inductor, as taught by Liu, to minimize the distance between the passive device and the dies, as taught by Liu, to reduce the package size (para [0005]).
3. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yasukawa and Hwang, as applied to claim 13 respectively above, and further in view of Yu et al. (PG Pub 2020/0176387; hereinafter Yu).
Regarding claim 17, refer to the figures cited above, Yasukawa and Hwang teach the metal layers 14,15,16 with the mold material 33. He does not teach a "main circuit board, wherein the package substrate is coupled to the main circuit board and the metal layers with the mold material comprise traces coupled to traces within the package substrate that are coupled to power supply lines within the main circuit board."
In the same field of endeavor, refer to Fig. 23, Yu teaches an integrated circuit package comprising: a main circuit board 302, wherein a package substrate 122 is coupled to the main circuit board and metal layers 116 with a mold material 120 comprise traces 110 coupled to traces 130 within the package substrate (See Fig. 23) that are coupled to power supply lines 138B within the main circuit board (see Fig. 22).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a main circuit board and package substrate interconnection, as taught by Yu, to provide a connection between power and ground to the device.
4. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Yasukawa and Hwang, as applied to claim 13 respectively above, and further in view of Zhang et al. (PG Pub 2020/01212020; hereinafter Zhang).
Regarding claim 23, refer to the cited figures above, the combination of Yasukawa and Hwang teach the metal layers14-16 with the mold material 31-36 comprise traces 14,16 coupling the first integrated circuit die 22 and the second integrated circuit die 21 (see Fig. 31).
In the same field of endeavor, refer to Fig. 4, Zhang teaches a semiconductor device 100 comprising: a power supply (not shown; para [0021]) coupling a first integrated circuit die 114-1 and a second integrated circuit die 114-2 to the power supply (para [0021); see Fig. 4).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a power supply, as taught by Lin in view of Lao, in the device of Lin, for the purpose of providing power to the device.
Allowable Subject Matter
5. Claims 4-5, 11, 16, 18, 22 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 4, the one or more passive electrical components includes a radio frequency (RF) shield surrounding the second integrated circuit die, the RF shield comprising: a set of metal pillars within the mold material and surrounding the second integrated circuit die; and a set of traces defined in a layer of the one or more metal layers, the set of traces arranged in a grid pattern and coupled to the metal pillars of the set of metal pillars.
Claim 5 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 5, the one or more passive electrical components includes a radio frequency (RF) shield surrounding the second integrated circuit die, the RF shield comprising: a set of metal pillars within the mold material and surrounding the second integrated circuit die; and a plane defined in a layer of the one or more metal layers and coupled to the metal pillars of the set of metal pillars.
Claim 11 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 11, second integrated circuit die comprises die-to-die communication circuitry coupling the first integrated circuit die and the third integrated circuit die.
Claim 16 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 16, the one or more passive electrical components includes a radio frequency (RF) shield surrounding the second integrated circuit die, the RF shield comprising: a set of metal pillars within the mold material and surrounding the second integrated circuit die; and a plane defined in a layer of the one or more metal layers and coupled to the metal pillars of the set of metal pillars.
Claim 18 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 18, a main circuit board, wherein the package substrate is coupled to the main circuit board and the metal layers with the mold material comprise a first layer and a second layer, a portion of the first layer coupled to a voltage supply plane of the main circuit board and a portion of the second layer coupled to a ground plane of the main circuit board.
Claim 22 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 22, the one or more passive electrical components includes a radio frequency (RF) shield surrounding the second integrated circuit die, the RF shield comprising: a set of metal pillars within the mold material and surrounding the second integrated circuit die; and a set of traces defined in a layer of the one or more metal layers, the set of traces arranged in a grid pattern and coupled to the metal pillars of the set of metal pillars.
Claim 24 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 24, the metal layers with the mold material comprise a first layer and a second layer, a portion of the first layer coupled to a voltage supply plane of a main circuit board of the computing system and a portion of the second layer coupled to a ground plane of the main circuit board of the computing system.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817