Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over MOHAMMED (Pub. No.: US 2014/0332981) in view of Sarah et al. (Highly conductive …… Molecular Layer Deposition) (hereinafter Sarah) filed in the IDS on 03/23/2022.
Re claim 1, MOHAMMED, FIG. 1A teaches a microelectronic structure, comprising:
a core substrate including one of a glass material or an organic material (20, ¶ [0078]), and defining a plurality of trenches therein;
electrically conductive vias (40, [0064]) extending within the trenches, the vias to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate, individual ones of the vias including:
a trench liner (43, [0063]) adjacent walls of a corresponding one of the plurality of trenches; and
a metal structure (41/42) on the trench liner (43).
MOHAMMED fails to teach the trench liner including an electrically conductive polymer material having double carbon bonds.
Sarah teaches the trench liner including an electrically conductive polymer material having double carbon bonds (“Highly Conductive and Conformal Poly(3,4-ethylenedioxythiophene) (PEDOT) Thin Films” and page 3 right column).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of producing highly as conformal coatings over high aspect ratio structures as taught by Sarah, ABSTRACT.
Claim(s) 1-19 and 26-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (Patent No.: US 9991244) in view of Sarah et al. (Highly conductive …… Molecular Layer Deposition) (hereinafter Sarah) filed in the IDS on 03/23/2022.
Re claim 1, Lin, FIG. 2D teaches a microelectronic structure, comprising:
a core substrate including one of a glass material or an organic material (104/107/126/146, col. 2, lines 34-45), and defining a plurality of trenches therein;
electrically conductive vias (400) extending within the trenches, the vias to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate, individual ones of the vias including:
a trench liner (420) adjacent walls of a corresponding one of the plurality of trenches; and
a metal structure (430) on the trench liner (420).
Re claim 10, Lin, FIG. 2D teaches a semiconductor package including:
a microelectronic structure, comprising:
a core substrate (04/107/126/146) including one of a glass material or an organic material, and defining a plurality of trenches therein;
electrically conductive vias (400) extending within the trenches, the vias to provide electrical coupling through the core substrate to semiconductor packages (200’) to be attached to the core substrate, individual ones of the vias including:
a trench liner (420) adjacent walls of a corresponding one of the plurality of trenches; and
a metal structure (430) on the trench liner; and microelectronic assemblies disposed on respective top and bottom surface of the core substrate and including dies (transistors formed on the bottom) electrically coupled to corresponding ones of the vias.
Re claim 17, Lin, FIG. 2D teaches an integrated circuit (IC) device assembly including:
a printed circuit board (204); and
a plurality of integrated circuit (200’) components coupled to the printed circuit board (500), individual ones of the integrated circuit components including one or more semiconductor packages, individual ones of the semiconductor packages including:
a microelectronic structure, comprising:
a core substrate including one of a glass material or an organic material (104), and defining a plurality of trenches therein;
electrically conductive vias (400) extending within the trenches, the vias to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate, individual ones of the vias including:
a trench liner (420) adjacent walls of a corresponding one of the plurality of trenches; and
a metal structure (430) on the trench liner; and microelectronic assemblies disposed on respective top and bottom surface of the core substrate and including dies (transistors formed on the bottom) electrically coupled to corresponding ones of the vias.
In re claims 1, 10 and 17, Lin fails to teach the trench liner including an electrically conductive polymer material having double carbon bonds.
Sarah teaches the trench liner including an electrically conductive polymer material having double carbon bonds (“Highly Conductive and Conformal Poly(3,4-ethylenedioxythiophene) (PEDOT) Thin Films”, page 1, left column).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of producing highly as conformal coatings over high aspect ratio structures as taught by Sarah, ABSTRACT.
Re claim 2/11/18, in the combination, Lin, FIG. 2D teaches the microelectronic structure of claim 1/10/17, wherein at least some of the vias are through vias (400) extending across a thickness of the core substrate (104).
Re claim 3/12/19, in the combination, Sarah teaches the microelectronic structure of claim 1/10/17, wherein the polymer material includes single carbon bonds alternating with the double carbon bonds (page 1, left column).
Re claim 4/13/28, in the combination, Sarah teaches the microelectronic structure of claim 1/10/17, wherein the polymer material has a conjugated backbone (page 1, left column).
Re claim 5/14/29, in the combination, Sarah teaches the microelectronic structure of claim 1/10/17, wherein the polymer material includes conjugated pi bonds (page 1, left column).
Re claim 6/15/30, in the combination, Sarah teaches the microelectronic structure of claim 1/10/17, wherein the polymer material further includes at least one of nitrogen, oxygen, sulfur or hydrogen (page 2).
Re claim 7/16, in the combination, Sarah teaches the microelectronic structure of claim 1/10, wherein the polymer material is based on one or more monomers including at least one of: 3,4-Ethylenedioxythiophene (EDOT), Thiophene, 3,4-Ethylenedithiathiophene (EDTT), Aniline, Pyrrole,Selenophene, 3,4-Dimethoxythiophene (DMOT), 3-Thiophene acetic acid (TAA), 3- Thiophene ethanol (3TE), 1,3-Dihydroisothianaphthene (DHITN), Anthracene, Biphenyl,3,4-Dimethyl thiophene (DMT), 3-Methyl thiophene (MT), 3,4-Propylene dioxythiophene (ProDOT), 3,4-(2,2-Dimethylpropylenedioxy)thiophene (DMProDOT),2,2'-Bithiophene (BiT)3,2':5',3"-Terthiophene (TerT), Thieno[3,2-b]thiophene (TT) (ABSTRACT).
Re claim 8, in the combination, Lin, FIG. 2A teaches the microelectronic structure of claim 1, wherein the metal structure includes one or more layers including copper (430, col. 3, lines 13-20).
Re claim 9, in the combination, Lin, FIG. 2A teaches the microelectronic structure of claim 1, wherein, for individual ones of at least some of the electrically conductive vias (400), the metal structure fills openings defined by the trench liner (420).
Re claim 26, in the combination, Lin, FIG. 2A teaches the semiconductor package of claim 10, wherein the metal structure includes one or more layers including copper (430, col. 3, lines 15-20).
Re claim 27, in the combination, Lin, FIG. 2A teaches the semiconductor package of claim 10, wherein, for individual ones of at least some of the electrically conductive vias (430), the metal structure fills openings defined by the trench liner (420).
Response to Arguments
Applicant's arguments filed 01/12/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument:
“1. There is no reasoned motivation or reasonable expectation of success to replace Mohammed's metallic low-stress liner with Sarah's conjugated polymer films:
The Office Action appears to propose using Sarah's conductive polymer (e.g., PEDOT) in place of, or in addition to, Mohammed's first metal layer and/or barrier metal layer to obtain a polymer-containing trench liner for the via in Mohammed. Applicant respectfully submits that a person of ordinary skill in the art would not have been motivated to make that substitution, as such a substitution would not have had a reasonable expectation of success.
Mohammed's core concept is to use a stiff first metal layer surrounding a more ductile second metal region, with the first layer's Young's modulus and thickness tuned such that the via's effective CTE is significantly reduced relative to the second metal's CTE, thereby reducing stress during thermal cycling. See e.g., Mohammed at 19 and 10. Replacing the stiff first metal/barrier metal stack with a relatively pliable conductive polymer (as in Sarah) would directly undermine this stress-engineering strategy.
Sarah is concerned with the synthesis and electrical performance of thin films of the intrinsically conductive polymer PEDOT for use in organic electronic applications such as organic photovoltaics, OLEDs, and capacitor electrodes, and demonstrates high conductivity and conformal coverage over high-aspect-ratio silica fibers (Sarah, Abstract; pp. 3471-3472, Fig. 1(d)). The properties characterized in Sarah are electrical conductivity, film thickness dependence, crystalline texture, and compositional uniformity.
Sarah is directed to highly conductive thin films of the conjugated polymer poly(3,4-ethylenedioxythiophene) (PEDOT) deposited via oxidative molecular layer deposition using MoCls and EDOT precursors, for use in organic electronic devices such as organic photovoltaics, OLEDs, and capacitor electrodes. Sarah emphasizes the electrical conductivity, crystalline texture, and conformal coating capability of PEDOT films on planar fused quartz and high-aspect-ratio silica fibers, reporting conductivities routinely above 1000 Scm-' and as high as 3000 S cm-'. However, Sarah does not disclose or discuss the stiffness, Young's modulus, elastic modulus, creep behavior, viscoelastic response, or coefficient of thermal expansion (CTE) of the PEDOT films, nor does Sarah address stress-engineered interconnects, CTE-matched via stacks, diffusion-barrier performance in copper-filled through-substrate vias, or electromigration reliability in semiconductor or glass interconnects.
By looking at both Mohammed and Sarah, a person of ordinary skill in the art would readily understand that PEDOT, as a conjugated organic polymer, has mechanical and thermal properties (including stiffness, modulus, viscoelastic behavior, and CTE) that are fundamentally different from the high-modulus refractory and barrier metals specified by Mohammed for the first metal layer and barrier layers. Mohammed's core teaching is that the first metal layer must be deliberately selected for its stiffness and mechanical properties-specifically, a Young's modulus at least 50% greater than that of the copper or aluminum fill, with thickness tuned relative to via diameter to tailor the via's effective CTE. The materials Mohammed identifies for this role-alpha-tantalum, tungsten, nickel, molybdenum, titanium, and their nitrides-are all characterized by high stiffness, high melting point, strong metallic or covalent bonding, and predictable elastic behavior under thermal cycling and applied stress. These properties are precisely what allow Mohammed to achieve his stated goal: to engineer the via's effective CTE to be less than 80% of the second metal region's CTE, thereby minimizing stress-induced failures during repeated thermal cycling.
The Examiner has not satisfied the burden of showing obviousness by demonstrating that the PEDOT polymer disclosed in Sarah could in fact be used to take the place of the stiff metallic first layer envisaged by Mohammed. Sarah is silent on the stiffness or modulus of PEDOT, and provides no data, teaching, or suggestion that PEDOT films could be used in semiconductor fabrication processes, or that they possess the mechanical properties required to perform the stress-constraining, CTE-matching function that Mohammed explicitly and emphatically relies upon…….”, pages 11-13.
The Examiner respectfully submits that Mohammed suggests that “the layer 43 can include nickel, an alloy including nickel, titanium nitride, tantalum nitride, and tantalum silicon nitride.”, ¶ [0063] which is an alloy conductive layer and Sarah discloses PEDOT's chemical stability, visible transparency, and high electrical conductivity make it useful for electronic applications including organic photovoltaics (OPVs), organic light emitting diodes (OLEDs), and electrolytic capacitor electrodes.”, page 1, first paragraph, therefore, One would be motivated to make such a change to generate the claimed invention with a reasonable expectation of success and yield predictable results. Furthermore, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, it would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of producing highly as conformal coatings over high aspect ratio structures as taught by Sarah, ABSTRACT.
In response to Applicant’s argument:
“2. Mohammad's substrate is not a "core substrate":
Independent claim 1 recites a core substrate that includes one of a glass material or an organic material and defines a plurality of trenches, electrically conductive vias extend within those trenches to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate. The specification describes a packaging-core architecture, where a glass or organic core substrate 104 with high-aspect-ratio core trenches 106 and vias 108 provides vertical signal paths between microelectronic assemblies on opposite sides of the core, via upper and lower redistribution layers. The core substrate is defined in the Application as a non-conductive support (therefore, passive) for semiconductor packages, not an active semiconductor wafer. See Application at 22.
Mohammed's substrate 20 can indeed be semiconductor, ceramic, or glass, but Mohammed describes vias 40 that connect front-side conductive pads 25 to rear-side contacts 50 in a component 10 or 10a, where in embodiments the substrate includes active semiconductor devices in region 19 beneath the front surface. The focus in Mohammed is on chip- or die-level via structures and stress-engineered via stacks that optimize CTE and stress performance within a single substrate, not on a glass or organic packaging core that routes signals between separate semiconductor packages attached to the core's opposing faces. Even if a skilled artisan were to (impermissibly) substitute Sarah's conductive polymer for Mohammed's carefully chosen metal liners and barriers, the combined teachings still would not provide a glass or organic core substrate serving as a package core with top and bottom microelectronic assemblies, nor vias whose function is specifically to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate (as opposed to merely connecting pads on the same die or substrate). These package-level architectural features are described and enabled in the present application, but are not suggested in Mohammed or Sarah.”,
The Examiner respectfully submits that claim language requires “a core substrate including one of a glass material or an organic material”, therefore, Mohammed clearly reads on: “the substrate 20, ….., the substrate consists essentially of dielectric material (e.g., glass or ceramic)”, paragraph [0067]).
In response to Applicant’s argument:
“1. There is no reasoned motivation or reasonable expectation of success to replace
Lin's insulating liner and metallic barriers with Sarah's conjugated polymer films.
The Office Action appears to propose using Sarah's conductive polymer (e.g., PEDOT) in place of, or in addition to, Lin's insulating liner 410 and/or metallic diffusion barrier layer 420 to obtain a polymer-containing trench liner for the via in Lin. Applicant respectfully submits that a person of ordinary skill in the art would not have been motivated to make that substitution, as such a substitution would not have had a reasonable expectation of success.
Lin is directed to methods for forming hybrid bonding with through-substrate vias (TSVs) in semiconductor wafers for 3D integrated circuits (3DICs). Semiconductor substrate 104 contains device regions 103 (transistors and other active devices) and through-substrate vias 400. TSV 400 in Lin includes liner 410, which Lin identifies as an insulating material (e.g., oxides or nitrides such as silicon oxide or silicon nitride), diffusion barrier layer 420, which is a metallic diffusion barrier (e.g., Ta, TaN, Ti, TiN, CoW), and conductive material 430, which is a metal fill (e.g., Cu, Cu alloy, Al, Al alloy). Liner 410 is explicitly taught as an electrical isolation layer between the conductive TSV 400 and the active semiconductor substrate 104 and device regions 103, and barrier 420 is taught to prevent diffusion of Cu or Al into the substrate and surrounding structures. The via and hybrid bonding structures are integrated into the wafer-level metallization and bonding stacks for 3D chip stacking, not into a glass or organic package core as in the present application.
Sarah, in contrast, is concerned with the synthesis and electrical performance of thin films of the intrinsically conductive polymer PEDOT for use in organic electronic applications such as organic photovoltaics, OLEDs, and capacitor electrodes, and demonstrates high conductivity and conformal coverage over high-aspect-ratio silica fibers (Sarah, Abstract; pp. 3471-3472, Fig. 1(d)). The properties characterized in Sarah are electrical conductivity, film thickness dependence, crystalline texture, and compositional uniformity. Sarah is directed to highly conductive thin films of the conjugated polymer poly(3,4-ethylenedioxythiophene) (PEDOT) deposited via oxidative molecular layer deposition using MoCls and EDOT precursors, for use in organic electronic devices such as organic photovoltaics, OLEDs, and capacitor electrodes. Sarah emphasizes the electrical conductivity, crystalline texture, and conformal coating capability of PEDOT films on planar fused quartz and high-aspect-ratio silica fibers, reporting conductivities routinely above 1000 S/cm and as high as 3000 S/cm.
However, Sarah does not disclose or discuss TSV liners in active semiconductor wafers, does not discuss replacement of oxide/nitride isolation liners (like Lin's 410) with conductive polymers, does not address replacement of conventional metal diffusion barriers (like Lin's 420) with conductive polymers, and does not address long-term isolation, diffusion-barrier performance, or electromigration reliability in copper-filled TSVs.
By looking at both Lin and Sarah, a person of ordinary skill in the art would readily understand that the proposed substitution would disrupt Lin's isolation and barrier scheme and is not suggested by the references. Lin's core teaching is that liner 410 must be electrically insulating to isolate the conductive via from the surrounding semiconductor and active device regions, and that barrier 420 must be a robust metallic diffusion barrier to prevent Cu or Al diffusion into the substrate. The materials Lin identifies for these roles-silicon oxide, silicon nitride, and metallic barriers such as Ta, TaN, Ti, TiN, and CoW-are all characterized by well-understood insulating or barrier properties, high thermal stability, and predictable behavior”, pages 15-17.
The Examiner respectfully submits that Lin teaches a liner including 420 wherein the “Diffusion Barrier layer 420 is made of Ta, TaN, Ti, TiN, or CoW. In some embodiments”, which is an alloy conductive layer and Sarah discloses PEDOT's chemical stability, visible transparency, and high electrical conductivity make it useful for electronic applications including organic photovoltaics (OPVs), organic light emitting diodes (OLEDs), and electrolytic capacitor electrodes.”, page 1, first paragraph, therefore, One would be motivated to make such a change to generate the claimed invention with a reasonable expectation of success and yield predictable results. Furthermore, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, it would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of producing highly as conformal coatings over high aspect ratio structures as taught by Sarah, ABSTRACT.
In response to Applicant’s argument:
“2. Lin's substrate is not a "core substrate."
Independent claim 1 recites a core substrate that includes one of a glass material or an organic material and defines a plurality of trenches, electrically conductive vias extending within those trenches "to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate." See Application at 82. The specification further explains that a "core substrate" or "core" is "any supportive layer that is not electrically conductive, and that is to support microelectronic components thereon" (Id. at 22). The present application describes a packaging-core architecture, where a glass or organic core substrate 104 with high-aspect-ratio core trenches 106 and vias 108 provides vertical signal paths between microelectronic assemblies on opposite sides of the core, via upper and lower redistribution layers. The core substrate is a passive, non-conductive support (glass or organic HDP) for semiconductor packages, not an active semiconductor wafer. Id.
Lin's substrate 104, by contrast, is explicitly an active semiconductor wafer containing device regions 103 and front-end-of-line structures. The focus in Lin is on TSVs 400 that interconnect that active wafer into a 3DIC stack through hybrid bonding. Lin's TSVs are used to interconnect active circuitry within a 3D chip stack, not to provide electrical coupling through a passive, non-conductive core substrate to separate semiconductor packages to be attached to the core's opposing faces. Lin does not disclose or suggest a "core substrate" as defined in the present specification-i.e., a non-conductive supportive layer whose role is to support microelectronic components thereon-and does not describe a glass or organic core that routes signals between separate semiconductor packages mounted on its top and bottom surfaces.
Even if a skilled artisan were to (impermissibly) substitute Sarah's conductive polymer for Lin's insulating liner 410 and metallic barrier 420, the combined teachings still would not provide a glass or organic core substrate serving as a package core with top and bottom microelectronic assemblies, nor vias whose function is specifically to provide electrical coupling through the core substrate to semiconductor packages to be attached to the core substrate (as opposed to merely connecting active circuitry within a single semiconductor die). These package-level architectural features are described and enabled in the present application, but are not suggested in Lin or Sarah.”, pages 18-19.
The Examiner respectfully submits that claim language requires “a core substrate including one of a glass material or an organic material”, therefore, Lin reads on: a core substrate (104+107+146 wherein “146 is benzocyclobutene (BCB) polymer, polyimide (PI), or polybenzoxazole (PBO).”, col. 4, lines 24-28, and those are the organic material) including one of a glass material or an organic material
For the above reasons, it is believed that the rejections should be sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893