DETAILED ACTION
This Office Action is in response to the Amendment/Arguments filed 19 September 2025. Claims 13-12, 23-25 are pending in this application. Claim 22 has been cancelled.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 13, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over of Yuan (US 2023/0200136 A1) (newly cited) in view of Kim et. al (KR 2006/0104146 A) (previously cited) and Choi et. al (US 2021/0013280 A1) (previously cited).
Regarding Claim 13, Yuan discloses (as shown in Fig. 9, 20)
A method of manufacturing a display apparatus ([0005] The present disclosure provides an array substrate and a manufacturing method of an array substrate and a display panel and device.), the method comprising:
forming a first semiconductor layer ([0039] the switch transistor 12 includes a second active layer 121…[0042] the second transistor 222 includes a second active layer 2221) on a substrate ([0042] base substrate 21); ([0069] In step S120, the first active layer and the second active layer are manufactured on one side of the base substrate.)
forming a first gate insulating layer ([0072] first-type inorganic layer 23) to cover the first semiconductor layer (2221); [0071] In step S130, the first-type inorganic layer is manufactured on the side of the first active layer facing away from the base substrate.
forming, on the first gate insulating layer (23), a first conductive layer ([0077] Further, as shown in FIG. 15, when the second-type inorganic layer is manufactured, the first gate electrode 2212 of the first transistor 221, the second gate electrode 2224 of the second transistor 222 and a capacitor structure 224 may be manufactured simultaneously.) including a gate wire including a switching gate electrode([0077] the second gate electrode 2224); (See Fig. 9, showing the first gate electrode 2212 of the first transistor 221, the second gate electrode 2224 of the second transistor 222 and a capacitor structure 224 formed on the first-type inorganic layer 23)
forming a second gate insulating layer ([0054] a second insulating layer 32… the second insulating layer 32 and the third insulating layer 33 may be the above-mentioned second-type inorganic layer 24) to cover the first conductive layer (2212, 2224); (See Fig. 9, showing the second-insulating layer 32 formed on the first gate electrode 2212 and second gate electrode 2224)
forming, on the second gate insulating layer (32), a second conductive layer including an upper capacitor electrode ([0054] second capacitor plate 2242); (See Fig. 9, showing the second capacitor plate 2224 formed on the second insulating layer 32)
forming a first interlayer insulating layer ([0054] third insulating layer 33) to cover the second conductive layer (2242); (See Fig. 9, showing the third insulating layer 33 covering the second capacitor plate 2242)
forming a second semiconductor layer ([0056] the third active layer 2231) on the first interlayer insulating layer (33); ([0056] the third insulating layer 33 disposed between the second capacitor plate 2242 and the third active layer 2231)
forming a third gate insulating layer ([0058] where the third-type inorganic layer 26 includes a plurality of third inorganic layers) to cover the second semiconductor layer (2231) and overlap the first semiconductor layer (2221) and the gate wire (2224) of the first conductive layer (2212,2224); (See Fig. 9, showing the middle layer of the third-type inorganic layer 26 covering the third active layer 2231 and extends to overlap the second active area 2221 and the second gate electrode 2224)
forming a second interlayer insulating layer ([0058] where the third-type inorganic layer 26 includes a plurality of third inorganic layers) to cover the third gate insulating layer (middle layer of 26); (See Fig. 9, showing the top layer of the third-type inorganic layer 26 covering the middle layer of the third-type inorganic layer 26)
forming a contact hole ([0060] third via hole 28) in the first gate insulating layer (23), the second gate insulating layer (32), the first interlayer insulating layer (33), the third gate insulating layer (middle layer of 26), and the second interlayer insulating layer (top layer of 26) ([0061] The second via hole 27 and the third via hole 28 both penetrate through the first-type inorganic layer 23, the second-type inorganic layer 24 and the third-type inorganic layer 26)
and forming, on the second interlayer insulating layer (23), a first connection electrode layer ([0050] a first source electrode 2213 and a first drain electrode 2214, … a second source electrode 2222 and a second drain electrode 2223) including a first connection electrode (2222) in contact with the first semiconductor layer (2221) via the contact hole (28) ([0050] the second source electrode 2222 and the second drain electrode 2223 are respectively electrically connected to the second active layer 2221 through a second source-drain electrode via hole 28 (a third via hole 28)),
wherein the switching gate electrode (2224) is part of a switching transistor ([0046] the second transistor 222 may be a switch transistor) electrically connected to a data line ([0046] the switch transistor is a transistor whose gate connected to a scanning signal or a light-emitting control signal),
and wherein the upper capacitor electrode (2242) does not overlap the gate wire (2224). (See Figure 9, showing that the second capacitor plate 2242 does not overlap the second gate electrode 2224)
However, Yuan fails to disclose:
forming an etch stop layer to cover the first conductive layer (2212, 2224);
forming a second gate insulating layer (32) to cover the etch stop layer;
forming a first temporary contact hole directly contacting and extending through the second gate insulating layer (32), the first interlayer insulating layer (33), the third gate insulating layer (middle layer of 26), and the second interlayer insulating layer (top layer of 26);
forming a second temporary contact hole by removing a portion of the etch stop layer exposed by the first temporary contact hole; forming a contact hole in the first gate insulating layer (23), the etch stop layer, the second gate insulating layer (32), the first interlayer insulating layer (33), the third gate insulating layer (middle layer of 26), and the second interlayer insulating layer (top layer of 26) by removing a portion of the first gate insulating (23) layer exposed by the second temporary contact hole;
wherein the switching gate electrode is part of a switching transistor having a first end electrically connected to a data line and a second end electrically connected to a driving transistor and a control transistor,
Kim discloses (Figs. 4a-4d) forming an etch stop layer ([0046] an etching stop layer (190)) to cover the first conductive layer ([0045] the gate electrode (112)); (Thereafter, Si N x, which is an inorganic material, is deposited on the front surface including the gate electrode (112) by a chemical vapor deposition method to form an etching stop layer (190))
forming a second gate insulating layer (interlayer insulating film 116) to cover the etch stop layer (190); (See Fig. 4a)
forming a first temporary contact hole ([0047] etch the interlayer insulating layer 116 to form a contact hole 179 through which the etch stop layer 190 is exposed) directly contacting and extending through the second gate insulating layer (17), the first interlayer insulating layer (19), the third gate insulating layer (21), and the second interlayer insulating layer (23); ([0113] The first through hole and the second through hole respectively penetrate through the interlayer dielectric layer, the third gate insulating layer, the second buffer layer, the second gate insulating layer and the first buffer layer.)
forming a second temporary contact hole (contact hole 179 in Fig. 4c) by removing a portion of the etch stop layer (190) exposed by the first temporary contact hole contact hole 179 in Fig. 4b); ([0049] the gate insulating layer 114 is exposed by dry etching the etching top layer 190 exposed between the contact holes 179)
forming a contact hole (contact hole 179 in Fig. 4d) in the first gate insulating layer ([0049] the gate insulating layer 114), the etch stop layer (190), and layers the first temporary contact hole (Fig. 4b: 179) passes through (the second gate insulating layer 116) by removing a portion of the first gate insulating layer (114) exposed by the second temporary contact hole (contact hole 179 in Fig. 4c). ([0051] the gate insulating layer 114 exposed between the contact holes 179 is wet etched to expose the source/drain regions 115a and 115b)
Kim teaches that by using an etch-stop layer, the gate insulating film and interlayer insulating film can be prevented from being over-etched or under-etched due to the non-uniform nature of the insulating film or a non-uniform etch. This improves the electrical characteristics by preventing defects caused by etching unevenness. ([0062] an etch stop layer is further provided between the gate insulating film and the interlayer insulating film to prevent the gate insulating film and the interlayer insulating film from being under-etched or over-etched due to non-uniform thickness of the insulating film and non-uniform etch. [0063] Therefore, it is possible to improve the electrical characteristics of the device by preventing defects caused by etching unevenness.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an etch stop layer to separately etch the upper insulating layer and the first gate insulating layer in order to improve the electrical characteristics of the device.
Since Kim teaches forming the first temporary hole (179) exposes the top of the etch stop layer, and the contact hole of Yuan extends through the first gate insulating layer (14) the second gate insulating layer (17), the first interlayer insulating layer (19), the third gate insulating layer (21), and the second interlayer insulating layer (23).
However, neither Yuan nor Kim discloses wherein the switching gate electrode (2224) is part of a switching transistor having a first end electrically connected to a data line and a second end electrically connected to a driving transistor and a control transistor.
Choi discloses (as shown in Figs. 2 and 23) wherein the switching transistor ([0075] The second transistor T2 and the seventh transistor T7 may be switching transistors) is a polysilicon transistor. ([0064] For example, the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include (or be made of) a crystallized silicon)
and wherein the switching gate electrode ([0100] The first semiconductor layer 105 may include a channel region disposed to overlap with a second-first gate electrode (or a second bottom gate electrode) 123 on (e.g., above) the channel region) is part of a switching transistor ([0101] The first semiconductor layer 105 may be a semiconductor layer of any of the above-described first transistor T1, second transistor T2, fifth transistor T5, sixth transistor T6, and/or seventh transistor T7) ([0075] The second transistor T2 and the seventh transistor T7 may be switching transistors)
having a first end electrically connected to a data line ([0068] The first electrode of the second transistor T2 is connected to a data line DLm) and a second end electrically connected to a driving transistor and a control transistor. ([0068] The second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1 and is connected to the first power voltage supply line VDDL via the fifth transistor T5.)
It would have been obvious before the effective filing date of the application to combine the teachings of Yuan and Choi. Yuan teaches a display device with switching and driving transistors ([0046] Generally, in a pixel circuit, the switch transistor is a transistor whose gate connected to a scanning signal or a light-emitting control signal, and a transistor other than the switch transistor in the pixel circuit is a drive transistor) Yuan further teaches that the pixel circuit may include either 2 or 7 transistors ([0043] By way of example, for the array substrate provided by the embodiments of the present disclosure, the pixel circuit 22 may include two transistors (2T) or seven transistors (7T).) However, Yuan does not teach the configuration of the seven-transistor pixel circuit. ([0043] The specific structure of the pixel circuit 22 is not limited in the embodiments of the present disclosure. FIG. 4 merely, by way of example, shows two transistors.)
Choi also teaches a display device made of seven transistors. ([0064] For example, the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include (or be made of) a crystallized silicon, and the semiconductor layers of the third transistor T3 and the fourth transistor T4 may include (or be made of) an oxide.) It would have been obvious to arrange the transistors of Yuan in the arrangement of the seven transistor circuit of Choi in order to form the seven transistor pixel circuit mentioned but not disclosed in Yuan.
Regarding Claim 23, Yuan further discloses (as shown in Fig. 9) herein the upper capacitor electrode (2242) overlaps a first gate electrode ([0055] the first gate electrode 2212) of a driving transistor ([0046] the first transistor 221 may be a drive transistor). ([0055] the first capacitor plate 2241 and the first gate electrode 2212 of the first transistor 221 may be disposed in a same layer, and the second capacitor plate 2242 is disposed on one side of the first electrode gate 2212 facing away from the base substrate 21.)
Claims 14-18, 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan in view of Choi and Kim as applied to Claim 13 above, and further in view of Lee et. al. (KR 20080040885 A) (previously cited).
Regarding Claim 14, Yuan in view of Choi and Kim discloses all the limitations of Claim 13;
However, Kim fails to disclose wherein the forming of the first temporary contact hole includes using a gas including fluorine, and the forming of the second temporary contact hole includes oxygen plasma treatment.
Kim and Lee are both directed to multistep etching processes using an etch stop layer. Lee discloses wherein the forming of the first temporary contact hole ([0039] the second and third insulating layers (38, 39) etched to form the opening portion 41) includes using a gas including fluorine ([0030] the gas etching the insulating layer is for example, C4F6or C4F8), and the forming of the second temporary contact hole ([0031] Next, the etch stop layer 37 under the open portion 41 is etched) includes oxygen plasma treatment ([0034] In a case in which the etching stop layer 37 is a nitride layer-based column, the etching stop layer 37 is performed using a mixed gas of a fluorine-based gas and an oxygen gas in an ICP (inductively Coupled Plasma) or a TCP (Transformer Coupled Plasma)…[0034] When the etch stop film 37 is amorphous carbon, it is performed using an oxygen-based gas.)
Kim does not disclose the type of etching processes used in etching the insulating layers and the etch-stop layer. Lee teaches types of etchants with etch selectivity between inorganic insulating layers and an organic etch stop layer. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings Zhao in view of Kim with the types of etching in Lee in order to get the predictable result of separately etching the insulating and etch stop layers.
Regarding Claim 15, Yuan further discloses that the first gate insulating layer (23) is an inorganic film. ([0042] first-type inorganic layer 23)
However, Yuan in view of Choi and Kim does not disclose that the portion of the first gate insulating layer (111) is removed using a process that includes using a gas that includes fluorine.
Lee further discloses that inorganic insulating films can be etched using a Fluorine based gas ([0030] only the second and third insulating layers 38 and 39 of the oxide layer query are selectively etched using a gas having a high selectivity with respect to the etch stop layer 37. the gas etching the insulating layer is for example, C4F6or C4F8… [0032] is a nitride layer-based layer, etching is performed using fluorine-based gas) While Kim teaches that a wet etch is used to etch the first gate insulation layer (125), One having ordinary skill in the art would know that a dry etching process can be substituted for a wet etching process. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute the dry etching process of Lee for the wet etching process of Zhao in view of Choi and Kim to get the predictable result of selectively etching the first gate insulation layer (125).
Regarding Claim 16, Kim further discloses wherein a material (Claim 3: the etching stop layer is formed of a silicon nitride material) used in the forming of the etch stop layer (190) is different from a material (Claim 4: The inter-layer insulating film is SiO2, Claim 5: The gate insulating layer is SiO2) used in the forming of the first gate insulating layer an interlayer layer.
However, Yuan in view of Choi and Kim fails to disclose wherein a material used in the forming of the etch stop layer (190) is different from a material used in the forming of the second gate insulating layer (32), the forming of the first interlayer insulating layer (33), the forming of the third gate insulating layer (middle layer of 26), and the forming of the second interlayer insulating layer (top layer of 26)
Lee teaches forming the etch stop layer of a material with a different etching selectivity than the insulating layers ([0024] The etch stop film 37…is formed of a material having an etching selectivity with a subsequent interlayer insulating layer). Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to have the etch stop layer (190) formed of a different material than the first gate insulating layer (104), second gate insulating layer (106), first interlayer layer (110), third gate insulating layer (113), and second interlayer layer (115) so that the etch stop layer would have a different etch selectivity.
Regarding Claim 17, Yuan further discloses (as shown in Fig. 9) each of the forming of the first gate insulating layer (23), the forming of the second gate insulating layer (32), the forming of the first interlayer insulating layer (33), the forming of the third gate insulating layer (middle layer of 26), and the forming of the second interlayer insulating layer (top layer of 26) includes forming an inorganic insulating layer. ([0042] first-type inorganic layer 23…[0056] the second insulating layer 32 and the third insulating layer 33 may be the above-mentioned second-type inorganic layer 24…[0058] the third-type inorganic layer 26 includes a plurality of third inorganic layers)
Yuan further discloses that the inorganic material can include silicon nitride (At least one of the first insulating layer 31, the second insulating layer 32 and the third insulating layer 33 is a silicon nitride layer)
However, Yuan in view of Choi and Kim fails to disclose the forming of the etch stop layer (190) includes forming an amorphous carbon layer;
Lee discloses (See Fig. 2b, 2c) the forming of the etch stop layer ([0032] etch stop layer 37) includes forming an amorphous carbon layer ([0032] when the etch stop layer 37 is amorphous carbon).
Lee teaches forming the etch stop layer of a material with a different etching selectivity than the insulating layers ([0024] The etch stop film 37…is formed of a material having an etching selectivity with a subsequent interlayer insulating layer) Since the interlayer insulating layers in Zhao in view of Kim is inorganic, a different material with etch selectivity is needed. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute the amorphous carbon etch stop layer (37) in Lee for the SiN etch stop layer (190) in Kim in order to ensure etch selectivity with the inorganic insulating layers disclosed in Zhao in view of Choi and Kim.
Regarding Claim 18, Yuan further discloses (as shown in Fig. 9) each of the forming of the first gate insulating layer (23), the forming of the second gate insulating layer (32), the forming of the first interlayer insulating layer (33), the forming of the third gate insulating layer (middle layer of 26), and the forming of the second interlayer insulating layer (top layer of 26) includes forming an inorganic insulating layer. ([0042] first-type inorganic layer 23…[0056] the second insulating layer 32 and the third insulating layer 33 may be the above-mentioned second-type inorganic layer 24…[0058] the third-type inorganic layer 26 includes a plurality of third inorganic layers)
Yuan further discloses that the inorganic material can include silicon nitride (At least one of the first insulating layer 31, the second insulating layer 32 and the third insulating layer 33 is a silicon nitride layer)
Choi further discloses that the inorganic insulating layers can include silicon oxide, silicon nitride or silicon oxynitride. ([0102] For example, the first insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride...; [0106] For example, the second insulating layer 112 may include silicon oxide, silicon nitride, silicon oxynitride…; [0110] For example, the third insulating layer 113 may include silicon oxide, silicon nitride, silicon oxynitride…; [0116] For example, the fourth insulating layer 114 may include silicon oxide, silicon nitride, silicon oxynitride…)
It would have been obvious to use the inorganic insulating materials in Choi as the inorganic insulating materials in Zhao. Zhao does not disclose what materials the inorganic insulating materials are; therefore, it would be obvious to use the insulating materials of Zhao, which is a similar device.
Regarding Claim 24, Lee further discloses (as shown in Fig. 2b, 2c) the forming of the etch stop layer ([0032] etch stop layer 37) includes forming an amorphous carbon layer ([0032] when the etch stop layer 37 is amorphous carbon).
Lee teaches forming the etch stop layer of a material with a different etching selectivity than the insulating layers ([0024] The etch stop film 37…is formed of a material having an etching selectivity with a subsequent interlayer insulating layer) Since the interlayer insulating layers in Zhao in view of Kim is inorganic, a different material with etch selectivity is needed. it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute the amorphous carbon etch stop layer (37) in Lee for the SiN etch stop layer (190) in Kim in order to ensure etch selectivity with the inorganic insulating layers disclosed in Yuan in view of Choi and Kim.
Regarding Claim 25, Yuan further discloses (as shown in Fig. 9) each of the forming of the first gate insulating layer (23), the forming of the second gate insulating layer (32), the forming of the first interlayer insulating layer (33), the forming of the third gate insulating layer (middle layer of 26), and the forming of the second interlayer insulating layer (top layer of 26) includes forming an inorganic insulating layer. ([0042] first-type inorganic layer 23…[0056] the second insulating layer 32 and the third insulating layer 33 may be the above-mentioned second-type inorganic layer 24…[0058] the third-type inorganic layer 26 includes a plurality of third inorganic layers)
the second gate insulating layer (32), the first interlayer insulating layer (33), the third gate insulating layer (middle layer of 26), and the second interlayer insulating layer (top layer of 26) overlap the gate wire (2224). (See Fig. 9)
Claim 21 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Choi and Kim as applied to Claim 19 above, and further in view of Zhao et. al (US 2023/0329037 A1) (previously cited) and Park et. al (KR 20040007822 A) (previously cited)
Zhao (965) in view of Choi and Kim fails to disclose wherein the first connection electrode overlaps the switching gate electrode of the gate wire in a plan view.
Zhao (037) discloses (as shown in Fig. 4) wherein the first connection electrode ([0074] second electrode 30) overlaps the gate electrode [0056] gate electrode 15) of the gate wire in a plan view. (See Fig 4, showing second electrode 30 extending partially over the gate electrode 15)
It would have been obvious to combine the teachings of Zhao (965) and Zhao (037) in light of the teachings of Park. Park teaches that the first overlapping region Va defined as an overlapping region between the gate electrode 212 and the source electrode 216 is defined as an overlapping region between the gate electrode 212 and the drain electrode 218. It is configured to be wider than the two overlapping regions Vb, and among the parasitic capacitances in the first and second overlapping regions Va and Vb, the parasitic capacitance in the overlapping region of the gate electrode 212 and the source electrode 216. Is used as a pixel driving storage capacitance CST. ([0051]) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have an overlapping region between the gate electrode and connection electrode (source electrode) in order to use the parasitic capacitance as a pixel driving storage capacitance.
Allowable Subject Matter
Claims 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 19, Choi further discloses (as shown in Fig. 22) forming a first planarization layer ([0130] The first via layer VIA1 is disposed on the third conductive layer 150)
forming, on the first planarization layer (VIA1), a second contact hole ([0189] the sixth contact hole CNT6) exposing at least a portion of the first connection electrode ([0189] second drain electrode 157); ([0190] The sixth contact hole CNT6 may be formed to extend (e.g., pass) through the first via layer VIA1 to expose an upper surface of the second source electrode 155 or an upper surface of the second drain electrode 157.)
and forming, on the first planarization layer (VIA1), a second connection electrode layer ([0191] the pixel electrode ANO is formed on the first via layer VIA1)
However, Choi fails to disclose including a data wire connected to the first connection electrode via the contact hole defined in the first planarization layer (VIA1).
The transistor which connects to the anode is the driving transistor, and not the switching transistor. Therefore, the anode does not connect to the connection electrode of the switching transistor.
Other relevant prior art includes Zhao et. al (US 2023/0329037 A1) (previously cited) which discloses:
A method of manufacturing a display apparatus ([0089] A display panel including the display base plate described above), the method comprising:
forming a first semiconductor layer ([0102] the active layer 13 of the polysilicon transistor) on a substrate ([0102] the substrate 10); ([0102] In the step S101, … the active layer 13 of the polysilicon transistor … are sequentially formed on the substrate 10.)
forming a first gate insulating layer ([0102] the first gate insulating layer 14) to cover the first semiconductor layer (13); ([0102] In the step S101, … the active layer 13 of the polysilicon transistor, the first gate insulating layer 14, … are sequentially formed on the substrate 10.)
forming, on the first gate insulating layer (14), a first conductive layer including a gate wire including a switching gate electrode ([0102] the gate metal layer); ([0102] In the step S101, … the first gate insulating layer 14, the gate metal layer, … are sequentially formed on the substrate 10.)
forming a second gate insulating layer ([0102] the second gate insulating layer 17) to cover the first gate insulating layer (14); ([0102] In the step S101, … the first gate insulating layer 14, … the second gate insulating layer 17 … are sequentially formed on the substrate 10.)
forming, on the second gate insulating layer (17), a second conductive layer ([0102] the second gate insulating layer 17) including an upper capacitor electrode ([0102] the first electrode 18 of the storage capacitor); ([0102] In the step S101, … the second gate insulating layer 17 and the first electrode 18 of the storage capacitor as shown in FIG. 6 are sequentially formed on the substrate 10.)
forming a first interlayer insulating layer ([0106] a second buffer layer 19) to cover the second conductive layer (18); ([0106] In the step S102, a second buffer layer 19 as shown in FIG. 7 is deposited on the first electrode 18.)
forming a second semiconductor layer ([0108] active layer 20) on the first interlayer insulating layer (18); ([0108] In the step S103, the active layer 20 of the oxide transistor as shown in FIG. 8 is formed on the second buffer layer 19.)
forming a third gate insulating layer ([0110] In the step S104, the third gate insulating layer 21) to cover the second semiconductor layer (20) and overlap the first semiconductor layer (13) and the gate wire of the first conductive layer (gate metal layer); ([0110] In the step S104, the third gate insulating layer 21 and a gate electrode (i.e., top gate) 22 of the oxide transistor are formed as shown in FIG. 9. The third gate insulating layer 21 covers the active layer 20 of the oxide transistor.) (See Fig. 4, showing the third gate insulating layer 21 extends over the active layer 13 and the gate electrode 15)
forming a second interlayer insulating layer ([0112] interlayer dielectric layer 23; [0053] a second ILD layer 113) to cover the third gate insulating layer (21); ([0112] In the step S105, as shown in FIG. 10, the interlayer dielectric layer 23 covering the gate electrode of the oxide transistor)
forming a contact hole ([0112] a first through hole 24) in the first gate insulating layer (14), the second gate insulating layer (17), the first interlayer insulating layer (19), the third gate insulating layer (21), and the second interlayer insulating layer (23) ([0112] a first through hole 24, a second through hole 25 and a third through hole 26 are formed) (See Fig. 10, showing the through holes 24 and 25 pass through the first gate insulating layer (14), the second gate insulating layer (17), the first interlayer insulating layer (19), the third gate insulating layer (21), and the second interlayer insulating layer (23))
forming, on the second interlayer insulating layer (23,113), a first connection electrode layer (See Fig. 1, showing connection electrodes formed on the second ILD layer 113) including a first connection electrode in contact with the first semiconductor layer via the contact hole, (See Fig. 1)
forming a first planarization layer ([0053a first PLN layer 114) to cover the first connection electrode layer; (See Ann. Fig. 1, showing the first PLN layer 114 covering the first connection electrode layer)
forming, on the first planarization layer (114), a second contact hole exposing at least a portion of the first connection electrode; and forming, on the first planarization layer (114), a second connection electrode layer via the contact hole defined in the first planarization layer (114). (See Ann. Fig. 1, showing a second connection electrode layer passing through the first PLN layer 114 to connect to the first connection electrode layer)
However, Zhao fails to disclose wherein the switching gate electrode is part of a switching transistor having a first end electrically connected to a data line and a second end electrically connected to a driving transistor and a control transistor,
And wherein the upper capacitor electrode does not overlap the gate wire.
Instead, in Zhao, the first transistor is a driving transistor (0053] In related art, an LTPO base plate may include an LTPS driving transistor 103). Zhao discloses a switching transistor ([0053] an oxide switching transistor 105) but it is the second transistor with the second active area. Therefore, it is not in the same layers as is claimed.
Zhao further discloses forming, on the second interlayer insulating layer (113), a first connection electrode layer including a first connection electrode of the switching transistor (105) in contact with the first semiconductor layer via the contact hole,
forming a first planarization layer (114) to cover the first connection electrode layer (See Ann. Fig. 1 below);
forming, on the first planarization layer (114), a second contact hole exposing at least a portion of the first connection electrode; (See Ann. Fig. 1)
and forming, on the first planarization layer (114), a second connection electrode layer including a data wire connected to the first connection electrode via the contact hole defined in the first planarization layer (114). (See Ann. Fig. 1)
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However, it would not have been obvious to combine the second connection electrode of the switching transistor in Zhao with the switching transistor in Yuan. Zhao provides no motivation to combine the second connection layer (as shown in Ann. Fig. 1) with the display device of Yuan in view of Choi and Kim.
Since the Claim contains limitations not found in the prior art, it contains allowable subject matter.
Regarding Claim 20, Claim 20 depends form Claim 19 and contains allowable subject matter for the same reasons.
Response to Arguments
Applicant’s arguments, filed 19 September 2025, with respect to the rejection(s) of claim(s) 13 under 35 U.S.C. 103 have been fully considered and are partially persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yuan (US 2023/0200136 A1) (newly cited) in view of Kim et. al (KR 2006/0104146 A) (previously cited) and Choi et. al (US 2021/0013280 A1) (previously cited).
Applicant's arguments filed 19 September 2025 have been fully considered but they are not fully persuasive.
Regarding Claim 13, Applicant’s second argument, on page 11 of the Applicant’s Remarks, that “Kim provides an etching stop layer 190 between an interlayer insulating film 116 and a gate electrode 112 but claim 13 requires “forming an etch stop layer to cover the first conductive layer;” “forming a second gate insulating layer to cover the etch stop layer;” “forming, on the second gate insulating layer, a second conductive layer including an upper capacitor electrode;” and “forming a first interlayer insulating layer to cover the second conductive layer;”” is not persuasive. Applicant’s argument is essentially that Kim lacks the specific arrangement of layers claimed. Examiner agrees that Kim lacks these layers; however, Examiner does not rely on Kim to show these layers. Each of these layers is found in Zhao (now shown in Yuan). Kim is used to shown that it would be obvious to include an etch stop layer in order to prevent over- and under-etching, thereby reducing defects and improving electrical characteristics. ([0062] an etch stop layer is further provided between the gate insulating film and the interlayer insulating film to prevent the gate insulating film and the interlayer insulating film from being under-etched or over-etched due to non-uniform thickness of the insulating film and non-uniform etch. [0063] Therefore, it is possible to improve the electrical characteristics of the device by preventing defects caused by etching unevenness.)
The question then becomes, where would it have been obvious to place the etch stop layer in the arrangement of Zhao (now Yuan) since Kim is missing some of the layers. It is known in the art that maintaining etch uniformity is harder the greater the height being etched. Therefore, it would be obvious to minimize the height of the etching step where over-etching is possible (the last etching step). As such, it would be obvious to place the etch stop layer between the bottom layer to be etched and the other layers to be etched. In Kim, this is between the gate insulating film 114 and the interlayer insulating film 116 (as is shown); in Zhao (and now Yuan) this would be between the first gate insulating layer (104) and the second gate insulating layer (106) (In Yuan, it would be between first insulating layer 31 and the second insulating layer 32). Placing the etch stop layer in this position would minimize the height of the last etching step, which is the step where over-etching can occur, thereby increasing etch uniformity to the greatest extent possible.
Applicant’s third argument , pages 11-12 of the Remarks, is also found unpersuasive. It is well known in the art that the gate of a transistor can also act as the bottom electrode of a capacitor, as shown in Yuan where the gate electrode 2212/2241 also serves as the bottom electrode of capacitor 224 and an upper electrode (second capacitor plate 2242) serves as the upper electrode of the capacitor. This is the same arrangement previously shown in Zhao. This argument is mute due to the new ground of rejection based on Yuan; however, Examiner does not feel that this limitation would have distinguished over the previous prior art.
Regarding Claims 14-18, Applicant argues, on pages 12-13, that combining Lee with Zhao, Choi and Kim (now Yuan, Choi, and Kim) would require a substantial redesign of Zhao’s device (now Yuan) because it would change the inorganic stacked layer to a hybrid organic/inorganic stacked layer (Page 13 Lines 1-3). Examiner disagrees. The purpose of the etch stop layer is to have etch selectivity with the other layer to be etched ([0017] forming an etch stop layer having an etch selectivity with a subsequent interlayer insulating layer). Kim discloses the etch stop layer 190 is made of silicon nitride ([Page 6 Line 16] SiNx (etching stop layer)) when in insulating film is SiO2 ([Page 3 Line 26-27] SiO .sub. 2 deposited to form the interlayer insulating film 16).
However, Yuan discloses that the first insulating layer 31, the second insulating layer 32 and the third insulating layer 33 is a silicon nitride layer ([0054]). Therefore, SiNx would not have etch selectivity with the insulating layers. Therefore, it would have been obvious before the effective filing date to use a different material for the etch stop layer which has etch selectivity with the silicon nitride insulating layers.
It is well known in the art (as evidenced by Tran (US 2007/0049011 A1) (newly cited) that amorphous carbon has high etch selectivity with silicon nitride ([0044] Due to its excellent etch selectivity relative to a variety of materials, including oxides, nitrides and silicon, the temporary layer 140 is preferably formed of amorphous carbon), therefore, it would have been obvious to make the etch stop layer out of amorphous carbon as disclosed in Lee instead of the SiNx etch stop layer in Kim in order to have good etch selectivity with the silicon nitride insulating layers of Yuan.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.J.G./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893