DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after May 23, 2022 is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the
statutory basis for the rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner
with paragraph numbers in the application and/or references cited to assist the examiner in
locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the
specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Remarks, filed 8/13/2025, with respect to the rejections of claims 1, 10 and 16 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Im, Yun-Hyeok (Pub No. US 20120119359 A1) (hereinafter, Im) in view of Hsiao, Yu-Hsiang et al. (Pub No. US 20160260677 A1) (hereinafter, Hsiao).
6. Applicant’s arguments, see the Remarks, filed 8/13/2025, with respect to objection to the specification have been fully considered and are persuasive. The object of the specification has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-4, 6, 9-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Im, Yun-Hyeok (Pub No. US 20120119359 A1) (hereinafter, Im), and further in view of Hsiao, Yu-Hsiang et al. (Pub No. US 20160260677 A1) (hereinafter, Hsiao).
Im, Fig 42: Sixth embodiment of interconnect structure - upper solder layer
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Re Claim 1, (Currently Amended) Im teaches a microelectronic assembly, comprising:
a die (Substrate; 10; Fig 42; ¶[0086]; Note: per ¶[0102] substrate 10 has preliminary semiconductor chips formed therein) having a first conductive contact (Connection pad; 20; Fig 42; ¶[0087]) on a surface (Lower surface of substrate 10; Fig 42);
a substrate (Substrate or Interposer; 110/160; Figs 42/43; ¶[0086]) having a second conductive contact (Connection pad and/or seed layer; 120/132; Fig 42; ¶[0087]) on a surface (Upper surface of substrate 110; Fig 42); and
an interconnect (First bump/Second bump/Nano-wires; 60/70/64; Fig 42; ¶[0089-0090]) electrically coupling the first conductive contact of the die and the second conductive contact of the substrate,
wherein the interconnect includes a portion of a nanowire (Nano-wire; 64; Fig 42; ¶[0089]) on the second conductive contact and a first intermetallic compound (IMC) (First and/or second bump; 60/70; Fig 42; ¶[0089-0090]) surrounding at least a portion of the nanowire on the second conductive contact.
However, Im does not teach a solder material between the first IMC and the second conductive contact; and
a second IMC between the solder material and the second conductive contact.
In the same field of endeavor, Hsiao teaches a solder material (Main solder portion; 45; Fig 2; ¶[0024]) between the first IMC (IMC top layer; 50; Fig 2; ¶[0025]) and the second conductive contact (Metal circuit layer; 422; Fig 2; ¶[0022]); and
a second IMC (IMC bottom layer; 52; Fig 2; ¶[0025]) between the solder material and the second conductive contact (Upper circuit layer; 383; Fig 2; ¶[0018]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a solder material between the first IMC and the second conductive contact; and a second IMC between the solder material and the second conductive contact, as taught by Hsiao for the semiconductor device of Im. One would have been motivated to do this with a reasonable expectation of success because the two IMC layers placed surrounding the solder material allows for avoiding joint crack and increasing mechanical reliability of the semiconductor flip-chip bonded device, as suggested by Im (¶[0028]).
Re Claim 2, (Original) Im teaches the microelectronic assembly of claim 1, wherein a material of the nanowire (Nano-wire; 64; Fig 42; ¶[0089]) includes copper, nickel, gold, silver, or palladium, or an alloy thereof (First bump 60 includes nano-wires 64, and may include copper (Cu), nickel (Ni), gold (Au), silver (Ag), indium (In), etc; ¶[0089]).
Re Claim 3, (Original) Im teaches the microelectronic assembly of claim 1, wherein the IMC (First and/or second bump; 60/70; Fig 42; ¶[0089-0090]) extends from the first conductive contact (Connection pad; 20; Fig 42; ¶[0087]) to the second conductive contact (Connection pad and/or seed layer; 120/132; Fig 42; ¶[0087]).
Im, Fig 43: Seventh embodiment of semiconductor package
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Re Claim 4, (Original) Im teaches the microelectronic assembly of claim 1, further including an underfill material (Sealing member; 150; Fig 43; ¶[0091]) around the interconnect (First bump/Second bump/Nano-wires; 60/70/64; Fig 42; ¶[0089-0090]).
Im, Fig 2: Cross-section of interconnect structure in semiconductor package
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Re Claim 6, (Currently Amended) Im teaches the microelectronic assembly of claim 1, wherein the solder material (Second bump; 70; Figs 2/42; ¶[0089]) includes tin; tin and silver; tin and bismuth; tin, silver, and bismuth; indium; indium and tin; antimony; or gallium (tin (Sn), tin/silver (Sn/Ag), tin/copper (Sn/Cu), tin/indium (Sn/In); ¶[0126]).
Re Claim 9, (Original) Im teaches the microelectronic assembly of claim 1,
wherein the substrate (Substrate or Interposer; 110/160; Figs 42/43; ¶[0086]) includes a first surface (Lower surface of interposer 160; Fig 43) with a third conductive contact (Connection pad; 162; Fig 43; ¶[0132]) and an opposing second surface (Upper surface of interposer 160; Fig 43) with the second conductive contact (Connection pad; 120/164; Figs 42/43; ¶[0087]; Note: The sixth embodiment (see Figs 41/42) replaces the first conductive contact with the second conductive contact),
and the microelectronic assembly further includes:
a circuit board (Circuit board, i.e. mounting substrate; 110; Fig 43; ¶[0082]) electrically coupled to the third conductive contact on the first surface of the substrate.
Re Claim 10, (Currently Amended) Im teaches a microelectronic assembly, comprising:
a microelectronic component (Substrate; 10; Fig 2; ¶[0086]; Note: per ¶[0102] substrate 10 has preliminary semiconductor chips formed therein) having a first conductive contact (Connection pad and/or seed layer; 20/32; Fig 2; ¶[0087]) with nanowires (Nano-wires; 64; Fig 2; ¶[0089]) extending from a surface (Lower surface of connection pad and/or seed layer 20/32; Fig 2) of the first conductive contact;
a substrate (Substrate; 110; Fig 2; ¶[0086]) having a second conductive contact (Connection pad; 120; Fig 2; ¶[0087]); and
an interconnect (First bump/Second bump/Nano-wires; 60/70/64; Fig 2; ¶[0089-0090]) electrically coupling the first conductive contact of the microelectronic component and the second conductive contact of the substrate,
wherein the interconnect includes a first intermetallic compound (IMC) (First and/or second bump; 60/70; Fig 2; ¶[0089-0090]) surrounding at least a portion (Surrounds all nanowires; Fig 2) of the nanowires on the first conductive contact.
However, Im does not teach a solder material between the first IMC and the second conductive contact; and
a second IMC between the solder material and the second conductive contact.
In the same field of endeavor, Hsiao teaches a solder material (Main solder portion; 45; Fig 2; ¶[0024]) between the first IMC (IMC top layer; 50; Fig 2; ¶[0025]) and the second conductive contact (Metal circuit layer; 422; Fig 2; ¶[0022]); and
a second IMC (IMC bottom layer; 52; Fig 2; ¶[0025]) between the solder material and the second conductive contact (Upper circuit layer; 383; Fig 2; ¶[0018]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a solder material between the first IMC and the second conductive contact; and a second IMC between the solder material and the second conductive contact, as taught by Hsiao for the semiconductor device of Im. One would have been motivated to do this with a reasonable expectation of success because the two IMC layers placed surrounding the solder material allows for avoiding joint crack and increasing mechanical reliability of the semiconductor flip-chip bonded device, as suggested by Im (¶[0028]).
Re Claim 11, (Original) Im teaches the microelectronic assembly of claim 10, wherein a material of the nanowires (Nano-wires; 64; Fig 2; ¶[0089]) includes copper, nickel, gold, silver, or palladium, or an alloy thereof (First bump 60 includes nano-wires 64, and may include copper (Cu), nickel (Ni), gold (Au), silver (Ag), indium (In), etc; ¶[0089]).
Re Claim 12, (Original) Im teaches the microelectronic assembly of claim 10, wherein the IMC (First and/or second bump; 60/70; Fig 2; ¶[0089-0090]) extends from the first conductive contact (Connection pad and/or seed layer; 20/32; Fig 2; ¶[0087]) to the second conductive contact (Connection pad; 120; Fig 2; ¶[0087]).
Re Claim 13, (Currently Amended) Im teaches the microelectronic assembly of claim 10,
and wherein the solder material (Second bump; 70; Fig 2; ¶[0089]) includes tin; tin and silver; tin and bismuth; tin, silver, and bismuth; indium; indium and tin; antimony; or gallium (tin (Sn), tin/silver (Sn/Ag), tin/copper (Sn/Cu), tin/indium (Sn/In); ¶[0126]).
Re Claim 15, (Original) Im teaches the microelectronic assembly of claim 10, wherein the microelectronic component (Substrate; 10; Fig 42; ¶[0086]; Note: per ¶[0102] substrate 10 has preliminary semiconductor chips formed therein) is a die selected from the group consisting of a central processing unit, a platform controller hub, a memory die, a field programmable gate array silicon die, and graphic processing unit (Memory device, e.g. DRAM, SRAM, Flash EEPROM, etc.; ¶[0085]).
Re Claim 16, (Currently Amended) Im teaches a method for fabricating a microelectronic assembly, the method comprising:
Im, Fig 16: Electroplating nanowires
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electroplating (Electroplating process to form first bump including nanowires; ¶[0139]) nanowires (Nano-wires; 64; Fig 16; ¶[0139]) on a first conductive contact (Connection pad and/or seed layer; 20/32; Fig 16; ¶[0087]) on a first component (Substrate; 10; Fig 16; ¶[0086]; Note: per ¶[0102] substrate 10 has preliminary semiconductor chips formed therein);
Im, Fig 17: Depositing solder onto substrate
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depositing a solder material (Second bump; 70; Fig 17; ¶[0089]) on a second conductive contact (Connection pad; 120; Fig 17; ¶[0087]) on a second component (Substrate or Interposer; 110/160; Fig 17; ¶[0086]);
melting (Reflow process, i.e. includes melting solder; ¶[0141]) the solder material on the second conductive contact;
placing the nanowires of the first conductive contact in contact (Arranging nanowires 64 to be in contact with second bump 70; Fig 17) with the solder material of the second conductive contact; and
forming a first interconnect (First bump/Second bump/Nano-wires; 60/70/64; Fig 17; ¶[0089-0090]) between the first component and the second component that includes an intermetallic compound (First and/or second bump; 60/70; Fig 17; ¶[0089-0090]) surrounding the nanowires on the first conductive contact.
However, Im does not teach a solder material between the first IMC and the second conductive contact; and
a second IMC between the solder material and the second conductive contact.
In the same field of endeavor, Hsiao teaches a solder material (Main solder portion; 45; Fig 2; ¶[0024]) between the first IMC (IMC top layer; 50; Fig 2; ¶[0025]) and the second conductive contact (Metal circuit layer; 422; Fig 2; ¶[0022]); and
a second IMC (IMC bottom layer; 52; Fig 2; ¶[0025]) between the solder material and the second conductive contact (Upper circuit layer; 383; Fig 2; ¶[0018]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a solder material between the first IMC and the second conductive contact; and a second IMC between the solder material and the second conductive contact, as taught by Hsiao for the semiconductor device of Im. One would have been motivated to do this with a reasonable expectation of success because the two IMC layers placed surrounding the solder material allows for avoiding joint crack and increasing mechanical reliability of the semiconductor flip-chip bonded device, as suggested by Im (¶[0028]).
Re Claim 17, (Original) Im teaches the method of claim 16, wherein the first component is a substrate (Substrate or Interposer; 110/160; Figs 42/43; ¶[0086]; Note: first component in the sixth embodiment attaches to nanowires) and the second component is a die (Substrate; 10; Fig 42; ¶[0086]; Note: per ¶[0102] substrate 10 has preliminary semiconductor chips formed therein, and second component is disposed above connection pad).
Re Claim 18, (Original) Im teaches the method of claim 16, wherein the first component is a die (Substrate; 10; Fig 16; ¶[0086]; Note: per ¶[0102] substrate 10 has preliminary semiconductor chips formed therein) and the second component is a substrate (Substrate or Interposer; 110/160; Fig 17; ¶[0086]).
Re Claim 19, (Original) Im teaches the method of claim 16, wherein a material of the nanowires (Nano-wires; 64; Fig 2; ¶[0089]) includes copper, nickel, gold, silver, or palladium, or an alloy thereof (First bump 60 includes nano-wires 64, and may include copper (Cu), nickel (Ni), gold (Au), silver (Ag), indium (In), etc; ¶[0089]).
Re Claim 20, (Original) Im teaches the method of claim 16, wherein the solder material (Second bump; 70; Figs 2/42; ¶[0089]) includes tin; tin and silver; tin and bismuth; tin, silver, and bismuth; indium; indium and tin; antimony; or gallium (tin (Sn), tin/silver (Sn/Ag), tin/copper (Sn/Cu), tin/indium (Sn/In); ¶[0126]).
9. Claims 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Im, Yun-Hyeok (Pub No. US 20120119359 A1) (hereinafter, Im) in view of Hsiao, Yu-Hsiang et al. (Pub No. US 20160260677 A1) (hereinafter, Hsiao) as applied to Claims 1 and 10, and further in view of Haba, Belgacem et al. (Pub No. US 20200294908 A1) (hereinafter, Haba).
Haba, Fig 2: Bonded structure with passive components
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Re Claim 8, (Original) Im teaches the microelectronic assembly of claim 1, wherein the interconnect (First bump/Second bump/Nano-wires; 60/70/64; Fig 42; ¶[0089-0090]) is one of a plurality of interconnects (Plurality of interconnects; A; Fig 43; ¶[0080]).
However, Im in view of Hsiao does not teach and a pitch of the plurality of interconnects is between 3 microns and 20 microns.
In the same field of endeavor, Haba teaches and a pitch (Horizontal distance between contact pads 21, which comprise of a comparable length as the conductive features 9a/a' and 9b/b'; Fig 2; ¶[0067]) of the plurality of interconnects (Conductive features; 9a/a' and 9b/b'; Fig 2; ¶[0066]) is between 3 microns and 20 microns (Per ¶[0067] the pitch of the contact pads 21 can be in a range of 0.5 microns to 50 microns, in a range of 0.5 microns to 20 microns, or in a range of 1 micron to 10 microns (e.g., about 5 microns)).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a pitch of the plurality of interconnects taught by Im in view of Hsiao to be between 3 microns and 20 microns, as taught by Brand. One would have been motivated to do this with a reasonable expectation of success because passive components (interconnects) occupy valuable space on the integrated device die, the package, and/or the system board, and incorporating passive components in an efficient manner allows for miniaturization of modern semiconductor packages, such that performance of active devices is enhanced, as suggested by Haba (¶[0003]).
Im, Fig 1: First embodiment of semiconductor package
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Re Claim 14, (Original) Im teaches the microelectronic assembly of claim 10, wherein the interconnect (First bump/Second bump/Nano-wires; 60/70/64; Fig 2; ¶[0089-0090]) is one of a plurality of interconnects (Plurality of interconnects; A; Fig 1; ¶[0080]).
However, Im in view of Hsiao does not teach and a pitch of the plurality of interconnects is between 3 microns and 20 microns.
In the same field of endeavor, Haba teaches and a pitch (Horizontal distance between contact pads 21, which comprise of a comparable length as the conductive features 9a/a' and 9b/b'; Fig 2; ¶[0067]) of the plurality of interconnects (Conductive features; 9a/a' and 9b/b'; Fig 2; ¶[0066]) is between 3 microns and 20 microns (Per ¶[0067] the pitch of the contact pads 21 can be in a range of 0.5 microns to 50 microns, in a range of 0.5 microns to 20 microns, or in a range of 1 micron to 10 microns (e.g., about 5 microns)).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a pitch of the plurality of interconnects taught by Im in view of Hsiao to be between 3 microns and 20 microns, as taught by Brand. One would have been motivated to do this with a reasonable expectation of success because passive components (interconnects) occupy valuable space on the integrated device die, the package, and/or the system board, and incorporating passive components in an efficient manner allows for miniaturization of modern semiconductor packages, such that performance of active devices is enhanced, as suggested by Haba (¶[0003]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817