DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishimaru et al. (US 20100210088) in view of KURAGUCHI et al. (US 20120012857).
Regarding claim 1, Ishimaru discloses that a method of aligning a lithographic layer on a semiconductor wafer having planar and parallel first and second surfaces on first and sides of the semiconductor wafer, respectively, the first and second surfaces being separated by the thickness of the semiconductor wafer, the method comprising:
forming a first alignment structure DP from one or more first trenches extending from the first surface S1 into the semiconductor wafer 10 (Fig. 2B);
aligning at least one lithographic layer 15 arranged on the second side of the semiconductor wafer S2 and parallel to the second surface.
Ishimaru fails to teach that by detecting the first alignment structure from the second side, using illumination in the visible spectrum.
However, KURAGUCHI suggests that a layer can be formed after detecting the first alignment structure from the second side, using illumination in the visible spectrum (para. 0024-0025). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Ishimaru with aligning at least one lithographic layer, by detecting the first alignment structure from the second side, using illumination in the visible spectrum as taught by KURAGUCHI in order to high-accuracy alignment is further required for recently advanced miniaturization of the device and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Claim(s) 2-8, 13 & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishimaru et al. (US 20100210088) in view of KURAGUCHI et al. (US 20120012857) and further in view of Yang et al.(US 10534276).
Reclaim 2, Ishimaru & KURAGUCHI fail to teach that that aligning one or more lithographic layers arranged on the first side of the semiconductor wafer and parallel to the first surface of the semiconductor wafer, using the first alignment structure.
However, Yang suggests that aligning one or more lithographic layers 170 arranged on the first side of the semiconductor wafer and parallel to the first surface of the semiconductor wafer, using the first alignment structure (Fig. 10).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Ishimaru & KURAGUCHI with aligning one or more lithographic layers 170 arranged on the first side of the semiconductor wafer and parallel to the first surface of the semiconductor wafer, using the first alignment structure as taught by Yang in order to enhance accurate alignment (col. 14, lines 60) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 3, Ishimaru, KURAGUCHI, & Yang disclose that the one or more first trenches 12 & 13 (Ishimaru’s Fig 3D)are formed in a kerf portion of the semiconductor wafer using a same etching step used to form one or more trenches in an active portion of the semiconductor wafer (Ishimaru’s Fig. 3D in view of Yang’s 2A).
Reclaim 4, Ishimaru, KURAGUCHI, & Yang disclose that the one or more first trenches 12/13 (Ishimaru’s Fig. 3D) are formed to the same depth as the one or more trenches in the active portion of the semiconductor wafer (Ishimaru’s Fig. 3D in view of Yang’s 2A).
Reclaim 5, Ishimaru, KURAGUCHI, & Yang disclose that the one or more first trenches 12/13 have a wider critical distance than the one or more trenches in the active portion of the semiconductor wafer, such that the one or more first trenches are deeper than the one or more trenches in the active portion of the semiconductor wafer (Ishimaru’s Fig. 3D in view of Yang’s 2A).
Reclaim 6, Ishimaru, KURAGUCHI, & Yang fail to specify that said one or more first trenches are formed to a depth reaching to within about 3 micrometers from the second surface of the semiconductor wafer (Ishimaru, para. 0113, overlapping range).
Reclaim 7, Ishimaru, KURAGUCHI, & Yang disclose that said method further comprises thinning the semiconductor wafer from a side opposite the first side, thereby forming the second surface, prior to said aligning (Ishimaru’s Fig. 2D-3D in view of Yang’s 2A).
Reclaim 8, Ishimaru, KURAGUCHI, & Yang disclose that said thinning is performed so that the one or more first trenches reach to within about three micrometers from the second surface of the semiconductor wafer (Ishimaru’s Fig. 2D-3D in view of Yang’s 2A).
Reclaim 13, Ishimaru, KURAGUCHI, & Yang disclose that the method comprises forming one or more image sensor devices in an active region of the semiconductor wafer, on the first side (Ishimaru’s Fig. 2D-3D in view of Yang’s 2A).
Reclaim 19, Ishimaru, KURAGUCHI, & Yang disclose that the one or more first trenches are at least substantially empty of solid material during said aligning (Fig. 2D-3D, Ishimaru in view of Yang’s Fig. 2A).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 14-18 are allowed over the prior art.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
After further search and consideration, it is determined that the prior art neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination. The prior art does not teach or render not obvious “- - depositing an epitaxial layer on the first side-surface of the semiconductor wafer, after said forming of the first alignment structure, such that a bottom side of said epitaxial layer contacts the first surface and overgrows the one or more first trenches, leaving corresponding cavities between the semiconductor wafer and the epitaxial layer; thinning the semiconductor wafer from a side opposite the first side, after said depositing, thereby forming|[ a]]_the second side-surface, to at least a thickness where the cavities are detectable from the second side of the semiconductor wafer using illumination in the visible spectrum; and aligning at least one lithographic layer arranged parallel to the second surface on the second side of the semiconductor wafer, by detecting the cavities from the second side, using illumination in the visible spectrum.” with combination of other claim limitations in claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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/SU C KIM/ Primary Examiner, Art Unit 2899
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