The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-11 and 13-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (20080116487) in view of Huang et al. (10,522,359).
Regarding claims 1, 10 and 16, Lee et al. teach in figure 8 and related text a semiconductor device comprising:
a semiconductor substrate 100;
an element isolation 105s provided on the semiconductor substrate; and
a plurality of conductive layers 127a-c facing to the semiconductor substrate and the element isolation, and
a plurality of contacts,
wherein the semiconductor substrate includes a first active region 105a and a second active region 105b arranged in a first direction along a main surface of the semiconductor substrate,
the element isolation 105s is provided between the first active region and the second active region,
the semiconductor device includes a first gate insulating film 125a and a second gate insulating film 125b respectively facing (positioning in front) to the first active region and the second active region, in a second direction intersecting with the main surface of the semiconductor substrate, and
the plurality of conductive layers include:
a first gate electrode 127a and a second gate electrode 127b respectively facing (positioning in front) to the first gate insulating film and the second gate insulating film, in the second direction; and
a first electrode 170a and a second electrode 170b facing to the element isolation in the second direction and arranged in the first direction, the first electrode being disposed on the first active region side, and the second electrode being disposed on the second active region side,
the first active region and the second active region each include a first region, a second region, and a third region (all regions are arbitrarily chosen) sequentially arranged in a third direction intersecting with the first direction and the second direction (since all devices are 3D devices), and
the plurality of contacts include:
a first contact 170a connecting to the first region of the first active region 105a;
a third contact (another 170a) connecting to the third region of the first active region 105a;
a fourth contact 170b connecting to the first region of the second active region 105b; and
a sixth contact (another 170b) connecting to the third region of the second active region 105b.
Lee et al. do not teach a second contact connecting to the first gate electrode and a fifth contact connecting to the second gate electrode.
Huang et al. teach in figure 8 and related text a second contact 160 connecting to the first gate electrode and a fifth contact 108 connecting to the second gate electrode.
Huang et al. and Lee et al. are analogous art because they are directed to semiconductor devices comprising contacts and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a second contact connecting to the first gate electrode and a fifth contact connecting to the second gate electrode, as taught by Huang et al., in Lee et al.’s device, in order to be able to operate the device in its intended use. The device will not operate without contacts connecting to the gate electrodes.
Regarding claim 2, Lee et al. teach in figure 8 and related text that the first electrode and the second electrode are disposed at least between the first region of the first active region and the first region of the second active region, viewed from the second direction.
Regarding claim 10, Lee et al. teach in figure 8 and related text a semiconductor device comprising:
a semiconductor substrate 100;
a first transistor A disposed on the semiconductor substrate;
a second transistor B disposed on the semiconductor substrate and arranged on a first side in the first direction along a main surface of the semiconductor substrate with respect to the first transistor;
a third transistor C disposed on the semiconductor substrate and arranged on a second side in the first direction with respect to the first transistor;
a first element isolation 105s disposed between the first transistor and the second transistor;
a second element isolation (another 105s) disposed between the first transistor and the third transistor;
a first electrode 127a facing (positioning in front) to the first element isolation, in a second direction intersecting with the main surface of the semiconductor substrate, between a drain of the first transistor and a drain of the second transistor;
a second electrode 127b facing to the first element isolation in the second direction, between the first electrode and the drain of the second transistor;
a third electrode 127c facing to the second element isolation in the second direction, between the drain of the first transistor and a drain of the third transistor; and
a fourth electrode 170b facing to the second element isolation in the second direction, between the third electrode and the drain of the third transistor.
Lee et al. do not explicitly state using drains as specific region.
Huang et al. teach in figure 1 and related text using drains 44 as part of the active regions.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use explicit regions as drains, as taught by Huang et al., in Lee et al.’s device, in order to be able to operate the device in its intended use.
Regarding claim 3, Lee et al. teach substantially the entire claimed structure, as applied to claim 1 above, except explicitly stating that the semiconductor device is configured to simultaneously apply different voltages to the first electrode and the second electrode.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to configure the semiconductor device to simultaneously apply different voltages to the first electrode and the second electrode, in Lee et al.’s device, in order to operate the device in its intended use.
Regarding claim 4, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to configure the semiconductor device to apply a voltage higher than a voltage applied to the second electrode, to the first electrode when a voltage of the first region of the first active region is higher than a voltage of the first region of the second active region in Lee et al.’s device, in order to adjust the respective voltages applied to the NMOS and PMOS transistors.
Regarding claim 6, Lee et al. teach in figure 8 and related text a third active region disposed on a side opposite to the second active region in the first direction, with respect to the first active region, wherein the element isolation 105a includes a first element isolation insulating layer and a second element isolation insulating (see figure 8), the second element isolation insulating layer is disposed between the first active region and the third active region, and the plurality of conductive layers include a third electrode (another 170a) and a fourth electrode (another 170b) facing to the second element isolation insulating in the second direction and arranged in the first direction, the third electrode being disposed on the first active region side, the fourth electrode being disposed on the third active region side.
Regarding claim 7, Lee et al. teach in figure 8 and related text that the third active region includes a fourth region, a fifth region, and a sixth region sequentially arranged in the third direction, and the third electrode and the fourth electrode are disposed at least between the first region of the first active region and the fourth region, as viewed from the second direction.
Regarding claim 8, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to configure the semiconductor device to simultaneously apply different voltages to the third electrode and the fourth electrode, in Lee et al.’s device, in order to operate the device in its intended use.
Regarding claim 9, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to configure the semiconductor device to apply a voltage higher than a voltage applied to the fourth electrode, to the third electrode when a voltage of the first region of the first active region is higher than a voltage of the fourth region, in order to adjust the respective voltages applied to the NMOS and PMOS transistors.
Regarding claim 11, as discussed in claims 1 and 9 above, Huang et al. and Lee et al. teach the entire claimed structure, as recited in claim 11.
Regarding claim 13, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form fourth, fifth and sixth transistors in Lee et al.’s device, such that the fourth transistor disposed on the semiconductor substrate and arranged with the first transistor in a third direction intersecting with the first direction and the second direction, the fourth transistor having a source shared with the first transistor; the fifth transistor disposed on the semiconductor device and arranged with the second transistor in the third direction, the fifth transistor having a source shared with the second transistor; and the sixth transistor disposed on the semiconductor device and arranged with the third transistor in the third direction, the sixth transistor having a source shared with the third transistor in prior art’s device, in order to use the device in practical application which requires pluralities of transistors and in order to simplify the processing steps of making the device.
Regarding claim 14, Lee et al. teach in figure 8 and related text a fifth electrode facing to the first element isolation in the second direction, between a drain of the fourth transistor and a drain of the fifth transistor; a sixth electrode facing to the first element isolation in the second direction, between the fifth electrode and the drain of the fifth transistor; a seventh electrode facing to the second element isolation in the second direction, between the drain of the fourth transistor and a drain of the sixth transistor; and an eighth electrode (since Lee et al. teach having eight electrodes) facing to the second element isolation in the second direction, between the seventh electrode and the drain of the sixth transistor.
Regarding claim 15, Lee et al. teach in figure 8 and related text that the first electrode and the fifth electrode, the second electrode and the sixth electrode, the third electrode and the seventh electrode, the fourth electrode and the eighth electrode are each arranged in the third direction, and are each electrically insulated from one another.
Regarding claim 16, Lee et al. teach substantially the entire claimed structure, as applied to claim 1 above, except teaching using the device as a memory device. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use prior art’s device as a memory device in order to expand the applicability of the device.
Regarding claim 17, Lee et al. teach in figure 8 and related text that the first electrode and the second electrode are disposed at least between the first region of the first active region and the first region of the second active region, as viewed from the second direction.
Regarding claim 18, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to configure the semiconductor device to simultaneously apply different voltages to the first electrode and the second electrode, in Lee et al.’s device, in order to operate the device in its intended use.
Regarding claim 19, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to configure the semiconductor device to apply a voltage higher than a voltage applied to the second electrode, to the first electrode when a voltage of the first region of the first active region is higher than a voltage of the first region of the second active region, in Lee et al.’s device, in order to adjust the respective voltages applied to the NMOS and PMOS transistors.
Response to Arguments
1. Applicants argue that “it is apparent in the above annotated Fig. 8 of Lee
et al that the first electrode 170a does not face the element isolation 105s in the second direction (i.e., the up-down direction, as defined by the Examiner)”.
Applicants further argue that “even if the first and second electrodes
170a and 170b of Lee et al could be considered to "face to" an element isolation, they clearly are provided with respective different such element isolations and not to one (same) element isolation, as recited in claim 1”.
1. The claimed limitation of “face to” does require any direction to the elements.
2. Applicants argue that “each of the contact structures 170a,170b, and 170c of Lee et al is connected to a single respective source/drain region in a single respective transistor region (A, B, or C). However, Lee et al does not disclose or or suggest contact structures connecting separately to a first region and a third region of a same active region, as recited in claim 1.”
2. The term “region” means part of a whole. Therefore, a single respective source/drain region can comprise many pluralities of “regions”.
3. Applicants argue that by citing “another 170b” then “the Examiner cites the contact structure 170a as corresponding to both the first and third contacts, and cites the contact structure 170b as corresponding to both the fourth and sixth contacts”.
3. Lee et al. teach plurality of 170a and 170b contact structures. Therefore, the citation refers to different contact structures and not to the same contact structure, as argue by applicants.
4. Applicants argue, regarding claim 10, that “while these gate electrodes face their respective gate insulating films and active regions in the second direction, they do not face the element isolation 105s in the second direction, as recited in claim 10”, and “In Lee et al, the electrodes identified by the Examiner are either gate electrodes over the active regions or a single source/drain contact plug over the drain of transistor B”.
4. As noted above, the claimed limitation of “face to” does require any direction to the elements. Furthermore, “gate electrodes” are “contact structure”.
5. Applicants argue that “in Lee et al, the transistors B and C are both arranged on a same side of the first transistor along the first direction (e.g., the right side in Fig. 8), and Lee et al clearly fails to teach or suggest providing the transistor C on a second side with respect to the first transistor along the first direction”.
5. The claimed limitation of “a second transistor disposed on the semiconductor substrate and arranged on a first side in the first direction along a main surface of the semiconductor substrate with respect to the first transistor; a third transistor disposed on the semiconductor substrate and arranged on a second side in the first direction with respect to the first transistor” does not explicitly state that the second transistor is arranged on a first side of the first transistor and the third transistor is arranged on a second side the first transistor, because the phrase “with respect to” is not explicitly defined as asserted by applicants.
Furthermore, the broad recitation of the claim does not require that the “second side” must be interpreted as the “opposite side”.
Moreover, merely identifying the first/second/third transistors as transistors B/A/C, respectively, would read on the claimed limitation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
6/14/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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