DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed January 28, 2026 has been entered. Claims 1-30 remain pending in the application. Applicant’s amendments to the Drawings have overcome each and every objection previously set forth in the Non-Final Office Action mailed October 30, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 3 are rejected under 35 U.S.C. 103 as being unpatentable over Tessariol et. al. (US20170263556A1), hereinafter Tessariol, in view of Zhang et. al. (US20210296232A1), hereinafter Zhang, with support from US Patent (US9941209B2) corresponds to US20170263556A1.
Regarding claim 1, Tessariol teaches a microelectronic device (Fig 2 conductive structure 100, [0021]), comprising: a stack structure (Fig 2 stair step structure 106, 108, 110, [0032]) comprising blocks (not shown, [0021]) separated from one another by dielectric slot structures (Fig 4 stack slot element 240, [0047]) and each including a vertically alternating sequence (Fig 2 top left corner for clarity, [0026]) of conductive structures (Fig 2 conductive materials 103, [0026]) and insulative structures (Fig 2 insulative materials 105, [0026]) arranged in tiers (Fig 2 stair step structure 106, 108, 110, [0032]), at least one of the blocks (Fig 3 conductive structure 200, [0039]) comprising: an upper stadium structure (Fig 2 stair step structure 106, [0032]) extending in a first horizontal direction (See annotated figure) from and between two of the dielectric slot structures (Fig 4 stack slot element 240, [0047]), the upper stadium structure (Fig 2 stair step structure 106, [0032]) comprising staircase structures (Fig 2 stair step structure 106, [0032]) having steps comprising edges of some of the tiers; two crest regions (Fig 2 landings 112, [0027]) offset from the upper stadium structure (Fig 2 stair step structure 106, [0032]) in a second horizontal direction (See annotated figure) orthogonal to the first horizontal direction (See annotated figure); a lower stadium structure (Fig 2 stair step structure 108, [0032]) vertically below the upper stadium structure (Fig 2 stair step structure 106, [0032]) and interposed between the two crest regions (Fig 2 landings 112, [0027]) in the second horizontal direction (See annotated figure), the lower stadium structure (Fig 2 stair step structure 108, [0032]) comprising additional staircase structures (Fig 2 stair step structure 108, [0032]) having additional steps comprising edges of some other of the tiers.
Tessariol fails to teach two bridge regions interposed between the lower stadium structure and the two of the dielectric slot structures in the first horizontal direction and extending from and between the two crest regions in the second horizontal direction, the two bridge regions having upper surfaces substantially coplanar with upper surfaces of the two crest regions, and the two bridge regions not interposed between the upper stadium structure and the two of the dielectric slot structures.
However, Zhang teaches two bridge regions (Fig 6A bridge structure 614, [0061]) interposed between the lower stadium structure (Fig 6A staircase 610-1, [0061] corresponds to Tessariol: Fig 2 stair step structure 108, [0032]) and the two of the dielectric slot structures (The bridge structure can be multilayered to include conductive and dielectric layers, [0088] corresponds to Tessariol: Fig 4 stack slot element 240, [0047]) in the first horizontal direction (See annotated figure) and extending from and between the two crest regions (Fig 6A area between staircases in X direction corresponds to Tessariol: Fig 2 landings 112, [0027]) in the second horizontal direction (See annotated figure), the two bridge regions (Fig 6A bridge structure 614, [0061]) having upper surfaces substantially coplanar (Fig 6A upper surfaces are coplaner) with upper surfaces of the two crest regions (Fig 6A area between staircases in X direction corresponds to Tessariol: Fig 2 landings 112, [0027]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol to incorporate the teachings of Zhang by having two bridge regions interposed between the lower stadium structure and the two of the dielectric slot structures in the first horizontal direction and extending from and between the two crest regions in the second horizontal direction, the two bridge regions having upper surfaces substantially coplanar with upper surfaces of the two crest regions. This would allow for electrical connection between different staircase structures ([0006]). Zhang further teaches that the staircase zones can be formed at different depths ([0008]). In applying the bridge regions of Zhang to the lower stadium structure, the upper stadium structure would be lacking the bridge regions, i.e. the two bridge regions not interposed between the upper stadium structure and the two of the dielectric slot structures.
It is noted for clarity of the record that Tessariol teaches one semiconductor device but teaches that an electronic device can include one or more portions of the semiconductor device ([0021]).
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Regarding claim 2, Tessariol teaches additional dielectric slot structures (Fig 4 inner stack slot elements 238, [0042]) partially vertically extending through the at least one of the blocks, the additional dielectric slot structures vertically overlying the lower stadium structure (Fig 2 stair step structure 108, [0032]) and extending in the second horizontal direction into a horizontal area of the upper stadium structure (Fig 2 stair step structure 106, [0032]).
With regards to additional dielectric slot structures partially vertically extending through the at least one of the blocks, the additional dielectric slot structures vertically overlying the lower stadium structure and extending in the second horizontal direction into a horizontal area of the upper stadium structure, Tessariol teaches a simplified fabrication method (0048) that includes the additional dielectric structure. Examiner interprets the substrate (Fig 5 substrate 302, [0051]) in Figs 5 – 9 to mean the lowermost level desired for the staircase such that when the additional dielectric slot is only formed extending partially through a block. The additional dielectric structure corresponding to the insulative material (Fig 8 insulative material 314) as Tessariol teaches the stack slot element 238 can be formed of insulative materials ([0055]).
Regarding claim 3, Tessariol teaches conductive contact structures (Fig 4 conductive portions 218, Col 8, lines 32-33 of US Patent US9941209B2 is the same as Fig 4 of Tessariol) physically contacting the steps of the upper stadium structure (Fig 3 stair step structure 206 corresponds to Fig 2 stair step structure 106) and the additional steps of the lower stadium structure (Fig 3 stair step structure 208 corresponds to Fig 2 stair step structure 108).
With regards to the conductive contact structures physically contacting the additional steps of the lower stadium structure, Tessariol fails to label the structures in the lower portion of Fig 4. Examiner interprets the structures in the lower portion of Fig 4 to be the same as the conductive portions of the upper stadium structure as they are drawn the same and are also connected to contacts (Fig 4 contacts 228, [0056]).
It is noted for clarity of the record that the PG Publication for Tessariol teaches Fig 4 reference number 218, but the reference number is not in the specification. The US Patent for Tessariol associated with the PB Publication has the same Fig 4 and the reference number is in the specification.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Tessariol et. al. (US20170263556A1), hereinafter Tessariol, in view of Zhang et. al. (US220210296232A1), hereinafter Zhang, in further view of Matovu et. al. (US20200203220A1), hereinafter Matovu.
Regarding claim 4, Tessariol teaches a horizontal area (Bottom-most portion of Fig 2 stair step structure 106) of the upper stadium structure (Fig 2 stair step structure 106, [0032]) of the at least one of the blocks (Fig 3 conductive structure 200, [0039]), extending in the first horizontal direction (See annotated figure from claim 1) from and between two of the dielectric slot structures (Fig 4 stack slot element 240, [0047]).
Tessariol and Zhang fail to teach teaches a filled trench vertically overlying and within a horizontal area of the upper stadium structure of the at least one of the blocks, the filled trench comprising: a first dielectric liner on the staircase structures of the upper stadium structure and extending in the first horizontal direction from and between two of the dielectric slot structures; a second dielectric liner on the first dielectric liner and having a different material composition; and a first dielectric fill material on the second dielectric liner.
However, Matovu teaches a filled trench vertically (Fig 3G valley 325 from Fig 3E is filled) overlying and within a horizontal area (Bottom most portion of semiconductor structure 300) of the upper stadium structure (Fig 3D stair step structure 320, [0038] corresponds to Tessariol: Fig 2 stair step structure 106, [0032]) of the at least one of the blocks (Fig 2 stair step structure 200, [0022] corresponds to Tessariol: Fig 3 conductive structure 200, [0039]), the filled trench comprising: a first dielectric liner (Fig 3E first liner 326, [0042]) on the staircase structures (Fig 3D stair step structure 320, [0038] corresponds to Tessariol: Fig 2 stair step structure 106, [0032]) of the upper stadium structure (Fig 3D stair step structure 320, [0038] corresponds to Tessariol: Fig 2 stair step structure 106, [0032]) and extending in the first horizontal direction from and between two of the dielectric slot structures; a second dielectric liner (Fig 3E second liner 328, [0042]) on the first dielectric liner (Fig 3E first liner 326, [0042]) and having a different material composition (different materials listed, [0042]) than the first dielectric liner (Fig 3E first liner 326, [0042]); and a first dielectric fill material (Fig 3G insulative material 330, [0045]) on the second dielectric liner (Fig 3E second liner 328, [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol and Zhang to incorporate the teachings of Matovu by having a filled trench vertically overlying and within a horizontal area of the upper stadium structure of the at least one of the blocks, the filled trench comprising: a first dielectric liner on the staircase structures of the upper stadium structure and extending in the first horizontal direction from and between two of the dielectric slot structures; a second dielectric liner on the first dielectric liner and having a different material composition than the first dielectric liner; and a first dielectric fill material on the second dielectric liner. This would reduce failure rate of upper staircase structures of semiconductor devices formed as compared to conventional methods ([0014]).
With regards to a first dielectric liner on the staircase structures of the upper stadium structure and extending in the first horizontal direction from and between two of the dielectric slot structures. Matovu is silent on the extent of the formation of layers. However, one having ordinary skill in the art before the effective filing date of the claimed invention would recognize that Matovu is teaching that the entire valley (Fig 3G valley 325) is filled. As such, the liners and fillers would naturally be formed on the entirety of the staircase structure.
It is noted for clarity of the record that though Matovu teaches one stair step structure, one having ordinary skill in the art before the effective filing date of the claimed invention could apply this method to all the stair step structures.
Regarding claim 5, Tessariol as modified by Zhang in claim 1 teaches a horizontal area (Bottom-most portion of Fig 2 stair step structure 108) of the lower stadium structure (Fig 2 stair step structure 106, [0032]) of the at least one of the blocks (Fig 3 conductive structure 200, [0039]), the additional staircase structures (Fig 2 stair step structure 106, [0032]) of the lower stadium structure (Fig 2 stair step structure 106, [0032]) and inner sidewalls (sidewalls formed when stair case structure is formed) of the two bridge regions (From Zhang: Fig 6A bridge structure 614, [0061]).
Tessariol and Zhang fail to teach an additional filled trench vertically overlying and within a horizontal area of the lower stadium structure of the at least one of the blocks, the additional filled trench comprising: a third dielectric liner on the additional staircase structures of the lower stadium structure and on lower portions of inner sidewalls of the two bridge regions; and a fourth dielectric liner on the third dielectric liner and having a different material composition than the third dielectric liner; and a second dielectric fill material on the fourth dielectric liner.
With regards to an additional filled trench vertically overlying and within a horizontal area of the lower stadium structure of the at least one of the blocks, the additional filled trench comprising: a third dielectric liner on the additional staircase structures of the lower stadium structure and on lower portions of inner sidewalls of the two bridge regions; and a fourth dielectric liner on the third dielectric liner and having a different material composition than the third dielectric liner; and a second dielectric fill material on the fourth dielectric liner. One having ordinary skill in the art before the effective filing date of the claimed invention could take the teaching of Matovu from claim 4 and apply it to the lower stadium structure with a reasonable expectation of success. In applying the dielectric liners, the inner sidewalls of the bridge regions would be covered by the liners. Further, this would also reduce failure rate of the lower staircase structures of semiconductor devices formed as compared to conventional methods ([0014]).
Claims 6 - 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tessariol et. al. (US20170263556A1), hereinafter Tessariol, in view of Zhang et. al. (US220210296232A1), hereinafter Zhang, in further view of Matovu et. al. (US20200203220A1), hereinafter Matovu, in further view of Zhu et. al. (US20200258837A1), with support from Huang et. al. (US20060246686A1), hereinafter Huang.
Regarding claim 6, Tessariol and Zhang fail to teach the first dielectric liner and the third dielectric liner each comprise silicon oxide; the second dielectric liner comprises one or more of silicon oxynitride and silicon carboxynitride; and fifth dielectric liner comprises one or more of silicon nitride, silicon oxynitride, and silicon carboxynitride.
However, Matovu teaches the first dielectric liner (Fig 3G first liner 326, [0042]) and the third dielectric liner (Fig 3G first liner 326, [0042]) each comprise silicon oxide (silicon oxide, [0042]); and fourth dielectric liner (Fig 3G second liner 328, [0042]) comprises one or more of silicon nitride, silicon oxynitride, and silicon carboxynitride (silicon nitride, [0042]).
Matovu fails to teach the second dielectric liner comprises one or more of silicon oxynitride and silicon carboxynitride.
However, Zhu teaches the second dielectric liner (Fig 3 etch stop layer 310, [0056] corresponds to Matovu: Fig 3G second liner 328, [0042]) comprises one or more of silicon oxynitride and silicon carboxynitride (silicon oxynitride, [0056]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol, Zhang, and Matovu to incorporate the teachings of Zhu by having the second dielectric liner comprises one or more of silicon oxynitride and silicon carboxynitride. Huang teaches that using different materials for different etch stop layers can help in reducing stresses placed on the semiconductor devices by choosing materials with desirable material properties for the given region ([0006] and [0007]).
Regarding claim 7, Tessariol and Zhang fail to teach the first dielectric liner and the third dielectric liner each comprise a first dielectric material; the second dielectric liner comprises a second dielectric material different than the first dielectric material; and the fourth dielectric liner comprises a third dielectric material different than each of the first dielectric material and the second dielectric material.
However, Matovu teaches the first dielectric liner (Fig 3G first liner 326, [0042]) and the third dielectric liner (Fig 3G first liner 326, [0042]) each comprise a first dielectric material (silicon oxide, [0042]); the second dielectric liner (Fig 3G second liner 328, [0042]) comprises a second dielectric material different than the first dielectric material; and the fourth dielectric liner (Fig 3G second liner 328, [0042]) comprises a third dielectric material (silicon nitride, [0042]) different than each of the first dielectric material and the second dielectric material.
With regards to the second dielectric liner comprises a second dielectric material different than the first dielectric material and the fifth dielectric liner comprises a third dielectric material different than each of the first dielectric material and the second dielectric material. Huang teaches that using different materials for different etch stop layers can help in reducing stresses placed on the semiconductor devices ([0006] and [0007]). One of ordinary skill in the art before the effective filing date of the clamed invention could choose three different materials known in the art such that they are different and apply them the dielectric liners to act as etch stop layers with a reasonable expectation of success. This would result in the upper staircase and lower stair case having different second dielectric layers chosen for reducing the stresses between the staircase structures. MPEP 2143(I)(G)
Regarding claim 8, Tessariol and Zhang fail to teach the first dielectric material comprises dielectric oxide material; the second dielectric material comprises one or more of dielectric oxynitride material and dielectric carboxynitride material; and the third dielectric material comprises a dielectric nitride material.
However, Matovu teaches the first dielectric material (Fig 3G first liner 326, [0042]) comprises dielectric oxide material; and the third dielectric material (Fig 3G second liner 328, [0042]) comprises a dielectric nitride material (silicon nitride, [0042]).
Matovu fails to teach the second dielectric material comprises one or more of dielectric oxynitride material and dielectric carboxynitride material.
However, Zhu teaches the second dielectric material (Fig 3 etch stop layer 310, [0056] corresponds to Matovu: Fig 3G second liner 328, [0042]) comprises one or more of dielectric oxynitride material and dielectric carboxynitride material (silicon oxynitride, [0056]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol, Zhang, and Matovu to incorporate the teachings of Zhu by having the second dielectric liner comprises one or more of silicon oxynitride and silicon carboxynitride. Huang teaches that using different materials for different etch stop layers can help in reducing stresses placed on the semiconductor devices by choosing materials with desirable material properties for the given region ([0006] and [0007]).
Regarding claim 9, Tessariol and Zhang fail to teach the first dielectric fill material and the second dielectric fill material each comprise the first dielectric material.
However, Matovu teaches the first dielectric fill material (Fig 3G insulative material 330, [0045]) and the second dielectric fill material (Fig 3G insulative material 330, [0045]) each comprise the first dielectric material (silicon dioxide, [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol and Zhang to incorporate the teachings of Matovu by having the first dielectric fill material and the second dielectric fill material each comprise the first dielectric material. This would allow for filling the valley (Fig 3E valley 325) in the staircase structure ([0046]).
Claims 25 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Tessariol et. al. (US20170263556A1), hereinafter Tessariol, in view of Zhang et. al. (US220210296232A1), hereinafter Zhang, with support from US Patent (US9941209B2) corresponds to US20170263556A1.
Regarding claim 25, Tessariol teaches a memory device (Fig 2 conductive structure 100, [0021]), comprising: a stack structure (Fig 2 stair step structure 106, 108, 110, [0032]) comprising tiers each comprising a conductive material (Fig 2 conductive materials 103, [0026]) and an insulative material (Fig 2 insulative materials 105, [0026]) vertically neighboring the conductive material (Fig 2 conductive materials 103, [0026]), the stack structure (Fig 2 stair step structure 106, 108, 110, [0032]) divided into blocks (not shown, [0021]) extending in parallel in a first direction and separated from one another in a second direction (See annotated drawing) by dielectric slot structures (Fig 4 stack slot element 240, [0047]), each of the blocks (Fig 3 conductive structure 200, [0039]) comprising: an upper stadium structure (Fig 2 stair step structure 106, [0032]) comprising opposing staircase structures (Fig 2 opposing stair step structure 107, [0032]) having steps comprising edges of an upper group of the tiers of the stack structure, the upper stadium structure (Fig 2 stair step structure 106, [0032]) extending in the second direction (See annotated drawing) from and between two of the dielectric slot structures (Fig 4 stack slot element 240, [0047]); lower stadium structures (Fig 2 stair step structure 108, [0032]) vertically below the upper stadium structure (Fig 2 stair step structure 106, [0032]) and each comprising additional opposing staircase structures (Fig 2 opposing stair step structure 109, [0032]) having additional steps comprising edges of a lower group of the tiers of the stack structure; crest regions (Fig 2 landings 112, [0027]) interposed between the lower stadium (Fig 2 stair step structure 108, [0032]) structures in the first direction (See annotated drawing); and strings of memory cells (Fig 2 semiconductor device 102 , [0026]) vertically extending through a portion of each of the blocks neighboring the upper stadium structure (Fig 2 stair step structure 106, [0032]) in the first direction (See annotated drawing).
Tessariol fails to teach the upper stadium structure being relatively wider than the lower stadium structures in the second direction, and bridge regions integral with the crest regions and interposed between the lower stadium structures and the two of the dielectric slot structures in the second direction, a first bridge region of the bridge regions exhibiting a different length in the first direction than a second bridge region of the second bridge region.
However, Zhang teaches bridge regions (Fig 6A bridge structure 614, [0061]) integral with the crest regions (Fig 6A area between staircases in X direction corresponds to Tessariol: Fig 2 landings 112, [0027]) and interposed between the lower stadium structures (Fig 6A staircase 610-1, [0061] corresponds to Tessariol: Fig 2 stair step structure 108, [0032]) and the two of the dielectric slot structures (The bridge structure can be multilayered to include conductive and dielectric layers, [0088] corresponds to Tessariol: Fig 4 stack slot element 240, [0047]) in the second direction (Fig 6A y-direction).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol to incorporate the teachings of Zhang by having two bridge regions interposed between the lower stadium structure and the two of the dielectric slot structures in the first horizontal direction and extending from and between the two crest regions in the second horizontal direction, the two bridge regions having upper surfaces substantially coplanar with upper surfaces of the two crest regions. This would allow for electrical connection between different staircase structures ([0006]). Zhang further teaches that the staircase zones can be formed at different depths ([0008]). In applying the teachings of Zhang to the lower stadium structure, the upper stadium structure would be wider than the lower stadium structure by the width of the bridge regions. Further, during production to form the combination of Tessariol and Zhang, manufacturing tolerances would result in a first bridge region of the bridge regions exhibiting a different length in the first direction than a second bridge region of the second bridge region. Examiner notes that since there is no degree of difference, different horizontal widths, can be interpreted to mean that even a couple atoms difference between the two bridge regions meets the limitations of the claim.
It is noted for clarity of the record that Tessariol teaches one semiconductor device but teaches that an electronic device can include one or more portions of conductive structures ([0021]).
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Regarding claim 28, Tessariol teaches within each of the blocks (Fig 3 conductive structure 200, [0039]) of the stack structure (Fig 2 stair step structure 106, 108, 110, [0032]): a first group of conductive contact structures (not shown but would use Fig 2 access lines 132, [0033]) landing on at least some of the steps of the opposing staircase structures (Fig 2 opposing stair step structure 107, [0032]) of the upper stadium structure (Fig 2 stair step structure 106, [0032]); and a second group of conductive contact structures (not shown but would use Fig 2 access lines 132, [0033]) landing on at least some of the additional steps of the additional opposing staircase structures (Fig 2 opposing stair step structure 107, [0032]) of each of the lower stadium structures (Fig 2 stair step structure 108, [0032]).
Claims 26, 27, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Tessariol et. al. (US20170263556A1), hereinafter Tessariol, in view of Zhang et. al. (US220210296232A1), hereinafter Zhang, with support from US Patent (US9941209B2) corresponds to US20170263556A1, in further view of Matovu et. al. (US20200203220A1), hereinafter Matovu, with support from Huang et. al. (US2006246686A1), hereinafter Huang.
Regarding claim 26, Tessariol and Zhang fail to teach within each of the blocks of the stack structure: a first filled trench vertically overlying and within horizontal boundaries of the upper stadium structure, the first filled trench comprising multiple dielectric materials; and second filled trenches vertically overlying and within horizontal boundaries of the lower stadium structures, each of the second filled trenches comprising multiple additional dielectric materials.
However, Matovu teaches within each of the blocks (Fig 2 stair step structure 200, [0022] corresponds to Tessariol: Fig 3 conductive structure 200, [0039]) of the stack structure (Fig 3A stack 305, [0025] corresponds to Tessariol: Fig 2 stair step structure 106, 108, 110, [0032]): a first filled trench (Fig 3G valley 325 from Fig 3E is filled) vertically overlying and within horizontal boundaries (Bottom most portion of semiconductor structure 300) of the upper stadium structure (Fig 3D stair step structure 320, [0038] corresponds to Tessariol: Fig 2 stair step structure 106, [0032]), the first filled trench comprising multiple dielectric materials (multiple dielectric materials listed, [0042] and [0047]); and second filled trenches (Fig 3G valley 325 from Fig 3E is filled) vertically overlying and within horizontal boundaries (Bottom most portion of semiconductor structure 300) of the lower stadium structures (Fig 3D stair step structure 320, [0038] corresponds to Tessariol: Fig 2 stair step structure 108, [0032]), each of the second filled trenches (Fig 3G valley 325 from Fig 3E is filled) comprising multiple additional dielectric materials (multiple dielectric materials listed, [0042] and [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol and Zhang to incorporate the teachings of Matovu by having within each of the blocks of the stack structure : a first filled trench vertically overlying and within horizontal boundaries of the upper stadium structure, the first filled trench comprising multiple dielectric materials; and second filled trenches vertically overlying and within horizontal boundaries of the lower stadium structures, each of the second filled trenches comprising multiple additional dielectric materials. This would reduce failure rate of staircase structures of semiconductor devices formed as compared to conventional methods ([0014]).
It is noted for clarity of the record that though Matovu teaches one stair step structure, one having ordinary skill in the art before the effective filing date of the claimed invention could apply this method to all the stair step structures.
Regarding claim 27, Tessariol and Zhang fail to teach at least one of the multiple dielectric materials of the first filled trench has a different material composition than any of the multiple additional dielectric materials of the each of the second filled trenches.
With regards to at least one of the multiple dielectric materials of the first filled trench has a different material composition than any of the multiple additional dielectric materials of the each of the second filled trenches. Matovu teaches multiple dielectric materials ([0042] and [0047]) that can be used to fill trenches. One of ordinary skill in the art before the effective filing date of the claimed invention could have chosen from the different dielectric materials such that the material composition of the first filled trench would be different from the second filled trench. In choosing the different combination there would be a reasonable expectation of success since the materials are known in the art. Further, Huang teaches that using different materials for different etch stop layers can help in reducing stresses placed on the semiconductor devices by choosing the appropriate material properties for a given region ([0006] and [0007]).
Regarding claim 29, Tessariol and Zhang fail to teach digit lines overlying the stack structure and coupled to the strings of memory cells; a source structure underlying the stack structure and coupled to the strings of memory cells; conductive routing structures coupled to the first group of conductive contact structures and the second group of conductive contact structures; and control logic circuitry underlying the stack structure and coupled to the source structure, the digit lines, and the conductive routing structures.
However, Matovu teaches digit lines (Fig 1 data lines 102, [0015]) overlying the stack structure (Fig 1 conductive tiers 105, [0015] corresponds to Tessariol: Fig 2 stair step structure 106, 108, 110, [0032]) and coupled to the strings of memory cells (Fig 1 memory cells 103, [0015] corresponds to Tessariol: Fig 2 semiconductor device 102, [0021]); a source structure (Fig 1 source tier 104, [0015]) underlying the stack structure (Fig 1 conductive tiers 105, [0015] corresponds to Tessariol: Fig 2 stair step structure 106, 108, 110, [0032]) and coupled to the strings of memory cells (Fig 1 memory cells 103, [0015] corresponds to Tessariol: Fig 2 semiconductor device 102, [0021]); conductive routing structures (Fig 1 select lines 109, [0015]) coupled to the first group of conductive contact structures (Fig 1 vertical conductive contacts, [0015]) and the second group of conductive contact structures (Fig 1 vertical conductive contacts, [0015]); and control logic circuitry (Fig 1 control unit 112, [0016] corresponds to Tessariol: Fig 2 control units 130, [0031]) underlying the stack structure (Fig 1 conductive tiers 105, [0015] corresponds to Tessariol: Fig 2 stair step structure 106, 108, 110, [0032]) and coupled to the source structure (Fig 1 source tier 104, [0015]), the digit lines (Fig 1 data lines 102, [0015]), and the conductive routing structures (Fig 1 select lines 109, [0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol and Zhang to incorporate the teachings of Matovu by having digit lines overlying the stack structure and coupled to the strings of memory cells; a source structure underlying the stack structure and coupled to the strings of memory cells; conductive routing structures coupled to the first group of conductive contact structures and the second group of conductive contact structures; and control logic circuitry underlying the stack structure and coupled to the source structure, the digit lines, and the conductive routing structures. This would enable access to the semiconductor device for use as a memory device ([0015]).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Tessariol et. al. (US20170263556A1), hereinafter Tessariol, in view of Zhang et. al. (US220210296232A1), hereinafter Zhang.
Tessariol teaches an electronic system (Fig 10 electronic system 400, [0059]), comprising: an input device (Fig 10 input device 404, [0059]); an output device (Fig 10 output device 406, [0059]); a processor device (Fig 10 electronic signal processor device 402, [0059]) operably coupled to the input device (Fig 10 input device 404, [0059]) and the output device (Fig 10 output device 406, [0059]); and a memory device (Fig 10 electronic device 401, [0059]) operably coupled to the processor device (Fig 10 electronic signal processor device 402, [0059]) and comprising ([0059]) at least one microelectronic device structure (Fig 2 conductive structure 100, [0021]) comprising: a stack structure (Fig 2 stair step structure 106, 108, 110, [0032]) having a vertically alternating sequence of conductive material (Fig 2 conductive materials 103, [0026]) and insulative material (Fig 2 insulative materials 105, [0026]) arranged in tiers, the stack structure (Fig 2 stair step structure 106, 108, 110, [0032]) comprising blocks (Fig 3 conductive structure 200, [0039]) separated from one another by dielectric slot structures (Fig 4 stack slot element 240, [0047]), at least one of the blocks (Fig 3 conductive structure 200, [0039]) comprising: an upper stadium structure (Fig 2 stair step structure 106, [0032]) comprising opposing staircase structures (Fig 2 opposing stair step structure 107, [0032]) having steps comprising edges of an upper group of the tiers of the stack structure (Fig 2 stair step structure 106, 108, 110, [0032]), the upper stadium structure (Fig 2 stair step structure 106, [0032]) extending in a first direction (See annotate figure) from and between two of the dielectric slot structures (Fig 4 stack slot element 240, [0047]); lower stadium structures (Fig 2 stair step structure 108, [0032]) vertically below the upper stadium structure (Fig 2 stair step structure 106, [0032]) and each comprising additional opposing staircase structures (Fig 2 stair step structure 109, [0032]) having additional steps comprising edges of a lower group of the tiers of the stack structure (Fig 2 stair step structure 106, 108, 110, [0032]); first elevated regions (Fig 2 landings 112, [0027]) intervening between the lower stadium structures (Fig 2 stair step structure 108, [0032]) in a second direction (See annotated figure) orthogonal to the first direction (See annotated figure) ; conductive contact structures (Fig 2 access lines 132, [0033]) landing on the steps and the additional steps (not shown, [0033]) of the at least one of the blocks (Fig 3 conductive structure 200, [0039]); and strings of memory cells (Fig 2 semiconductor device 102 , [0026]) vertically extending through the at least one of the blocks (Fig 3 conductive structure 200, [0039]).
Tessariol fails to teach second elevated regions integral with the first elevated regions and interposed between the lower stadium structures and the two of the dielectric slot structures in the first direction and not interposed between the upper stadium structures and the two of the dielectric slot structures.
However, Zhang teaches teach second elevated regions (Fig 6A bridge structure 614, [0061]) integral with the first elevated regions (Fig 6A area between staircases in X direction corresponds to Tessariol: Fig 2 landings 112, [0027]) and interposed between the lower stadium structures (Fig 6A staircase 610-1, [0061] corresponds to Tessariol: Fig 2 stair step structure 108, [0032]) and the two of the dielectric slot structures (The bridge structure can be multilayered to include conductive and dielectric layers, [0088] corresponds to Tessariol: Fig 4 stack slot element 240, [0047]) in the first direction (Fig 6A y-direction).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tessariol to incorporate the teachings of Zhang by having second elevated regions integral with the first elevated regions and interposed between the lower stadium structures and the two of the dielectric slot structures in the first direction. This would allow for electrical connection between different staircase structures ([0006]). Zhang further teaches that the staircase zones can be formed at different depths ([0008]). In applying the bridge regions of Zhang to the lower stadium structure, the upper stadium structure would be lacking the bridge regions, i.e. there would be second elevated regions integral with the first elevated regions and not interposed between the upper stadium structures and the two of the dielectric slot structures.
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Allowable Subject Matter
Claims 10 – 24 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, the closest prior art is Tessariol et. al. (US20170263556A1), hereinafter Tessariol, in view of Zhang et. al. (US20210296232A1), hereinafter Zhang, in further view of Matovu et. al. (US20200203220A1), hereinafter Matovu.
Tessariol teaches a microelectronic device (Fig 2 conductive structure 100, [0021]), comprising: a stack structure (Fig 2 stair step structure 106, 108, 110, [0032]) comprising blocks (not shown, [0021]) separated from one another by dielectric slot structures (Fig 4 stack slot element 240, [0047]) and each including a vertically alternating (Fig 2 top left corner for clarity, [0026]) sequence of conductive structures (Fig 2 conductive materials 103, [0026]) and insulative structures (Fig 2 insulative materials 105, [0026]) arranged in tiers (Fig 2 stair step structure 106, 108, 110, [0032]), at least one of the blocks (Fig 3 conductive structure 200, [0039]) comprising: an upper stadium structure (Fig 2 stair step structure 106, [0032]) extending in a first horizontal direction (See annotated figure of claim 1) from and between two of the dielectric slot structures (Fig 4 stack slot element 240, [0047]), the upper stadium structure (Fig 2 stair step structure 106, [0032]) comprising staircase structures (Fig 2 stair step structure 106, [0032]) having steps comprising edges of some of the tiers; two crest regions (Fig 2 landings 112, [0027]) offset from the upper stadium structure (Fig 2 stair step structure 106, [0032]) in a second horizontal direction (See annotated figure of claim 1) orthogonal to the first horizontal direction (See annotated figure of claim 1); a lower stadium structure (Fig 2 stair step structure 108, [0032]) vertically below the upper stadium structure (Fig 2 stair step structure 106, [0032]) and interposed between the two crest regions (Fig 2 landings 112, [0027]) in the second horizontal direction (See annotated figure of claim 1), the lower stadium structure (Fig 2 stair step structure 108, [0032]) comprising additional staircase structures (Fig 2 stair step structure 108, [0032]) having additional steps comprising edges of some other of the tiers.
Tessariol fails to teach two bridge regions interposed between the lower stadium structure and the two of the dielectric slot structures in the first horizontal direction and extending from and between the two crest regions in the second horizontal direction, the two bridge regions having upper surfaces substantially coplanar with upper surfaces of the two crest regions; a filled trench vertically overlying and within a horizontal area of the upper stadium structure of the at least one of the blocks, the filled trench comprising: a first dielectric liner on the staircase structures of the upper stadium structure and extending in the first horizontal direction from and between two of the dielectric slot structures; a second dielectric liner on the first dielectric liner and having a different material composition than the first dielectric liner; and a first dielectric fill material on the second dielectric liner an additional filled trench vertically overlying and within a horizontal area of the lower stadium structure of the at least one of the blocks, the additional filled trench comprising: a third dielectric liner on the additional staircase structures of the lower stadium structure and on lower portions of inner sidewalls of the two bridge regions; and a fourth dielectric liner on the third dielectric liner and having a different material composition than the third dielectric liner; and a second dielectric fill material on the fourth dielectric liner, wherein the additional filled trench further comprises: a fifth dielectric liner vertically overlying the third dielectric liner and on upper portions of the inner sidewalls of the two bridge regions; and a sixth dielectric liner on the fifth dielectric liner and having a different material composition than the fifth dielectric liner; and a third dielectric fill material on the sixth dielectric liner.
However, Zhang teaches two bridge regions (Fig 6A bridge structure 614, [0061]) interposed between the lower stadium structure (Fig 6A staircase 610-1, [0061] corresponds to Tessariol: Fig 2 stair step structure 108, [0032]) and the two of the dielectric slot structures (The bridge structure can be multilayered to include conductive and dielectric layers, [0088] corresponds to Tessariol: Fig 4 stack slot element 240, [0047]) in the first horizontal direction (See annotated figure) and extending from and between the two crest regions (Fig 6A area between staircases in X direction corresponds to Tessariol: Fig 2 landings 112, [0027]) in the second horizontal direction (See annotated figure), the two bridge regions (Fig 6A bridge structure 614, [0061]) having upper surfaces substantially coplanar (Fig 6A upper surfaces are coplaner) with upper surfaces of the two crest regions (Fig 6A area between staircases in X direction corresponds to Tessariol: Fig 2 landings 112, [0027]).
Tessariol and Zhang fail to teach a filled trench vertically overlying and within a horizontal area of the upper stadium structure of the at least one of the blocks, the filled trench comprising: a first dielectric liner on the staircase structures of the upper stadium structure and extending in the first horizontal direction from and between two of the dielectric slot structures; a second dielectric liner on the first dielectric liner and having a different material composition than the first dielectric liner; and a first dielectric fill material on the second dielectric liner an additional filled trench vertically overlying and within a horizontal area of the lower stadium structure of the at least one of the blocks, the additional filled trench comprising: a third dielectric liner on the additional staircase structures of the lower stadium structure and on lower portions of inner sidewalls of the two bridge regions; and a fourth dielectric liner on the third dielectric liner and having a different material composition than the fourth dielectric liner; and a second dielectric fill material on the fourth dielectric liner, wherein the additional filled trench further comprises: a fifth dielectric liner vertically overlying the third dielectric liner and on upper portions of the inner sidewalls of the two bridge regions; and a sixth dielectric liner on the fifth dielectric liner and having a different material composition than the fifth dielectric liner; and a third dielectric fill material on the sixth dielectric liner.
However, Matovu teaches a filled trench vertically (Fig 3G valley 325 from Fig 3E is filled) overlying and within a horizontal area (Bottom most portion of semiconductor structure 300) of the upper stadium structure (Fig 3D stair step structure 320, [0038] corresponds to Tessariol: Fig 2 stair step structure 106, [0032]) of the at least one of the blocks (Fig 2 stair step structure 200, [0022] corresponds to Tessariol: Fig 3 conductive structure 200, [0039]), the filled trench comprising: a first dielectric liner (Fig 3E first liner 326, [0042]) on the staircase structures (Fig 3D stair step structure 320, [0038] corresponds to Tessariol: Fig 2 stair step structure 106, [0032]) of the upper stadium structure (Fig 3D stair step structure 320, [0038] corresponds to Tessariol: Fig 2 stair step structure 106, [0032]) and extending in the first horizontal direction from and between two of the dielectric slot structures; a second dielectric liner (Fig 3E second liner 328, [0042]) on the first dielectric liner (Fig 3E first liner 326, [0042]) and having a different material composition (different materials listed, [0042]) than the first dielectric liner (Fig 3E first liner 326, [0042]); and a first dielectric fill material (Fig 3G insulative material 330, [0045]) on the second dielectric liner (Fig 3E second liner 328, [0042]).
Tessariol, Zhang and Matovu fail to teach the additional filled trench further comprises: a fifth dielectric liner vertically overlying the third dielectric liner and on upper portions of the inner sidewalls of the two bridge regions; and a sixth dielectric liner on the fifth dielectric liner and having a different material composition than the fifth dielectric liner; and a third dielectric fill material on the sixth dielectric liner.
Claims 11 – 14 would be allowable because they are dependent on claim 10.
Regarding claim 15, the closest prior art is Tessariol et. al. (US20170263556A1), hereinafter Tessariol.
Tessariol teaches a method of forming a microelectronic device (Fig 2 semiconductor device 102, [0021]), comprising: forming a preliminary stack structure (Fig 5 stack of material 300, [0051]) comprising a vertically alternating sequence of sacrificial material (Fig 5 sacrificial materials 306, [0051]) and insulative material (Fig 5 insulative materials 304, [0051]) arranged in tiers (formed concurrently with the forming of the stair step structure, [0051]).
Claim 15 would be allowable for disclosing the preliminary stack structure further comprising: rows of lower stadium structures extending in parallel in a first horizontal direction and each comprising two of the lower stadium structures substantially aligned with another in a second horizontal direction orthogonal to the first horizontal direction, each of the lower stadium structures having steps comprising edges of a lower group of the tiers of the preliminary stack structure; and a preliminary upper stadium structure vertically overlying the rows of lower stadium structures and comprising additional staircase structures having additional steps comprising edges of an upper group of the tiers of the preliminary stack structure, the preliminary upper stadium structure continuously extending in the second horizontal direction across multiple of the rows of lower stadium structures; dividing the preliminary stack structure into blocks separated from one another by slots, each of the blocks comprising: an upper stadium structure comprising a portion of the preliminary upper stadium structure, the upper stadium structure extending in the second horizontal direction from and between two of the slots; one of the rows of lower stadium structures; a crest region interposed between the two of the lower stadium structures of the one of the rows of lower stadium structures in the first horizontal direction; and bridge regions integral with the crest region and interposed between the two of the lower stadium structures and the two of the slots in the second horizontal direction; and replacing the sacrificial material of the preliminary stack structure with conductive material by way of the slots.
Claims 16 – 24 would be allowable because they are dependent on claim 15.
Response to Arguments
Applicant's arguments, see 35 USC §103 section for claim 1 starting on page 14, filed January 28, 2026, with respect to the bridge structure of Zhang not being combined with Tessariol, have been fully considered but they are not persuasive.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Examiner has provided such a motivation disclosed in the rejection above, of wanting to allow electrical connection. Examiner notes that Zhang also teaches gate line slits (Fig 3 GLS 308, [0036] and Fig 5 GLS 506, [0057]) as separators between bridge structures (Fig 5 bridge structure 510, [0057]). One having ordinary skill in the art before the effective filing date of the claimed invention would recognize the GLS as corresponding to the dielectric slot structure of Tessariol.
Applicant's arguments, see 35 USC §103 section for claim 1 starting on page 15, filed January 28, 2026, with respect to the bridge structure of Zhang being applied to all stadium structures and not limited to lower stadium structures have been fully considered but they are not persuasive.
Examiner notes that Zhang teaches peripheral regions (Fig 3 peripheral region 303, [0037]) with top select gates (not shown). These peripheral regions have cut staircases which do not include bridge structures (Fig 3). Tessariol teaches the steps of the top most stadium (upper stadium of instant invention) may act as or act to select word lines plates, bit lines, selection gates ([0026]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the peripheral region of Zhang would correspond to the top most stadium of Tessariol, such that a bridge structure is not needed for the upper stadium.
Applicant's arguments, see 35 USC §103 section for claim 2 starting on page 16, filed January 28, 2026, with respect to the additional dielectric slot structures have been fully considered but they are not persuasive.
Examiner notes the additional dielectric slot structures (inner stack slot elements 238) were directed to Fig 4 and the “inner stack slot elements 238,” while not directly pointed out, can be seen in Fig 3. References to Fig 2 were for better illustration of the stadium structures. Fig 4 shows a step structure 206 and 207, which corresponds ([0038]) to step structure 106 and 107 of Fig 2. However, since the view is planar, a side view was chosen to show the upper stadium structure. Further, [0043] and [0048] of Tessariol, as previously mentioned in both the current rejection and the rejection of the office action dated October 30, 2025, discloses the stack slot elements 238 may be formed in the conductive structure 200. The mention of insulative material 314 was meant to convey the material of the inner stack slot element 238 can be the same as that of the insulative material 314, as the reference to [0055] of Tessariol discloses.
Applicant's arguments, see 35 USC §103 section for claim 25 starting on page 18, filed January 28, 2026, with respect to the width differences have been fully considered but they are not persuasive.
Examiner notes, similar to the previous reply, that Zhang teaches peripheral regions (Fig 3 peripheral region 303, [0037]) with top select gates (not shown). These peripheral regions have cut staircases which do not include bridge structures (Fig 3). Tessariol teaches the steps of the top most stadium (upper stadium of instant invention) may act as or act to select word lines plates, bit lines, selection gates ([0026]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the peripheral region of Zhang would correspond to the top most stadium of Tessariol, such that a bridge structure is not needed for the upper stadium.
Further, Examiner notes that, as previously mentioned in both the current rejection and the rejection of the office action dated October 30, 2025, since there is no degree of difference, different horizontal widths, can be interpreted to mean that even a couple atoms difference between the two bridge regions meets the limitations of the claim.
Applicant's arguments, see 35 USC §103 section for claim 30 starting on page 20, filed January 28, 2026, with respect to the combination of Tessariol and Zhang have been fully considered but they are not persuasive.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Examiner notes, similar to the previous reply, that Zhang teaches peripheral regions (Fig 3 peripheral region 303, [0037]) with top select gates (not shown). These peripheral regions have cut staircases which do not include bridge structures (Fig 3). Tessariol teaches the steps of the top most stadium (upper stadium of instant invention) may act as or act to select word lines plates, bit lines, selection gates ([0026]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the peripheral region of Zhang would correspond to the top most stadium of Tessariol, such that a bridge structure is not needed for the upper stadium and would be between the lower stadium structures.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Conti et. al (US 20260040550 A1) discloses a similar structure.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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