DETAILED ACTION
This Notice is responsive to communication filed on 03/09/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 03/09/2026 under 37 CFR 1.111 has been entered. Claims 1, 3-9 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20220068193), and further in view of Rovitto (2017) and Kang et al. (US 20090224262).
Regarding claim 1, Wang discloses:
A micro light emitting diode panel (Fig. 1, 7), comprising:
a circuit substrate Fig. 7: 120, comprising:
a plurality of signal lines Fig. 1: SL/DL, composed of a plurality of metal conductive layers Fig. 7: 131 (para. 0052) and defining a plurality of pixel areas Fig. 1: 110;
a plurality of bonding pads Fig. 7: PD/132 (para. 0050), extending from at least part of the signal lines Fig. 1: SL/DL; and
a plurality of thin film transistors Fig. 1: T1, formed on the circuit substrate Fig. 7: 120,
wherein each of the thin film transistors Fig. 7: T1 has a first semiconductor pattern (para. 0060 teaches T1, a TFT has a larger on-resistance; para. 0045 teaches T1 may also be an FET which can be a MOSFET (para. 0043)) and a plurality of electrodes Fig. 7: S1/D1/G1 composed of the metal conductive layers Fig. 7: 131, and
the electrodes Fig. 7: S1/D1/G1 are electrically connected to at least part of the bonding pads Fig. 7: PD/132 (shown in Fig. 7);
a plurality of solder bumps, each separated from the others and contacting the plurality of bonding pads on the same side away from the circuit substrate;
a plurality of transistor elements Fig. 1: T2, electrically bonded to a part of the bonding pads Fig. 7: PD/132 to be electrically connected to the thin film transistors Fig. 7: T1 (para. 0034); and
a plurality of micro light emitting diodes Fig. 1: 112, electrically bonded to another part of the bonding pads Fig. 7: PD/132 via the plurality of solder bumps (i.e. Fig. 7: 132/PD), and electrically connected to the thin film transistors (para. 0034),
wherein each of the pixel areas Fig. 1: 110 is provided with at least one thin film transistor Fig. 1: T1, at least one transistor element Fig. 1: T2, and at least one micro light emitting diode Fig. 1: 112,
each of the transistor elements Fig. 7: T2 has a second semiconductor pattern (para. 0043, channel material – polysilicon; teaches small on-resistance), and
an electron mobility difference between the first semiconductor pattern and the second semiconductor pattern is greater than 30 cm2/V-s;
wherein all of the transistor elements Fig. 7: T2 and all of the micro light emitting diodes Fig. 7: 112 are disposed on the same side of the plurality of solder bumps (i.e. Fig. 7: 132/PD), away from the plurality of bonding pads Fig. 7: 132/PD,
wherein the plurality of transistor elements Fig. 7: T2 and the plurality of micro light emitting diodes Fig. 7: 112 are structurally separated and bonded to the circuit substrate via different solder bumps (i.e. Fig. 7: 132/PD), and
the plurality of transistor elements Fig. 7: T2, the plurality of micro light emitting diodes Fig. 7: 112 and the plurality of thin film transistors Fig. 7: T1 do not overlap with each other along a direction perpendicular to the circuit substrate Fig. 7: 120 (shown in Fig. 6).
Rovitto discloses the following claim limitations not explicitly disclosed by Wang:
a plurality of solder bumps, each separated from the others and contacting the plurality of bonding pads on the same side away from the circuit substrate (Section 1.3.2);
Wang teaches a bonding layer Fig. 7: 132 that includes bonding pads Fig. 7: PD which are
separated from each other on a side of the layers away from the circuit substrate. Rovitto teaches, and it is also common in the art, where chip pads can be metallized on an IC, in a wafer processing step, and solder bumps are deposited on each of the chip pads, and also aligned to the bond pads on the substrate. Fig. 1: 9 shows this process.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention that the bonding layer Fig. 7: 132 and the bonding pads Fig. 7: PD of Wang’s invention also includes a solder bump according to Rovitto’s teachings, in order to provide electrically and thermally conductive paths to carry electrical current and heat from the chip to the substrate, guaranteeing mechanical support during the mounting of the die (or other elements) to the substrate (Rovitto, Section 1.3.2).
Kang discloses the following claim limitations not disclosed by Wang:
an electron mobility difference between the first semiconductor pattern and the second semiconductor pattern is greater than 30 cm2/V-s (para. 0008);
Kang teaches the (“The amorphous silicon TFT has electrical charge mobility of about 0.5-1.0 cm^2/V-sec, and, therefore, it can be used as a switching element”; “To overcome this problem, a polycrystalline silicon TFT using polycrystalline silicon having electrical charge mobility of about 20-150 cm^2/V-sec as semiconductor pattern is developed”). The ranges taught in Kang can be applied to meet the difference of greater than 30cm^2/V-s as claimed in the current application.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the micro-LEDs of Kim with the electron mobility difference as described by Kang in order to create sufficient electrical charge mobility without increasing the size of the driving circuit (para. 0017).
Regarding claim 3, Wang teaches the micro light emitting diode panel according to claim 1, wherein the electrodes Fig. 7: S1/D1/G1 of each of the thin film transistors Fig. 7: T1 comprise a source Fig. 7: S1, a drain Fig. 7: D1, and a gate Fig. 7: G1, the source Fig. 7: S1 and the drain Fig. 7: D1 are electrically connected to the first semiconductor pattern, the signal lines comprise a plurality of scan lines Fig. 7: SL and a plurality of data lines Fig. 7: DL, the source Fig. 7: S1, the drain Fig. 7: D1, and the data lines Fig. 7: DL are a same film layer (shown in Fig. 7), and the gate Fig. 7: G1 and the scan lines Fig. 7: SL are a same film layer (shown in Fig. 7).
Regarding claim 4, Kang discloses the following claim limitations not disclosed by Wang:
wherein an electron mobility of the first semiconductor pattern of each of the thin
film transistors is less than or equal to 20 cm2/V-s (para. 0008; “The amorphous silicon TFT has electrical charge mobility of about 0.5-1.0 cm^2/V-sec, and, therefore, it can be used as a switching element).
The range taught in Kang can be applied to meet the less than or equal to 20cm^2/V-s as claimed in the current application.
Regarding claim 5, Kang discloses:
The micro light emitting diode panel according to claim 1:
wherein each of the transistor elements Fig. 7: T2 further has a source Fig. 7: S1, a drain Fig. 7: D1, and a gate Fig. 7: G1, and the source Fig. 7: S1 and the drain Fig. 7: G1 are electrically connected to the second semiconductor pattern (shown in Fig. 7),
wherein the source Fig. 7: S1, the drain Fig. 7: D1, and the gate Fig. 7: G1 are located between the second semiconductor pattern (which is part of the T2 body) and the circuit substrate Fig. 7: 120, and
an electron mobility of the second semiconductor pattern of each of the transistor elements is greater than 50 cm2/V s.
Kang discloses the following claim limitation not disclosed by Wang:
an electron mobility of the second semiconductor pattern of each of the transistor elements is greater than 50 cm2/V s.
(para. 0008-0009, “However, it is not proper to use the amorphous silicon TFTs for a
driving circuit directly on the liquid crystal panel due to its insufficient electrical charge mobility. To overcome this problem, a polycrystalline silicon TFT using polycrystalline silicon having electrical charge mobility of about 20-150 cm^2/V-sec as semiconductor pattern is developed”). The range taught in Kang can be applied to meet the greater than 50cm^2/V-s as claimed in the current application.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20220068193), Rovitto (2017) and Kang et al. (US 20090224262) as applied to claim 1 above, and further in view of Kim et al. (US 20180174519).
Regarding claim 6, Kim discloses the following claim limitations not disclosed by Wang:
wherein the circuit substrate has a plurality of pixel circuits Fig. 2: PC disposed between the signal lines Fig. 2: GL, DL, and
each of the pixel circuits Fig. 2: PC comprises: a driving unit, configured to control a driving current flowing through one of the micro light emitting diodes Fig. 2: 300a during a light emitting stage (para 0147, “Tdr1 may be turned on by a voltage of the second node N2 to control the amount of current flowing from the driving power line PL to the first light emitting diode device 300a”); and
a light emission control unit, configured to control the driving current from the driving unit to the one of the micro light emitting diodes during the light emitting stage (para 0149, “emission control transistor Tem1 may be turned on by the emission control signal supplied through the emission control line ECL and may supply a data current, output from the first driving transistor Tdr1, to the first light emitting diode device 300a”),
wherein the light emission control unit is provided with a first thin film transistor Fig. 7: Tem1 of the thin film transistors, and
the driving unit is provided with a first transistor element Fig. 7: Tdr1 of the transistor elements. See annotated Fig. 7 below.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Wang, Kang, and Rovitto with Kim in order to have a pixel circuit with a driving unit to supply the data current and control the amount of current flowing to the LED device (para. 0045, 0147), and a light emission control unit that provides a path for pre-initializing the source electrode of a driving transistor to a reference voltage (para. 0149).
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Regarding claim 7, Kim discloses the following claim limitations not disclosed by Wang:
wherein each of the pixel circuits Fig. 7: PC further comprises a reset unit configured to initialize a voltage of a first terminal Fig. 7: N1 of a storage capacitor Fig. 7: Cst of the driving unit connected to the reset unit during a reset stage (Pg. 11, para 0143-0145; Pg. 12, para 0158-0160),
the driving unit is coupled between the reset unit and the light emission control unit, and
the reset unit is provided with a second transistor element Fig. 7: T2 of the transistor elements (refer to annotated Fig 7 above).
Kim teaches a switching transistor Fig. 7: Tsw connected to the first node Fig. 7: N1 that supplies a data signal from the data line Fig. 7: DL to the first node Fig. 7: N1. Kim also teaches a voltage initialization part Fig. 7: VIP including a second transistor element Fig. 7: T2 that initializes the voltage stored in the storage capacitor Fig. 7: Cst where the second transistor Fig. 7: T2 supplies a reference voltage to the first node Fig. 7: N1 (para 0144, “the switching transistor Tsw may be turned on according to a first gate signal supplied through the first gate line GL1 and may supply a data signal, supplied through the data line DL, to the first node N1”; para. 0160, “second transistor T2 may be turned on by the emission control signal supplied through the emission control line ECL and may supply the reference voltage, supplied through the reference power line RL, to the first node N1.”). Kim also teaches a Storage capacitor Fig. 7: Cst that is connected to a driving transistor Fig. 7: Tdr1 and to the switching transistor Fig. 7: Tsw through the first node Fig. 7: N1. The storage capacitor Fig. 7: Cst stores a voltage corresponding to the data signal from the switching transistor Fig. 7: Tsw, and the voltage from the storage capacitor Fig. 7: Cst is then used to initialize/turn on the first current output part Fig. 7: COP1 which includes the driving transistor Fig. 7: Tdr1 (para 0145, “the storage capacitor Cst may store a voltage corresponding to the data signal from the switching transistor Tsw and may supply the stored voltage to the first current output part COP1”; para 0146, “The first current output part COP1 may include the first driving transistor Tdr1”). Kim in Fig. 7 shows that the reset unit is connected to the driving unit by first node Fig. 7: N1. These teachings and the connections shown in Fig. 7, the switching transistor (Tsw) and the second transistor (T2) can be used to form a reset unit that initializes a voltage of a first terminal (N1) of a storage capacitor (Cst) of the driving unit (including Tdr) connected to the reset unit during a reset stage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Wang, Kang, and Rovitto with Kim in order to provide a unit that initializes a voltage of a first terminal of a storage capacitor of the driving unit (including Tdr) connected to the reset unit during a reset stage (para. 0158).
Regarding claim 8, Kim discloses the following limitation not disclosed by Wang:
wherein each of the pixel circuits further comprises a compensation unit coupled between the light emission control unit and the driving unit, and
the compensation unit is configured to adjust the driving current flowing through the one of the micro light emitting diodes during the light emitting stage and is provided with a second thin film transistor of the thin film transistors.
Para. 0162 discloses “the pixel circuit PC may further include at least one auxiliary
transistor and at least one auxiliary capacitor for compensating for a threshold voltage of a driving transistor, in addition to a switching transistor and a current output part.”
Regarding claim 9, Kim teaches the following limitations not disclosed by Wang:
wherein the compensation unit is further provided with a compensation capacitor connected to a control terminal of the second thin film transistor and a terminal of the second thin film transistor connected to the reset unit.
Para. 0162 discloses the pixel circuit PC may further include at least one auxiliary
transistor and at least one auxiliary capacitor for compensating for a threshold voltage of a driving transistor, in addition to a switching transistor and a current output part.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, and 3-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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