DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/16/2025 has been entered.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Regarding claim 1, under the Alice Framework Step 1 analysis, the claim falls within the four statutory categories of patentable subject matter: a method.
Under the Alice Framework Step 2A Prong 1 analysis, claim 1 recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“a particular comparison operation using floating point values, wherein the particular comparison operation is part of an intersection testing process;
each floating point value is represented with: (i) a sign bit, (ii) a plurality of bits to indicate an exponent, and (iii) a plurality of bits to indicate a significand,
extending an exponent range of the floating point values; one or more of:
(a) replacing a floating point value of zero with a non-zero substitute floating point value whose magnitude is small enough to behave like zero in said particular comparison operation if all other values involved in the particular comparison operation are non-zero finite values that are representable in their input format, wherein said non-zero substitute floating point value has a magnitude that is too small to be representable using the one or more input formats but is representable using the extended exponent range;
(b) shifting one or more of the floating point values by a non-zero amount which is small enough to behave like zero in said particular comparison operation if all other values involved in the particular comparison operation are non-zero finite values that are representable in their input format, wherein said non-zero amount is too small to be representable using the one or more input formats but is representable using the extended exponent range; and
(c) replacing a floating point value of infinity with a finite substitute floating point value whose magnitude is large enough to behave like infinity in said particular comparison operation if all other values involved in the particular comparison operation are non-zero finite values that are representable in their input format, wherein said finite substitute floating point value has a magnitude that is too large to be representable using the one or more input formats but is representable using the extended exponent range;
performing the particular comparison operation using one or more of: (i) the non-zero substitute floating point value, (ii) the one or more shifted floating point values, and (iii) the finite substitute floating point value.”
See specification describing the particular comparison operation ([0080], [0084], [0086]). See specification describing the floating point values ([0090]). See specification describing intersection testing ([0087], [0098], [00110]). See specification describing extending the exponent ([0091]). See specification describing replacing a floating point value of zero ([0094], [0096]). See specification describing the shifting ([00105-00107]). See specification describing the replacing a floating point value of infinity ([00100-00101]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: receiving the floating point values in one or more input formats, outputting a result of the particular comparison operation, a processing module, a processing module implemented as a part of a ray tracing system, and the outputted result of the particular comparison operation is used in the ray tracing system to render an image. A processing module implemented as a part of a ray tracing system is generally linking to a particular technological environment (see MPEP 2106.05(h)(vi)), and is an example of generic computing elements. The outputted result of the particular comparison operation is used in the ray tracing system to render an image generally links to a particular technological environment. The receiving and outputting limitations are examples of insignificant extra solution activity, mere data gathering (see MPEP 2106.05(g): Insignificant Extra-Solution Activity). Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, take alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the claim recites a processing module and implemented as a part of a ray tracing system as merely generally linking and at a high level of generality. The claim further recites “the outputted result of the particular comparison operation is used in the ray tracing system to render an image” which is merely generally linking to a particular technological environment. The limitations described above as insignificant extra-solution activities are also well-understood, routine, or conventional (see MPEP 2106.05(d)(II)(i): Receiving or transmitting data over a network; see MPEP 2106.05(d)(II)(iv): Storing and retrieving information in memory). Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 1 is ineligible.
Under the Alice Framework Step 2A Prong 1 analysis, claim 3 recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“the method”
See specification describing the methods ([00109]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: fixed-function circuitry of the processing module. The fixed-function circuitry of the processing module is generally linking to a particular technological environment (see MPEP 2106.05(h)(vi)), and is an example of generic computing elements. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, take alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the claim recites fixed-function circuitry of the processing module as merely generally linking and at a high level of generality. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 3 is ineligible.
Claims 4-16 merely further limit the mathematical concepts. Claims 4-16 do not recite any new additional elements, however claims 9 and 12 repeat already recited and analyzed additional element “processing module is implemented as part of a ray tracing system”.
Under the Alice Framework Step 2A Prong 1 analysis, claim 17 recites Mathematical Concepts. The claim recites Mathematical Calculations, which is specifically identified as an exemplar in the Mathematical Concepts grouping of abstract ideas:
“performing the particular comparison operation using floating point values of zero or infinity.”
See specification describing performing ([00147], [00163], [00183]). For these reasons, the claim recites Mathematical Concepts.
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: the fixed function circuitry of the processing module does not have exception handling functionality. The fixed function circuitry of the processing module does not have exception handling functionality is generally linking to a particular technological environment (see MPEP 2106.05(h)(vi)), and is an example of generic computing elements. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, take alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the claim recites the fixed function circuitry of the processing module does not have exception handling functionality as merely generally linking, and at a high level of generality. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 17 is ineligible.
Claims 18-19 are directed to a device that would perform the method of claim 1. The claims 1, 17 analysis similarly apply to claims 18-19, and are similarly rejected.
Claim 20 is directed to a computer program product that would perform the method of claim 1. The claim 1 analysis similarly apply to claim 20. Additionally, claim 20 recites the following:
Under the Alice Framework Step 2A Prong 2 analysis, the claim recites the combination of the following additional elements: an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a processing module. The integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a processing module is generally linking to a particular technological environment (see MPEP 2106.05(h)(vi)), and is an example of generic computing elements. Taken alone or in combination, they fail to integrate the judicial exception into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements recited above, take alone or in combination, do not amount to significantly more than the judicial exception. As discussed in the Step 2A Prong 2 analysis, the claim an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a processing module as merely generally linking, and at a high level of generality. Since the claim does not include additional elements that, alone or in combination, amount to significantly more than the judicial exception, claim 20 is ineligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 12-13, 15, 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190369960 A1 Mueller et al. (hereinafter “Mueller”) in view of US 20130321420 A1 Laine et al. (hereinafter “Laine”).
Regarding claim 1, Mueller teaches a method of performing:
in a processing module (Fig. 1, 102 or 106; Fig. 7, 702 or 706; [0085]), a particular comparison operation using floating point values (Fig. 9, 904; [0085]), the method comprising:
receiving the floating point values in one or more input formats ([0038], [0072]), such that each floating point value is represented with: (i) a sign bit, (ii) a plurality of bits to indicate an exponent, and (iii) a plurality of bits to indicate a significand ([0023], mantissa as significand),
extending an exponent range of the floating point values (Fig. 2, 200; [0025], [0040]);
one or more of:
(a) replacing a floating point value of zero with a non-zero substitute floating point value whose magnitude is small enough to behave like zero in said particular comparison operation (Fig. 9, 910, 912; [0090-0091]) if all other values involved in the particular comparison operation are non-zero finite values that are representable in their input format ([0086-0087]), wherein said non-zero substitute floating point value has a magnitude that is too small to be representable using the one or more input formats but is representable using the extended exponent range ([0090-0091]);
(b) shifting one or more of the floating point values by a non-zero amount which is small enough to behave like zero in said particular comparison operation if all other values involved in the particular comparison operation are non-zero finite values that are representable in their input format, wherein said non-zero amount is too small to be representable using the one or more input formats but is representable using the extended exponent range; and
(c) replacing a floating point value of infinity with a finite substitute floating point value whose magnitude is large enough to behave like infinity in said particular comparison operation if all other values involved in the particular comparison operation are non-zero finite values that are representable in their input format, wherein said finite substitute floating point value has a magnitude that is too large to be representable using the one or more input formats but is representable using the extended exponent range; performing the particular comparison operation using one or more of: (i) the non-zero substitute floating point value, (ii) the one or more shifted floating point values, and (iii) the finite substitute floating point value; and
outputting a result of the particular comparison operation ([0085] result to problem).
Although Mueller teaches computing operations on floating-point values (Fig. 9, 904; [0085]), they are silent with disclosing those computation operations including comparison operations. They are further silent with disclosing as part of a ray tracing system; comparison is part of an intersection testing process performed by the ray tracing system, and wherein the comparison is used in the ray tracing system to render an image.
Laine teaches comparison (Fig. 3, 304; [0034]). Further, Laine teaches implemented as part of a ray tracing system ([0005]), wherein the particular comparison (Fig. 3, 304; [0034]) operation is part of an intersection testing process ([abstract], [0032]) performed by the ray tracing system, and wherein the outputted result of the particular comparison operation is used in the ray tracing system to render an image ([0025]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Mueller’s circuitry with Laine’s comparison technique because they are in the claimed invention’s same field of endeavor of calculating with floating-point values ([0006]). Mueller teaches performing operations on floating-point values ([0085]), but is silent to explicitly disclosing comparison operations. It would have been obvious to one of ordinary skill in the art to implement the comparison technique as it allows Mueller’s circuitry to perform more types of operations, as floating-point comparison operations are a known technique in the art (See Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2013. (hereinafter “Patterson”), Pg. 211, floating-point comparison; Pg. 212, MIPS floating-point assembly language, Conditional branch; Pg. 221, Elaboration). Further, with respect to Laine’s ray tracing system, by modifying Mueller’s circuitry to be used in a ray tracing system would have been obvious as floating-point instructions are commonly used in computer graphic systems (Laine, [0002]). Making this modification provides benefit by expanding Mueller’s circuitry to an alternative application and technological environment. Thus, making this modification would be beneficial, as this allows Mueller’s circuity to perform more types of operations and in many other applications of use.
Regarding claim 1, the preamble is given patentable weight. Claim 1 contains the
limitation “the processing module”, “the particular comparison operation”, “the floating point values”, and “ray tracing system” in the body, which is referring to the limitations as recited in the preamble. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of a processing module performing the particular comparison operation using floating point values. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight.
Regarding claim 3, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Mueller teaches the method (see claim 1 mapping):
is performed in fixed-function circuitry (Fig. 7, 714, 716, 718, 720, 722, 724; [0073]; [0034] FPUs) of the processing module (see claim 1 mapping).
The motivation to combine provided with respect to claim 1 equally applies to claim 3.
Regarding claim 3, the preamble is given patentable weight. Claim 3 contains the
limitation “the methods ” in the body, which is referring to the method as recited in the preamble. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the methods recited in claim 1. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 3 should be afforded patentable weight.
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Mueller teaches the method and the particular comparison operation (see claim 1 mapping).
Although Mueller teaches computing operations on floating-point values (Fig. 9, 904; [0085]), they are silent with disclosing comparing the result of multiplying a first floating point value a and a second floating point value b, with the result of multiplying a third floating point value c and a fourth floating point value d.
Laine teaches comparing the result of multiplying a first floating point value a and a second floating point value b, with the result of multiplying a third floating point value c and a fourth floating point value d (Table 1, float x0, y0, z0, x1, y1, z1 as multiplications, float tminbox, tmaxbox as comparisons; [0022]).
The motivation to combine provided with respect to claim 1 equally applies to claim 4.
Regarding claim 12, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Mueller teaches the method, the processing module, and the particular comparison operation (see claim 1 mapping).
Mueller is silent with disclosing as part of a ray tracing system, and wherein the particular comparison operation is part of an intersection testing process to determine whether a ray intersects a box defining a volume within a scene.
Laine teaches as part of a ray tracing system, and wherein the particular comparison operation is part of an intersection testing process (see claim 2 mapping) to determine whether a ray intersects a box defining a volume within a scene ([0004-0006], [0031] 3-dimensional scene, [0032]).
The motivation to combine provided with respect to claim 1 equally applies to claim 12.
Regarding claim 13, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Mueller teaches the method (see claim 1 mapping).
Mueller is silent with disclosing the box is an axis-aligned box defined by, for each axis of the coordinate system in which the scene is represented, two planes each having a respective constant component value along the axis, wherein the method further comprises translating the coordinates of the box by subtracting the component values of a ray origin of the ray, wherein the particular comparison operation comprises comparing, for each of a plurality of edges of the box, values of
b
u
D
v
and
b
v
D
u
, wherein
b
u
and
b
v
are the component values that are constant for the respective two planes which intersect to define the edge of the box, and
D
u
and
D
v
are the components of a ray direction vector of the ray along the axes for which the two intersecting planes are defined, and wherein the method further comprises determining whether the ray intersects the axis-aligned box based on results of the comparisons for the plurality of edges of the box.
Laine teaches the box is an axis-aligned box defined by, for each axis of the coordinate system in which the scene is represented ([0031-0032]), two planes each having a respective constant component value along the axis ([0028]), wherein the method further comprises translating the coordinates of the box by subtracting the component values of a ray origin of the ray (Table 1, //Plane intersections – OoD[x], OoD[y], OoD[z]), wherein the particular comparison operation comprises comparing, for each of a plurality of edges of the box, values of
b
u
D
v
and
b
v
D
u
(Table 1, //Plane intersections – B.xmin*invD[x], B.ymin*invD[y], B.zmin*invD[z], B.xmax*invD[x], B.ymax*invD[y], B.zmax*invD[z]), wherein
b
u
and
b
v
are the component values that are constant for the respective two planes which intersect to define the edge of the box (Table 1, DEFINITIONS B =), and
D
u
and
D
v
are the components of a ray direction vector of the ray along the axes for which the two intersecting planes are defined (Table 1, DEFINITIONS D =), and wherein the method further comprises determining whether the ray intersects the axis-aligned box based on results of the comparisons for the plurality of edges of the box (Table 1, //Overlap test; [0032-0033]).
The motivation to combine provided with respect to claim 1 equally applies to claim 13.
Regarding claim 15, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Mueller teaches the method and the particular comparison operation (see claim 1 mapping).
Mueller is silent with disclosing the box is an axis-aligned box defined by, for each axis of the coordinate system in which the scene is represented, two planes each having a respective constant component value along the axis, wherein the method further comprises translating the coordinates of the box by subtracting the component values of a ray origin of the ray, wherein floating point values defining the components of a ray direction vector of the ray are received as reciprocal values, wherein the particular comparison operation comprises comparing, for each of a plurality of edges of the box, values of
b
u
(
1
D
u
)
and
b
v
1
D
v
, wherein
b
u
and
b
v
are the component values that are constant for the respective two planes which intersect to define the edge of the box, and
1
D
u
and
1
D
v
are the reciprocals of the components of the ray direction vector of the ray along the axes for which the two intersecting planes are defined, and wherein the method further comprises determining whether the ray intersects the axis-aligned box based on results of the comparisons for the plurality of edges of the box.
Laine teaches the box is an axis-aligned box defined by, for each axis of the coordinate system in which the scene is represented, two planes each having a respective constant component value along the axis, wherein the method further comprises translating the coordinates of the box by subtracting the component values of a ray origin of the ray, wherein floating point values (see claim 13 mapping) defining the components of a ray direction vector of the ray are received as reciprocal values (Table 1, DEFINITIONS invD =), wherein the particular comparison operation comprises comparing, for each of a plurality of edges of the box, values of
b
u
(
1
D
u
)
and
b
v
1
D
v
(Table 1, //Plane intersections – B.xmin*invD[x], B.ymin*invD[y], B.zmin*invD[z], B.xmax*invD[x], B.ymax*invD[y], B.zmax*invD[z]), wherein
b
u
and
b
v
are the component values that are constant for the respective two planes which intersect to define the edge of the box (Table 1, DEFINITIONS B =), and
1
D
u
and
1
D
v
are the reciprocals of the components of the ray direction vector of the ray along the axes for which the two intersecting planes are defined (Table 1, DEFINITIONS invD = which are based on previous DEFINITIONS D = ), and wherein the method further comprises determining whether the ray intersects the axis-aligned box based on results of the comparisons for the plurality of edges of the box (Table 1, //Overlap test; [0032-0033]).
The motivation to combine provided with respect to claim 1 equally applies to claim 15.
Regarding claim 17, in addition to the teachings addressed in the claim 3 analysis, the rejection of claim 3 is incorporated and Mueller teaches the method, fixed-function circuitry of the processing module (see claim 3 mapping):
does not have exception handling functionality ([0025-0027], [0032], [0034], [0053], [0063], [0073-0074] FPUs; [0073, 0076-0078] 714, 716, 718, 720, 722, 724) for performing the particular comparison operation using floating point values of zero (see claim 1 mapping) or infinity.
Although Mueller teaches computing operations on floating-point values (Fig. 9, 904; [0085]), they are silent with disclosing those computation operations including comparison operations.
Laine teaches comparison (Fig. 3, 304; [0034]).
The motivation to combine provided with respect to claim 1 equally applies to claim 17.
Claims 18-19 are directed to a device that would perform the method of claim 1. The claims 1, 17 analysis similarly apply to claims 18-19, and are similarly rejected.
Claim 20 is directed to a computer program product that would perform the method of claim 1. The claim 1 analysis equally applies, and claim 20 is similarly rejected. Additionally, claim 20 recites the following:
having stored thereon an integrated circuit definition dataset that when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a processing module, having fixed-function circuitry.
Mueller teaches having stored thereon an integrated circuit definition dataset that ([0101], [0107]) when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a processing module, having fixed-function circuitry ([0096], [0102]).
Allowable Subject Matter
Claims 5-11, 14, and 16 are rejected, but would be allowable if rewritten in independent form including all of the limitations of the base claim, any intervening claims, and to overcome the current 35 USC 101 rejections.
The statement of reasons of allowable subject matter as indicated in the Non-Final Office Action filed 02/04/2025 is still applicable.
Response to Arguments
35 USC 112(a). The rejections are withdrawn based on the amendment to the claims.
35 USC 112(b). The rejections are withdrawn based on the amendment to the claims.
35 USC 101. The Applicant argues the following in substance:
1) Applicant asserts that, whatever alleged "mathematical concept" is asserted to be claimed, such is clearly integrated into the practical application of computer graphics and in particular the technological field of ray tracing (Remarks p. 14 para. 3). That is, claim 1 requires that an image is rendered by the ray tracing system using the output result, which is a clear practical application of technology (Remarks p. 14 para. 6). The process of rendering an image is not a purely mathematical concept. An image is generated as a result of this rendering step at the ray tracing system, thus realizing a
tangible, real-world end result (Remarks p. 15 para. 2). Amended claims 1, 18 and 20 specify that the comparison operation is part of an intersection testing process performed by a ray tracing system and that the outputted result of the comparison operation is used in the ray tracing system to render an image. In this way, the invention is integrated into a practical application (i.e. the rendering of an image in a ray tracing system), such that the claims are not merely directed a 'mathematical concept' (Remarks p. 15 para. 4).
Examiner respectfully disagrees. In light of the amendments to claim 1 the scope of the 35 USC 101 analysis has been altered, therefore the limitation “the outputted result of the particular comparison operation is used in the ray tracing system to render an image” has been analyzed as an additional element. This additional element merely generally links the abstract idea, the mathematical concepts, to a particular technological environment and/or field of use (see MPEP 2106.05(h)).
Amended claims 1, 18, and 20 are not integrated into a practical application because the above additional element merely generally links to a particular technology/field of use without any relation between the mathematical concepts of ray tracing and intersection testing in a manner that is integral to the claim and as the abstract idea relates to the particularities of how an image is rendered.
2) Applicant asserts that, the Examiner further alleges that a processing module implemented as part of a ray tracing system, as in claim 1, is an example of 'generic computing elements.' Applicant respectfully disagrees. Claim 1 relates specifically to the use of the claimed processing module as part of a ray tracing system. The ray tracing system is not a set of generic computing elements but rather is comprised of computing components which are specifically used to perform ray tracing operations in computer graphics (Remarks p. 15 para. 3).
Examiner respectfully disagrees. The additional elements described above as examples of generic computing elements are not recited in the amended claims 1, 18, and 20 with any further details to limit the scope of what is included in them or not. That is, with the exception of “the processing module is implemented as part of a ray tracing system”, amended claims 1, 18, and 20 do not recite anything further that would lend itself to describe these components as anything more than recited at a high-level of generality.
Further, the additional elements described above are not recited in conjunction with the abstract idea as implementing or using with, a particular machine that is integral to the claim. See MPEP 2106.05(b).
35 USC 103. The Applicant argues the following in substance:
1) Applicant asserts that, Mueller does not disclose a ray tracing system. There is no mention whatsoever of performing a particular operation as part of an intersection testing process. Mueller therefore does not disclose the feature "wherein the processing module is implemented as part of a ray tracing system, wherein the particular comparison operation is part of an intersection testing process performed by the ray tracing system" in amended claim 1 (Remarks p. 18 par. 2).
Examiner respectfully disagrees. Mueller is relied upon to teach the operation, but is not relied upon in the prior art rejection to teach the remaining cited limitation. Instead, Laine is relied upon.
2) Applicant asserts that, The Office action at page 13 asserts that Mueller discloses the feature "(a)" but refers to "other values involved in the particular operation", rather than "other values involved in the particular comparison operation". Applicant respectfully disagrees.
The Office action cites paragraphs 90 - 91 of Mueller ( see steps 910 and 912 in
figure 9) as disclosing the feature "replacing a floating point value of zero with a nonzero substitute floating point value whose magnitude is small enough to behave like
zero in said particular comparison operation". In contrast, this cited passage does not
disclose this feature of claim 1.
Instead, paragraphs 90 - 91 of Mueller describe that, when a floating-point number is zero, a sign of zero can be represented as a "don't care" term, in accordance with the enhanced floating-point number format. That is, in Mueller, when a value of zero is processed, it is still processed as a value of zero, only that the sign bit represents a "don't care" term to indicate that the sign does not matter with respect to the zero value. The value of zero is still processed as zero; it is not replaced with a substitute floating point value.
Thus, Mueller does not disclose replacing a value of zero with a non-zero substitute floating point value at all. For completeness, as acknowledged by the Examiner's comments, Mueller does not disclose any of the other features (b) or (c) in claim 1. (Remarks p. 18 par. 3-6).
Examiner respectfully disagrees. Applicant is arguing Mueller does not teach “replacing a floating point value of zero with a non-zero substitute floating point value whose magnitude is small enough to behave like zero in said particular comparison operation” with respect to paragraph 90-91. However, under the broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. The definition given its plain meaning, provided by Merriam Webster, of replace is defined as 2) “tak[ing] the place of especially as a substitute” (see Anonymous, "replace", date accessed: July 11,2025. Merriam-Webster. https://www.merriam-webster.com/dictionary/replace (hereinafter “Merriam-Webster”, Pg. 1). Mueller teaches in paragraphs 90-91 that the zero is replaced by substituting with a “don’t care” term or symbol that indicates that the sign does not matter. Thus, based on the BRI of the claim, Mueller teaches the claimed limitation as recited. See MPEP 2111.01.
3) Laine does not disclose extending an exponent range of floating point values or any of features (a) to (c) in claim 1 (Remarks p. 19 par. 2).
Examiner respectfully disagrees. Laine is not relied upon to teach any of features (a) to (c). Instead, Mueller is relied on to teach (a).
4) The Office action at pages 29 - 30 asserts that paragraphs 90 - 91 of Mueller teach "that the zero is replaced by substituting with a "don't care" term. Applicant respectfully disagrees. The Office action attempts to construe Mueller by citing the Merriam-Webster definition of 'replace' as "taking the place of especially as a substitute" to arrive at the conclusion that Mueller teaches "that the zero is replaced by substituting with a 'don't care' term or symbol". As explained above, this is not at all what Mueller teaches. As explained above, in Mueller, only the sign of the zero value is replaced, not the value itself.
In further detail, paragraph 51 of Mueller refers to the sign of a zero being defined as being a "don't care" term in the enhanced floating-point format and states that "by employing the enhanced floating-point number format, including its treatment of the sign associated with the value of zero, can thereby enable the hardware utilized by the system 100 in connection with the enhanced floating-point number format to be relatively less complex, and less hardware and hardware resources (and less logic resources) can be utilized, than the hardware used for other floating-point number
formats (e.g., the 1/5/10 format)." (Remarks p. 19 par. 4-5, p. 20 par. 1).
Mueller thus teaches using a zero with a sign bit which indicates the zero's sign
does not matter can make the handling of the sign of zero less complex than in the
original input format, and hardware utilized by the system 100 in connection with the
enhanced floating-point number format can be relatively less complex, and utilize less
hardware and hardware resources. There is no suggestion whatsoever in Mueller of
replacing a zero value with the "don't care" term or symbol, but rather the sign (M- sign
bit) indicates that the sign of the zero does not matter.
Even if it were the case (even though it is not) that Mueller were to be interpreted as teaching replacing the zero value with the zero value plus 'don't care' term or even just a 'don't care' term, the zero value still would not be replaced by "a non-zero substitute floating point value", as is recited in claim 1. In other words, a 'don't care' term is not a 'non-zero substitute floating point value'. Indeed, a 'don't care' term is not a floating point value at all. Thus, the skilled person would still not arrive at the step of "(a) replacing a floating point value of zero with a non-zero substitute floating point value", as recited in claim 1, even if the incorrect interpretation of Mueller as stated in the Office action were taken.
There is no suggestion whatsoever in Mueller of replacing a zero value with a nonzero substitute value. In fact, Mueller demonstrates that it is effective to use the "don't care" sign term for the value of zero, when performing calculations using zero, to reduce the complexity in handling zeros when performing such calculations. Thus, the effect of reducing the complexity of calculations involving the processing of zero values is achieved in Mueller without the need to replace values with non-zero substitutes.
To reiterate, both Mueller and Laine fail to teach or suggest the features (a) to (c) of claim 1, hence the skilled person looking to the combination of these documents would have no motivation to arrive at any of the features (a) to (c). Hence, for at least this reason, claim 1 is novel and inventive over the prior art (Remarks p. 20 par. 2-5).
Examiner respectfully disagrees. Amended claims 1, 18, and 20 do not explicitly specify whether a specific portion, bit, or entirety of a floating-point value of zero is replaced with a non-zero substitute. Mueller discloses how the sign of zero is represented with a “don’t care term” when a floating-point number is zero as accounting for the signs of floating-point values is required for calculations (Fig. 9, 910, 912; [0090-0091]). The “sign of zero” is part of the floating-point value, and by replacing it with a “don’t care” term is effectively altering the floating-point value, and therefore teaches the limitation as claimed, based on the broadest reasonable interpretation and its plain meaning since the particularities of what exactly is being replaced are recited broadly.
In response to applicant’s argument that there is no teaching, suggestion, or
motivation to combine the references, the examiner recognizes that obviousness may
be established by combining or modifying the teachings of the prior art to produce the
claimed invention where there is some teaching, suggestion, or motivation to do so
found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir.
1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International
Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In this case, Mueller and Laine are both analogous art to the claimed invention.
Modifying Mueller with Laine would have been obvious, as Laine is from the same field
of endeavor as the claimed invention, calculating with floating-point values ([0006]). See
MPEP 2141.01(a).
Further, modifying Mueller in view of Laine would expand Mueller’s operations
capability as there exists more than one type of floating-point operation in the
computer architecture arts (See Patterson, Pg. 211, floating-point comparison; Pg. 212,
MIPS floating-point assembly language, Conditional branch; Pg. 221, Elaboration).
Further, with respect to Laine’s ray tracing system, by modifying Mueller’s circuitry to be
used in a ray tracing system would have been obvious as floating-point instructions are
commonly used in computer graphic systems ([0002]). Making this modification
provides benefit by expanding Mueller’s circuitry to an alternative application and
technological environment. Further, making this modification would be beneficial as it
provides Mueller’s device with more types of operations to use on floating-point
numbers for processing, and thus expands its processing capabilities and applications of
use.
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182