Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 02/09/2026, responding to the Office action mailed on 11/19/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-2, 4, 6-16, and 22-27.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 4, 6-16, and 22-27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “The IC device according to claim 1, further comprising an additional interface layer between the interface layer and the channel material”, which contradicts newly amended claim 1. Claim 1, in its current form, recites “one side of the interface laver is in physical contact with the channel material”. Therefore, claim 6 becomes ambiguous and rejected under this section. No prior art rejection has been made because of the indefiniteness.
Claims 7-8 do not rectify the indefiniteness and likewise rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 20170141235 A1; hereinafter “Lai”) in view of Chang et al. (US 20210399104 A1; hereinafter “Chang”).
In re claim 1, Lai discloses in fig. 1, an integrated circuit (IC) device, comprising:
a transistor gate-channel arrangement, comprising a channel material 108 and a transistor gate stack 104 (¶18),
wherein:
the transistor gate stack includes a gate electrode material 114, a hysteretic element 112 (the ferroelectric layer 112 is functionally indistinguishable to a hysteretic element; ¶20) between the gate electrode material 114 and the channel material 108, and an interface layer 110 between the hysteretic element 112 and the channel material 108 (¶21-23),
a thickness of the hysteretic element 112 is at least 35 nanometers (“the ferroelectric layer 112 has a thickness between 0.1 μm and 1 μm”; ¶23),
the interface layer 110 has a dielectric constant of at least 20 (e.g., HfO2; ¶21),
one side of the interface layer 110 is in physical contact with the channel material 108, and
another side of the interface layer 110 is in physical contact with the hysteretic element 112.
Lai discloses the interface layer 110 may include one or more dielectric films with proper thickness designed and configured for better device performance (¶21). However, Lai does not expressly disclose the interface layer a thickness below 3 nanometers.
In the same field of endeavor, Chang discloses in figs. 1-2, an integrated circuit (IC) device 200, comprising: an interface layer 280 having a high-k layer and a thickness below 3 nanometers (the interface layer 280 includes HfSiO and has a thickness of about 0.5 nm to about 1.5 nm; ¶33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Chang and form the high-k based interfacial layer of Lai having a thickness below 3 nanometers in order to attain flatband voltage tuning of high-k field effect transistors and better device performance (¶4 of Chang).
In re claim 2, Lai, as modified by Chang, discloses the IC device according to claim 1 outlined above.
Lai further discloses wherein the thickness of the hysteretic element 112 is between 0.1 μm and 1 μm (¶23), which overlaps the claimed range of between 50 nanometers and 110 nanometers.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lai to form a thickness of the hysteretic element having a thickness between 50 nanometers and 110 nanometers to improve the subthreshold swing without introduces undesired hysteresis (¶17 of Lai).
In re claim 4, Lai, as modified by Chang, discloses the IC device according to claim 1 outlined above.
Lai further discloses in fig. 1, wherein the interface layer 110 includes at least one of: a material comprising silicon and oxygen, a material comprising oxygen and one or more rare-earth elements, a material comprising a metal and oxygen (e.g., HfO2; ¶21), and a two-dimensional material.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai as modified by Chang, as applied to claim 1 above and further in view of Peng et al. (US 20220181495 A1; hereinafter “Peng”).
In re claim 9, Lai, as modified by Chang, discloses the IC device according to claim 1 outlined above.
Lai further discloses in fig. 1, wherein the hysteretic element 112 includes an insulator material (¶23) and the phase of the ferroelectric layer 112 is affected by the deposition process conditions and post-treatment conditions for forming the ferroelectric layer 112 (¶26).
Lai, as modified by Chang, does not expressly disclose wherein at least 5% of the insulator material is in one or more of a tetragonal phase and an orthorhombic phase.
In the same field of endeavor, Peng further discloses an IC device (fig. 6), wherein the hysteretic element 3* includes an insulator material, and wherein at least 5% of the insulator material is in one or more of a tetragonal phase and an orthorhombic phase (¶0049).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Peng into the hysteretic layer of Lai/Chang to adjust strain induced in the channel and provide flexibility of configuration design and optimize device performance (¶25 of Peng).
In re claim 10, Lai, as modified by Chang and Peng, discloses the IC device according to claim 9 outlined above.
Peng further discloses the IC device (fig. 6G) wherein a hysteretic element 3* includes nitrogen in concentration of at least about 1016 atoms per cubic centimeter (¶0050).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Peng and introduce nitrogen dopant into the hysteretic layer of Lai/Chang to stabilize and/or optimize the ferroelectricity of the ferroelectric layer (¶35 of Peng).
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai as modified by Chang, as applied to claim 1 above and further in view of Yoo et al. (US 20190393355 A1; hereinafter “Yoo2”).
In re claim 11, Lai, as modified by Chang, discloses the IC device according to claim 1 outlined above.
Chang further discloses in fig. 1, wherein: the hysteretic element includes a hysteretic arrangement comprising at least a first layer 284n and a second layer 282 and the second layer 282 includes an insulator material (¶12, 49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Chang into Lai and form the hysteretic layer having multiple high-k layers in order to attain flatband voltage tuning of high-k field effect transistors and better device performance (¶4 of Chang).
Lai, as modified by Chang, does not expressly disclose:
the first layer includes a sub-stoichiometric material with vacancies in concentration of at least about 1018 vacancies per cubic centimeter.
In the same field of endeavor, Yoo2 discloses an IC device (figs. 1-6) wherein a hysteretic arrangement comprising at least a first layer 130 and a second layer 120,
the first layer 130 includes a sub-stoichiometric material with vacancies (¶21-27).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Yoo2 into the ferroelectric layer of Lai/Chang and arrive at the claimed invention of two layers for the hysteretic element and concentration of vacancies of at least about 1018 vacancies per cubic centimeter to control the electric field of the ferroelectric layer (¶5-6 of Yoo2).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 12, Lai as modified by Chang and Yoo2, discloses the IC device according to claim 11, wherein the sub-stoichiometric material includes oxygen and wherein the vacancies are oxygen vacancies (¶0021-0027 of Yoo2).
In re claim 13, Lai as modified by Chang and Yoo2, discloses the IC device according to claim 11, wherein the sub-stoichiometric material 130 includes silicon and nitrogen, and wherein the vacancies are nitrogen vacancies (¶0031 of Yoo2).
In re claim 14, Lai as modified by Chang and Yoo2, discloses the IC device according to claim 11 outlined above.
Chang further discloses in fig. 1, wherein: the hysteretic arrangement 279n further includes a third layer 286, and the third layer includes 286 an insulator material, and the first layer 284n is between the second layer 282 and the third layer 286.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai as modified by Chang, as applied to claim 1 above and further in view of Yu et al. (US 20150357480 A1; hereinafter “Yu”).
In re claim 15, Lai, as modified by Chang, discloses the IC device according to claim 1 outlined above, but does not expressly disclose wherein the channel material includes a semiconductor having an average grain size smaller than about 1 millimeter.
In the same field of endeavor, Yu discloses a thick film transistor device (fig. 2) wherein a channel material 26 includes a semiconductor having an average grain size smaller than about 1 millimeter (¶0045).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Yu and modify the grain size of the channel material of Lai/Chang to provide a new and improved metal oxide semiconductor material with improved stability, high carrier mobility, and good control of oxygen vacancies (¶0013 of Yu).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai as modified by Chang, as applied to claim 1 above and further in view of Riemann et al. (US 20120285369 A1; hereinafter “Riemann”).
In re claim 16, Lai, as modified by Chang, discloses the IC device according to claim 1, wherein the channel material includes a semiconductor, e.g., silicon (Chang: the channel layer 108 includes silicon; ¶18-19).
Lai, as modified by Chang, does not expressly disclose wherein the semiconductor material having an average grain size larger than about 1 millimeter.
In the same field of endeavor, Riemann discloses in fig. 1 wherein a semiconductor 2 (e.g., silicon) having an average grain size larger than about 1 millimeter (¶0033).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Riemann into the channel layer of Lai/Chang to utilize single crystals silicon of large dimensions, having the fewest possible impurities as a channel material in electronic devices (¶0003 of Riemann).
Claim(s) 22-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vellianitis et al. (US 20230292524 A1; hereinafter “Vellianitis”) in view of Lai et al. (US 20170141235 A1; hereinafter “Lai”) and Yin et al. (US 20230024174 A1; hereinafter “Yin”).
In re claim 22, Vellianitis discloses in fig. 4E, an integrated circuit (IC) device 400e, comprising:
a transistor gate-channel arrangement 402, comprising a channel material 408 and a transistor gate stack 101 (¶51),
wherein:
the transistor gate stack includes a gate electrode material 204 (¶38), a hysteretic element 106 (¶40; e.g., a zirconium doped hafnium oxide or a silicon doped hafnium oxide) between the gate electrode material 204 and the channel material 408, an interface layer 102 between the hysteretic element 106 and the channel material 408, and an additional interface layer 104 between the interface layer 102 and the channel material 408 (¶39),
the additional interface layer 104 includes a ferroelectric material (¶39),
one side of the additional interface layer 104 is in physical contact with the channel material 408, and
another side of the additional interface layer 104 is in physical contact with the interface layer 102.
Vellianitis discloses a thickness of the hysteretic element 106 is about 5 nanometers or less, between 5 nanometers and 0.5 nanometers, or some other suitable value (¶40), but does not expressly disclose the thickness is at least 15 nanometers.
In the same field of endeavor, Lai discloses in fig. 1, an integrated circuit (IC) device, comprising:
a transistor gate-channel arrangement, comprising a hysteretic element 112 (e.g., HfSiO.sub.x, HfZrO.sub.x..; ¶23) between a gate electrode material 114 and an interface layer 110 (¶21-23),
a thickness of the hysteretic element 112 is at least 15 nanometers (“the ferroelectric layer 112 has a thickness between 0.1 μm and 1 μm”; ¶23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Lai and form the ferroelectric of Vellianitis having a thickness at least 15 nanometers to improve the subthreshold swing without introduces undesired hysteresis (¶17 of Lai).
Vellianitis discloses the interface layer 102 is a ferroelectric layer (¶34), but does not expressly disclose a dielectric constant of the interface layer 102 is at least 20.
In the same field of endeavor, Yin discloses in figs. 1A-1G, an integrated circuit, wherein, a gate dielectric layer 116 comprising a ferroelectric layer having a dielectric constant of at least 20 (¶19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Yin into the interfacial dielectric layer of Vellianitis and form the interfacial dielectric layer having a dielectric constant of at least 20 in order to reduce gate leakage, provide lower power consumption and increased transistor speed and facilitate the scaling down process of the integrated circuit (IC) industry.
In re claim 23, Vellianitis, as modified by Lai and Yin, discloses the IC device according to claim 22 outlined above.
Vellianitis further discloses in fig. 4E, wherein the ferroelectric material 104 includes hafnium, oxygen, and one or more dopants, wherein the one or more dopants include one or more of zirconium, yttrium, silicon, germanium, and aluminum (e.g., silicon doped hafnium oxide ¶39).
In re claim 24, Vellianitis, as modified by Lai and Yin, discloses the IC device according to claim 22 outlined above.
Vellianitis further discloses in fig. 4E, wherein:
one side of the interface layer 102 is in physical contact with the additional interface layer 104, and
another side of the interface layer 102 is in physical contact with the hysteretic element 106.
In re claim 25, Vellianitis, as modified by Lai and Yin, discloses the IC device according to claim 24 outlined above.
Vellianitis further discloses in fig. 4E, wherein:
one side of the hysteretic element 106 is in physical contact with the interface layer b102, and
another side of the hysteretic element 106 is in physical contact with the gate electrode material 204.
Claim(s) 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. (US 20210193811 A1; hereinafter “Moon”).
In re claim 26, Moon discloses in fig. 1, an integrated circuit (IC) device, comprising:
a transistor gate-channel arrangement, comprising a channel material 115 and a transistor gate stack (130, 140, 150) (¶44), wherein:
the transistor gate stack includes a gate electrode material 150, a hysteretic element 140 (the ferroelectric layer 140 is functionally indistinguishable to a hysteretic element; ¶59-60) between the gate electrode material 150 and the channel material 115, and an interface layer 130 between the hysteretic element 140 and the channel material 115, and
the interface layer 130 includes at least one of: graphene, boron disulfide, and a metal chalcogenide (¶51, 53).
Moon further discloses a thickness of the hysteretic element 140 is about 0.5 nm to 20 nm (¶61), which overlaps the claimed range of at least 15 nanometers and a thickness of the interface layer 130 is about 0.5 nm to 3 nm (¶55), which overlaps the claimed range of below 3 nanometers.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Moon to form a thickness of the hysteretic element having a thickness of at least 15 nanometers and a thickness of the interface layer below 3nm in order to achieve improved subthreshold swing and better performance of the logic transistor (¶2-26 of Moon)
In re claim 27, Moon discloses in fig. 1, the IC device according to claim 26, wherein:
one side of the interface layer 130 is in physical contact with the channel material 115, and
another side of the interface layer 130 is in physical contact with the hysteretic element 140.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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