DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/19/2025 has been entered.
Election/Restrictions
Claim 9 is no longer considered allowable (see new art rejections below). Therefore, claims 10-12 are once again withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Objections
Claim 8 is objected to because of the following informalities: “between the power plane” should read --between the conductive features--, since the power plane as claimed in claim 1 is not entirely within the encapsulant, and the connection between the conductive features in the encapsulant and the through-silicon via are part of the power plane. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8, 9 and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yee (US2017/0062383A1) in view of Jee (US2020/0006242A1).
Yee discloses an embodiment as shown in Fig. 2, which is identical to an embodiment as shown in Fig. 1, except in Fig. 2 the memory structure 202 comprises stacked dies 204 each having through vias 206, whereas the embodiment of Fig. 1 the memory structure 108 includes vias formed in an encapsulant material encapsulating dies 110. Manufacturing steps are shown only with respect to the embodiment of Fig. 1 (see Figs. 5-12), but it is understood the same manufacturing steps would be used to manufacture the embodiment of Fig. 2, except using memory structure 202 instead of memory structure 108. The rejection is based on the embodiment of Fig. 2, but reference is, therefore, also made to Figs. 5-12.
Yee discloses the claimed invention as follows (limitations not disclosed by Yee are crossed out, below):
Claim 1. A method comprising:
mounting (see [0017]) a second device die (Fig. 2: top die 204 in memory structure 202) to a first device die (Fig. 2: lowest die 204 in memory structure 202) to form a first package (structure shown in Fig. 10, except with memory structure 202 instead of memory structure 108);
mounting (compare Figs. 10 and 11) the first package to a substrate (118, Fig. 11), wherein the first device die is between the second device die and the substrate;
coupling a power source line (not specifically identified, but necessarily substrate 118 provides power, in order for the device 200 to function) to the first package; and
Claim 2. The method of claim 1, further comprising:
attaching a dummy structure (molding material 106; compare Figs. 7 and 8) to the first device die
Claim 3. The method of claim 2, wherein the dummy structure includes a ringed substrate that surrounds the second device die.
Claim 4. The method of claim 3, wherein the dummy structure comprises a via
Claim 5. The method of claim 1, further comprising:
disposing a heat dissipating feature (122, Fig. 12; see [0050]) over the first package, the heat dissipating feature adjacent the first device die (see Fig. 2).
Claim 8. The method of claim 1, further comprising:
encapsulating the second device die by an encapsulant (106; compare Figs. 7 and 8); and
forming a conductive line (in RDL layer 116) on an upper (the claims do not establish the orientation of the various elements) surface of the encapsulant
Claim 9. A method comprising:
Bonding (see [0017]) one or more second device dies (upper die 204 in Fig. 2) to a first device die (lowest die 204 in Fig. 2), the one or more second device dies arranged in a vertical stack (see Fig. 2);
forming a vertical power plane (112, Fig. 6) adjacent the one or more second device dies;
Claim 13. The method of claim 9, wherein
Claim 14. The method of claim 13, wherein the conductive element of the dummy die includes an array of through vias (112) disposed throughout the substrate.
Claim 15. The method of claim 9,
Yee discloses lower RDL layer 116, vertical vias 112, upper RDL layer 104, and through vias 206 formed through dies 204. Yen does not explicitly show the current paths through the various devices and conductive paths.
Jee discloses (refer to Fig. 5) a device very similar to that of Yee, including a lower RDL layer 140, vertical vias 120, RDL layer 130, and through electrodes 118 formed through die 110. In Fig. 7, Jee discloses an embodiment the same as that of Fig. 5, except with two stacked dies, 270 and 210, having through conductors 218 through die 210. Moreover, Jee discloses the die 270 can also have through conductors (see [0050]). Jee discloses with respect to the embodiment of Fig. 5 a conductive path A connected to a conductive path E. Jee also discloses (see [0041]) conductive path A can be VCC (i.e., positive voltage supply) or VSS (i.e., ground/negative voltage supply). Since path E is connected to path A, the entire combined path is connected to VCC or VSS. With respect to the embodiment of Fig. 7, as mentioned in [0050], die 270 can also include through conductors. The embodiment of Fig. 7 is identical to that of Fig. 5, with the exception of the number of dies. Therefore, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious the same conductive power plane path would also be present in the embodiment of Fig. 7.
In view of the teachings of Jee, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to provide a continuous conductive path, electrically coupling the power source line to a power plane of the first package, wherein the power plane extends in order from the substrate through conductive vias 112 embedded in an encapsulant material 106, from the conductive features through the RDL layer 104, die 102, back through RDL layer 104, through the second device die (upper 204), to the first device die (lowest 204), and from the second device die through the first device die to the substrate (118), the same as the conductive path comprising paths A and E of Jee, as one possible conductive path for providing power to the stacked dies 204 and to die 204, with predictable results.
Regarding claim 4, Yee does not disclose a via wall as claimed. Jee shows in Fig. 3B it is known to dispose vias to form a via wall (i.e., wall of vias 120, Fig. 3B) extending from a top of a dummy structure to a bottom of the dummy structure and along a length of the dummy structure, wherein the power plane extends through the via wall. In view of the teachings of Jee, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form a via wall as claimed, in order to provide multiple vias suitable for conducting data or power signals between RDL layer 116 and RDL layer 104, for connecting to the various dies as needed.
Regarding claim 8, although Yee does not explicitly disclose the dies 204 being silicon dies, and, therefore, does not disclose the through vias 206 being through-silicon vias, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to manufacture the dies from silicon, as a choice among suitable conventional semiconductor materials, with silicon being the most widely-used such material.
Regarding claim 9, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious that if only one end of the conductive path is connected to VCC for example (at lower end of 206 in lowest die 204 of Fig. 2), due to accumulating resistance, the voltage at the end of the conductive path (i.e. at bottom end of 112) would be different. One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to connect contact to the lower end of the via 112, such as through RDL layer 116, so that the current path branches through via 120 as one path, and through the stacked dies 210 and 270 as another path, thereby reducing the current passing through the stacked dies and providing for a more stable voltage.
Claim(s) 9 and 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jee.
Jee discloses the claimed invention as follows (refer to the embodiment of Fig. 7, as well as the manufacturing steps of Figs. 8-17; it is understood the process of obtaining the structure of Fig. 7 differs from the process of Figs. 8-17 by die 110 being thinner, and by attaching die 270 to die 110, to fill the space occupied by die 110 alone, in the process of Figs. 8-17):
Claim 9. A method comprising:
bonding one or more second device dies (270, Fig. 7) to a first device die (210, Fig. 7’ see [0050]), the one or more second device dies arranged in a vertical stack (see Fig. 7);
forming (when disposing dies 270 and 210 in 102, in Fig. 10) a vertical power plane (120, Fig. 7; see Figs. 9 and 10; it is understood the same process applies even when die 110 is replaced with two dies 210 and 270) adjacent the one or more second device dies;
electrically coupling a first contact (e.g. 214 in Fig. 7) of the first device die to the vertical power plane
Claim 13. The method of claim 9, wherein the vertical power plane includes a dummy die (102 with 120, Fig. 7), the dummy die comprising a conductive element (120) embedded within a substrate (102).
Claim 14. The method of claim 13, wherein the conductive element of the dummy die includes an array of through vias (120, Fig. 3B; it is understood the same process applies even when die 110 is replaced with two dies 210 and 270) disposed throughout the substrate.
Claim 15. The method of claim 9, wherein the vertical power plane extends horizontally (e.g., through die 150; see path E in Fig. 4) along a length of an edge of one device die of the one or more second device dies.
Jee discloses with respect to the embodiment of Fig. 5 a conductive path A connected to a conductive path E. Jee also discloses (see [0041]) conductive path A can be VCC (i.e., positive voltage supply) or VSS (i.e., ground/negative voltage supply). Since path E is connected to path A, the entire combined path is connected to VCC or VSS. With respect to the embodiment of Fig. 7, as mentioned in [0050], die 270 can also include through conductors. The embodiment of Fig. 7 is identical to that of Fig. 5, with the exception of the number of dies. Therefore, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious the same conductive power plane path would also be present in the embodiment of Fig. 7. Whereas it is clear that the contact 214 of the first circuit die is electrically connected to VCC or VSS, there is no discussion in Jee of the contact 214 is electrically connected the vertical power plane at one end of the power plane, as claimed.
However, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious that if only one end of the conductive path is connected to VCC for example (at 214), due to accumulating resistance, the voltage at the end of the conductive path (i.e. at bottom end of 120) would be different. One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to connect contact 140 to the lower end of the via 120, such as through RDL layer 140, so that the current path branches through via 120 as one path, and through the stacked dies 210 and 270 as another path, thereby reducing the current passing through the stacked dies and providing for a more stable voltage.
Claim(s) 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US9780071B2) in view of Jee.
Lee discloses the claimed invention as follows (refer to Fig. 5):
Claim 21. A method comprising:
mounting a first device die (first, i.e., lowest 20) to a substrate (10) [and simultaneously] mounting a first dummy device (first, i.e., lowest 30, not numbered) to the substrate adjacent the first device die, the first dummy device having a first power via (34 in first 30);
attaching a second device die (second 20, not numbered) to the first device die; [and] attaching a second dummy device (second 30) to the first dummy device, the second dummy device having a second power via (34 in second 30), the second power via being electrically coupled to the first power via (see Fig. 5);
forming a first encapsulant (84) over the substrate and on sidewalls of the first dummy device and the first device die [and simultaneously] forming a second encapsulant (additional 84) over the first encapsulant and on sidewalls of the second dummy device and the second device die; and
forming a conductive line (one 50 on the upper 20; also refer to Fig. 1) over the second dummy device to electrically connect the second power via of the second dummy device to a power line (one 22 on second 20; also see Fig. 1) of the second device die, wherein a power circuit comprises a continuously conductive loop extending in series from the substrate (one 12 of 10),
Claim 23. The method of claim 21, wherein the substrate comprises a device die (10).
It is not clear from Lee whether the package units 60 including the dies 20 and dummy dies 30 are stacked, followed by attaching the stack to the die 10, or a unit 60 is stacked to die 10, followed by stacking additional units 60 and attaching the units and the die 10 in a single step, or performing an attaching after each step of stacking a unit 60. However, one of ordinary skill in the art before the effective filing date of the claimed invention would have found obvious to sequentially attach the units 60 to die 10, as a choice among a small number of possibilities, with predictable results.
Lee also does not disclose the crossed-out limitations.
Jee discloses (refer to Fig. 5) a device including a lower RDL layer 140, vertical vias 120, RDL layer 130, and through electrodes 118 formed through die 110. In Fig. 7, Jee discloses an embodiment the same as that of Fig. 5, except with two stacked dies, 270 and 210, having through conductors 218 through die 210. Moreover, Jee discloses the die 270 can also have through conductors (see [0050]). Jee discloses with respect to the embodiment of Fig. 5 a conductive path A connected to a conductive path E. Jee also discloses (see [0041]) conductive path A can be VCC (i.e., positive voltage supply) or VSS (i.e., ground/negative voltage supply). Since path E is connected to path A, the entire combined path is connected to VCC or VSS. With respect to the embodiment of Fig. 7, as mentioned in [0050], die 270 can also include through conductors. The embodiment of Fig. 7 is identical to that of Fig. 5, with the exception of the number of dies. Therefore, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious the same conductive power plane path would also be present in the embodiment of Fig. 7.
From Jee, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to provide VCC or VSS (i.e., power) signals to the dies in a stack of dies by providing through conductors passing through each of the vias in the stack, such that a VCC or VSS connection to the lowest die is further connected to the other dies in the stack, by means of the through conductors. Jee also shows that same path being connected back to the substrate, along a conductive path external to the stack.
Taking into consideration the combined teachings of Lee and Jee, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to provide the dies 20 of Lee with conductive paths (i.e., through conductors) passing vertically through the dies, and connected to VCC or VSS at the bottom of the stack, to the substrate 10, and connected to the conductive line 50 associated with each die 20. One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious that providing two separate current paths would result in lower resistive losses and more stable voltage levels.
Regarding claim 22, Jee discloses an invention similar to that of Lee, in which a ringed dummy die 102 including TSVs 120 is provided so as to surround a device die 110 (see Figs. 3A, 3B and 4), for routing signals such as data and power (see [0034] and [0041]).
In view of the teachings of Jee, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to replace the dummy die 30 of modified Lee with a ringed dummy via including TSVs and other features at the same locations as disclosed by Lee. One of ordinary skill in the art would have found it obvious to do so as a simple substitution of one known dummy die design for another, with predictable results.
Claim(s) 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jee and further in view of Watanabe (US2018/0294249A1).
Lee, as modified in view of Jee, renders obvious the claimed invention, as discussed above, including forming an insulating layer (sealing member 84) over the conductive line, but does not disclose attaching a second substrate to the insulating layer, wherein the second substrate comprises a metal or metal alloy substrate and wherein the second substrate is attached to the insulating layer using thermal interface material.
Watanabe shows it is known to attach a heat sink (570, Fig. 5) using a thermal interface material (570, Fig. 5) to the upper surface of an insulating sealing member (160, Fig. 5) encapsulating a stack (105, Fig. 5) of device dies, to help dissipate heat generated from the dies. See [0030].
For the purpose of dissipating heat from the stacked dies 20, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to attach, through a thermal interface material, a heat sink to the upper surface of sealing member 84 of modified Lee.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729