DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed February 4, 2026. Claim 1 has been amended. No claims have been added. No claims have been canceled. Currently, claims 1-2, and 4-9 are pending.
Response to Arguments
Applicant's arguments filed February 4, 2026 have been fully considered but they are not persuasive.
Applicant asserts that the combination of Tsuchida, Lu and Takishita fail to disclose the newly amended limitations of claim 1. Specifically, Takishita does not teach or suggest "the plurality of marking regions being at least three marking regions that are separate from one another and being all outside the scribe lines, and positioned corresponding to one another to provide manufacturing process alignment, at least one of the marking regions being one of the plurality of second chip regions," as required by amended claim 1. Further indicating that “the other cited references are also silent on the above feature”.
The Examiner respectfully disagrees with these assertions. Firstly, Takishita was not relied upon to disclose all the limitations of claim 1 and was only relied upon to disclose a plurality of first chip regions (Fig. 1, semiconductor chip 22, ¶ [0037]), each for forming a semiconductor product chip (Fig. 1, “In the semiconductor chip 22, an active region is formed”, ¶ [0037]), and a plurality of second chip regions (Fig. 1, PCM 23, ¶ [0037]), each for forming a process control monitor (PCM) chip (Fig. 1, “PCM formation regions each for forming a PCM 23”, ¶ [0037]);
at least one of the marking regions being one of the plurality of second chip regions (Fig. 1, “the PCM 23… may be provided with markers”, ¶ [0046]). Secondly, the primary reference Tsuchida does disclose forming a plurality of marks (Fig. 1, markers 41, ¶ [0040]) in the epitaxial layer (Fig. 1, “markers 41 are formed on the wafer surface 31A on the epitaxial film side of the silicon carbide single crystal wafer 31”, ¶ [0040]), each mark being formed in a different one of a plurality of marking regions (41), the plurality of marking regions (41) being positioned corresponding to one another to provide manufacturing process alignment (“the position information corresponding to the pixels of the two-dimensional CCD array 9 therein can also be similarly identified using the marker 41 as a reference”, ¶ [0054]). Therefore, the Examiner would not need to rely upon Takishita to disclose this limitation.
The Applicant further asserts that one of ordinary skill in the art would not combine Tsuchida and Takishita as suggested by the Examiner because Takishita discloses “the markers in the PCM regions are for identifying each PCM region itself”.
The Examiner respectfully disagrees with this assertion. Tsuchida discloses the use of marking regions for alignment as outlined in the previous Office Action. While Takishita does not specifically disclose the use of PCM regions for alignment, it is known in the art that PCM regions can be used for alignment during fabrication. For example, Lu which was applied in the rejection of claim 1 in the previous Office Action discloses “the alignment marks of the alignment region in the same layer formed by the two corresponding masks are compared to perform in-chip overlay measurement for process-control-monitor (PCM)”. Therefore, the Examiner asserts that one of ordinary skill in the art would combine the teachings of Tsuchida and Takishita as suggested in the previous Office Action.
The Applicant asserts that Kojima does not disclose “wherein one of the plurality of marks is at a center of the cross shape” because the alignment mark 24 of Kojima are all formed within scribe lines, not "outside the scribe lines" as required by claim 1.
The Examiner respectfully disagrees with this assertion. Firstly, Kojima was not relied upon to disclose any of the limitations of claim 1 as they were all disclosed by the other applied prior art. Secondly, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Therefore, the previously presented rejections are maintained as appropriate and presented in full below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida et al. (JP 2007318031 A) herein after “Tsuchida” in view of Lu et al. (US 20210057350 A1) herein after “Lu” and Takishita et al. (US 20200135593 A1) herein after “Takishita”.
Regarding claim 1, Figs. 1-2, and 11 of Tsuchida disclose a method of manufacturing a silicon carbide semiconductor device (Figs. 1-9, “a method of manufacturing a silicon carbide semiconductor device from a silicon carbide”, ¶ [0023]), the method comprising:
providing a starting substrate containing silicon carbide (Fig. 1, silicon carbide single crystal substrate 31, ¶ [0040]);
epitaxially growing an epitaxial layer on the starting substrate (31), thereby forming a semiconductor wafer (“a silicon carbide single crystal wafer is prepared by growing an epitaxial film of the same crystal type as the substrate on a silicon carbide single crystal substrate”, ¶ [0039]);
delineating a plurality of chip regions (Fig. 1, “The element formation regions D1, D2, . . . are spaced apart from one another so that the elements can be finally cut and separated from the wafer”, ¶ [0043]) including:
a plurality of first chip regions (D1, D2), each for forming a semiconductor product chip (Fig. 11, semiconductor element 61, ¶ [0098]); and
forming a plurality of marks (Fig. 1, markers 41, ¶ [0040]) in the epitaxial layer (Fig. 1, “markers 41 are formed on the wafer surface 31A on the epitaxial film side of the silicon carbide single crystal wafer 31”, ¶ [0040]), each mark being formed in a different one of a plurality of marking regions (41), the plurality of marking regions (41) being at least three marking regions (41) that are separate from one another (Fig. 1, “a large number of these markers 41 are usually formed within the wafer surface 31A (only four markers are shown”, ¶ [0041]) and being all outside the space between the chip regions, and being positioned corresponding to one another to provide manufacturing process alignment (“the position information corresponding to the pixels of the two-dimensional CCD array 9 therein can also be similarly identified using the marker 41 as a reference”, ¶ [0054]);
inspecting the epitaxial layer for a crystal defect using crystal defect inspection equipment (Fig. 2, “information on the positions 51 of the crystal defects in the wafer surface 31A is acquired”, ¶ [0044]);
forming a device element structure (Fig. 1, element formation regions D1, D2, ..., ¶ [0042]) in at least one of the plurality of chip regions in the semiconductor wafer (“the formation of semiconductor elements is completed in each element formation region”, ¶ [0094]);
dicing the semiconductor wafer into a plurality of individual semiconductor chips, including the plurality of semiconductor product chips (61) after the device element structure is formed (“Then, each formed semiconductor element is cut and separated from the wafer”, ¶ [0094]); and
identifying, as a conforming product candidate, one of the plurality of semiconductor product chips that is free of the crystal defect detected during the inspecting (“each cut and separated semiconductor element is screened according to the selection result”, ¶ [0095]).
Tsuchida fails to disclose forming a plurality of scribe lines at a surface of the semiconductor wafer in the space between the chip regions;
the plurality of chips regions including:
a plurality of first chip regions, each for forming a semiconductor product chip, and a plurality of second chip regions, each for forming a process control monitor (PCM) chip;
at least one of the marking regions being one of the plurality of second chip regions;
dicing the semiconductor wafer along the plurality of scribe lines.
In the similar field of endeavor of wafer manufacturing, Fig. 2 of Lu discloses forming a plurality of scribe lines (Fig. 2, scribe lines 120, ¶ [0028]) at a surface of the semiconductor wafer (Fig. 2, semiconductor substrate 22, ¶ [0024]) in the space between the chip regions (Fig. 2, dies 110, ¶ [0028]); and
dicing the semiconductor wafer (22) into a plurality of individual semiconductor chips (“The cutting operation is performed by using a cutter to cut the semiconductor wafer 100 into individual dies 110 along the scribe lines 120”, ¶ [0028]) along the plurality of scribe lines (120).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Tsuchida with the scribe lines as disclosed by Lu, to reduce stress on the wafer when dicing (see Lu, ¶ [0028]).
Lu fails to disclose the plurality of chips regions including:
a plurality of first chip regions, each for forming a semiconductor product chip, and a plurality of second chip regions, each for forming a process control monitor (PCM) chip;
at least one of the marking regions being one of the plurality of second chip regions.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 1 of Takishita discloses the plurality of chips regions including:
a plurality of first chip regions (Fig. 1, semiconductor chip 22, ¶ [0037]), each for forming a semiconductor product chip (Fig. 1, “In the semiconductor chip 22, an active region is formed”, ¶ [0037]), and a plurality of second chip regions (Fig. 1, PCM 23, ¶ [0037]), each for forming a process control monitor (PCM) chip (Fig. 1, “PCM formation regions each for forming a PCM 23”, ¶ [0037]);
at least one of the marking regions being one of the plurality of second chip regions (Fig. 1, “the PCM 23… may be provided with markers”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Tsuchida with the chip regions as disclosed by Takishita, to enhance reliability and reduce defects (see Takishita, ¶ [0068]).
Regarding claim 2, Tsuchida, Lu, and Takishita together disclose the method according to claim 1 as applied above, but Tsuchida and Lu fail to disclose wherein each of the plurality of marking regions is one of the plurality of second chip regions.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 1 of Takishita discloses herein each of the plurality of marking regions is one of the plurality of second chip regions (Fig. 1, “the PCM 23… may be provided with markers”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Tsuchida with the chip regions as disclosed by Takishita, to enhance reliability and reduce defects (see Takishita, ¶ [0068]).
Regarding claim 4, Tsuchida, Lu, and Takishita together disclose the method according to claim 1 as applied above, and Fig. 1 of Tsuchida further discloses wherein at least one of the plurality of marking regions (41) is a dead region between an end of the semiconductor wafer and ones of the plurality of chip regions facing the end of the semiconductor wafer (Fig. 1, “markers 41 are formed on the wafer surface 31A on the epitaxial film side of the silicon carbide single crystal wafer 31”, ¶ [0040]), the device element structure not being formed in the dead region (Fig. 1 shows that the marks are formed in the region between element formation regions D1, D2, ... and the edge of the wafer 31).
Regarding claim 5, Tsuchida, Lu, and Takishita together disclose the method according to claim 1 as applied above, and Fig. 1 of Tsuchida further discloses wherein the plurality of marking regions (41) includes:
a second marking region that is a dead region between an end of the semiconductor wafer and ones of the plurality of chip regions facing the end of the semiconductor wafer (Fig. 1, “markers 41 are formed on the wafer surface 31A on the epitaxial film side of the silicon carbide single crystal wafer 31”, ¶ [0040]), the device element structure not being formed in the dead region (Fig. 1 shows that the marks are formed in the region between element formation regions D1, D2, ... and the edge of the wafer 31).
Tsuchida and Lu fail to disclose a first marking region that is one of the plurality of second chip regions.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 1 of Takishita discloses a first marking region that is one of the plurality of second chip regions (Fig. 1, “the PCM 23… may be provided with markers”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Tsuchida by including the first marking region as disclosed by Takishita, to enhance reliability and reduce defects (see Takishita, ¶ [0068]).
Regarding claim 6, Tsuchida, Lu, and Takishita together disclose the method according to claim 5 as applied above, and Fig. 1 of Tsuchida further discloses wherein the plurality of marking regions (41) are disposed in a cross shape (shown in Fig. 1).
Regarding claim 7, Tsuchida, Lu, and Takishita together disclose the method according to claim 2 as applied above, and Fig. 1 of Tsuchida further discloses wherein the plurality of marking regions (41) are disposed in a cross shape or a tetragon shape (shown in Fig. 1).
Regarding claim 8, Tsuchida, Lu, and Takishita together disclose the method according to claim 1 as applied above, and Fig. 1 of Tsuchida further discloses wherein forming the plurality of marks includes forming a plurality of protrusions or recesses by etching the surface of the semiconductor wafer (Fig. 1, “The markers 41 can be formed by making the surface of the wafer surface 31A uneven using a method such as reactive ion etching”, ¶ [0041]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida (JP 2007318031 A), Lu (US 20210057350 A1) and Takishita (US 20200135593 A1) in further view of Kojima (US 6132910 A).
Regarding claim 9, Tsuchida, Lu, and Takishita together disclose the method according to claim 6 as applied above, but the combination fails to disclose wherein one of the plurality of marks is at a center of the cross shape.
In the similar field of endeavor of semiconductor wafer manufacturing, Fig. 7 of Kojima discloses wherein one of the plurality of marks (Fig. 7, alignment mark 24, col. 4, line 65) is at a center of the cross shape (Fig. 7, “A cross-shaped alignment mark 24 is provided at the wafer's center point O”, col. 4, lines 65-66).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Tsuchida by including the marking regions as disclosed by Kojima, to improve production accuracy (see Kojima, col. 4, lines 17-19).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893