DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other References: Lee (US 209022021) – memory module with buffered memory package.
Lee (US 20190362758) – memory module memory packages – relates to claimed memory package.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,4,6,7,8,9,11,13,14,15,16,18 are rejected under 35 U.S.C. 103 as being unpatentable over Cox (US 20180254079) and in view of Harari (US 20100023800) in further view of Yang (US 20190265888)
Claim 1. Cox discloses An apparatus (eg., 0068 Fig. 4F - system 414)
a memory package with a plurality of memory dies, wherein the plurality of memory dies include an input port and two distinct groups of memory dies coupled on two distinct internal input/output (10) paths of the memory package, and each group of memory dies includes two or more memory dies that are coupled in parallel onto a respective internal 10 path (eg., Fig. 2B [0049] Chip 264 can be structured similarly or the same as chip 262, with DQB0 and DQB1 connectors, and CA connectors. Chip 264 is illustrated as having subarrays 282 mapped with data paths through logic 284 to the DQ I/O for the chip. In one example, logic 284 selectively maps the DQ I/O to subarrays 282.; 0035 - DQ paths 126 can be global I/O paths, and a path can be shared among multiple I/O interfaces of memory dies 122.; 0051 global I/O lines refer to data paths internal to the multi-die memory package, and which connect the memory dies to the package connectors.)
an interface module communicatively coupled to the plurality of one or more memory dies through the two distinct internal 10 paths, the interface module including two distinct circuitries, wherein each circuitry is coupled to a respective one of the two distinct groups of memory dies and configured to (eg., 0070 Fig. 4F - logic 476 maps connectors of chips 472 and 474 to the CA bus of package 470. logic 476 selects among different internal command signal paths to couple to the CA bus I/O that provides commands to package 470. In one example, chips 472 and 474 operate in byte mode. Logic 476 can provide the selection of command connectors for the chips to provide CAS selection and the mapping of subarrays to the external data I/O connectors of package 470).
Cox does not disclose, but Harari discloses
perform 10 external to the memory package at a first 10 width and a first 10 speed, and perform 10 internal to the memory package at a respective second 10 width and a respective second 10 speed; wherein at least one or more of respective second 10 widths is different from the first 10 widths and at least one of respective second 10 speeds is different from the first 10 speed. (eg.,. 0121 - the two buses can run at different frequencies and different widths (e.g., one side could use an 8-bit bus, and the other side can use a 16-bit bus).; 0122 - controller 300 of this embodiment can use buffering and can run these interfaces at different speeds. This allows the controller 300 to also match two different speed buses, for example, a flash side interface bus running at 140 MB/sec and an ONFI bus that runs at either 132 or 166 MB/sec.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, providing the benefit of devices and methods that provide compatibility between a host device having an onboard NAND controller and successive generations of NAND flash memory devices (see Harari, 0039).
Cox in view of Harari does not disclose, but Yang discloses
wherein the two distinct circuitries of the interface module are located on two distinct interface chips, and each circuitry interface chip has a separate substrate from the plurality of memory dies and is coupled between the input port of the memory package and the two or more memory dies of a respective one of the two distinct groups of memory dies within the memory package; wherein each of the two distinct circuitries is (eg., [0044] FIG. 1B illustrates a storage module 200 that includes plural non-volatile storage systems 100. - The interface between storage controller 202 and non-volatile storage systems 100 may be a bus interface,; [0046] FIG. 2A is a block diagram illustrating components of controller 102 in more detail. Controller 102 includes a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the one or more non-volatile memory die 104,)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, with Yang, providing the benefit of For a fast read, the controller can instruct the memory to operate differently (see Yang, 0055) these embodiments provide faster system read with higher data integrity from a system perspective, resulting in a more-reliable system with overall higher-performance fast reads as compared to other storage systems (0063).
Claim 2 Cox does not disclose, but Harari discloses
wherein each circuitry is further to:convert between external 10 at the first 10 width and the first 10 speed to internal 10 at the respective second 10 width and the respective second 10 speed. (e.g., 0121 interconnection between the host and the raw flash memory device(s) into a separate host side interface and a flash side interface with a buffer in between, the host bus has fewer loads and can run two to four times faster. Further, since the memory bus is internal to the MCP, it can have lower power, higher speed, and lower voltage because of the short distance and finite loads involved. Further, the two buses can run at different frequencies and different widths (e.g., one side could use an 8-bit bus, and the other side can use a 16-bit bus)..)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, providing the benefit of devices and methods that provide compatibility between a host device having an onboard NAND controller and successive generations of NAND flash memory devices (see Harari, 0039).
Claim 4. Cox discloses
wherein for one of the two distinct circuitries, the respective second 10 width is an integer factor of N times the first 10 width and the respective second 10 speed is the first 10 speed divided by N, (e.g., logic 532, 534, 522, and/or other logic) can select which I/O to use for a particular memory access transaction..; 0036 - speeds on CA bus 112 are faster than the required latency to read (e.g., fetch and latch) data, or write (e.g., store) data to the memory arrays; in combination with Best’s disclosure of 0040 - relatively slow and wide data path (i.e., relative to the high-speed interface 107) providing the benefit of using different portions of the memory device to enable ECC in a memory device with a typically fixed channel width and I/O interface size (see Cox, 0026) the ability within multichip memory 120 to select among multiple different CAS signals to cause memory dies 122 to access different portions of their memory arrays (0037).
Claim 6. Cox in view of Harari does not disclose, but Yang discloses
wherein the memory package further comprises: a package substrate with the one or more plurality of memory dies and the interface module co-located on the package substrate. (eg., 0038 - storage system 100 includes a controller 102 and non-volatile memory that may be made up of one or more non-volatile memory die 104).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, with Yang, providing the benefit of For a fast read, the controller can instruct the memory to operate differently (see Yang, 0055) these embodiments provide faster system read with higher data integrity from a system perspective, resulting in a more-reliable system with overall higher-performance fast reads as compared to other storage systems (0063).
Claim 7. Cox discloses
wherein the one or more memory die comprises NAND memory die (eg., 0097 - nonvolatile memory device is a block addressable memory device, such as NAND ).
Claim 8. Cox discloses A memory system (eg., 0068 Fig. 4F - system 414)
a memory package with a plurality of memory dies, wherein the plurality of memory dies include an input port and two distinct groups of memory dies includes two or more memory dies that coupled on two distinct internal input/output (10) paths of the memory package, and memory dies of each group of memory dies are coupled in parallel onto a respective internal 10 path (eg., Fig. 2B [0049] Chip 264 can be structured similarly or the same as chip 262, with DQB0 and DQB1 connectors, and CA connectors. Chip 264 is illustrated as having subarrays 282 mapped with data paths through logic 284 to the DQ I/O for the chip. In one example, logic 284 selectively maps the DQ I/O to subarrays 282. ; 0035 - DQ paths 126 can be global I/O paths, and a path can be shared among multiple I/O interfaces of memory dies 122.; 0051 global I/O lines refer to data paths internal to the multi-die memory package, and which connect the memory dies to the package connectors)
an interface module communicatively coupled to the plurality of one or more memory dies through the two distinct internal 10 paths, the interface module including two distinct circuitries, wherein each circuitry is coupled to a respective one of the two distinct groups of memory dies and configured to (eg., 0070 Fig. 4F - logic 476 maps connectors of chips 472 and 474 to the CA bus of package 470. logic 476 selects among different internal command signal paths to couple to the CA bus I/O that provides commands to package 470. In one example, chips 472 and 474 operate in byte mode. Logic 476 can provide the selection of command connectors for the chips to provide CAS selection and the mapping of subarrays to the external data I/O connectors of package 470).
Cox does not disclose, but Harari discloses
perform 10 external to the memory package at a first 10 width and a first 10 speed, and perform 10 internal to the memory package at a respective second 10 width and a respective second 10 speed;wherein at least one or more of respective second 10 widths is different from the first 10 widths and at least one of respective second 10 speeds is different from the first 10 speed. (eg.,. 0121 - the two buses can run at different frequencies and different widths (e.g., one side could use an 8-bit bus, and the other side can use a 16-bit bus).; 0122 - controller 300 of this embodiment can use buffering and can run these interfaces at different speeds. This allows the controller 300 to also match two different speed buses, for example, a flash side interface bus running at 140 MB/sec and an ONFI bus that runs at either 132 or 166 MB/sec.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, providing the benefit of devices and methods that provide compatibility between a host device having an onboard NAND controller and successive generations of NAND flash memory devices (see Harari, 0039).
Cox in view of Harari does not disclose, but Yang discloses
wherein the two distinct circuitries of the interface module are located on two distinct interface chips, and each circuitry interface chip has a separate substrate from the plurality of memory dies and is coupled between the input port of the memory package and the two or more memory dies of [[to]] a respective one of the two distinct groups of memory dies within the memory package; wherein each of the two distinct circuitries is (eg., [0044] FIG. 1B illustrates a storage module 200 that includes plural non-volatile storage systems 100. - The interface between storage controller 202 and non-volatile storage systems 100 may be a bus interface,; [0046] FIG. 2A is a block diagram illustrating components of controller 102 in more detail. Controller 102 includes a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the one or more non-volatile memory die 104,)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, with Yang, providing the benefit of For a fast read, the controller can instruct the memory to operate differently (see Yang, 0055) these embodiments provide faster system read with higher data integrity from a system perspective, resulting in a more-reliable system with overall higher-performance fast reads as compared to other storage systems (0063).
Claim 9 is rejected for reasons similar to Claim 2 above.
Claim 11 is rejected for reasons similar to Claim 4 above.
Claim 13 is rejected for reasons similar to Claim 6 above.
Claim 14 is rejected for reasons similar to Claim 7 above.
Claim 15. Cox discloses An apparatus (eg., 0068 Fig. 4F - system 414)
a memory package with a plurality of memory dies, wherein the plurality of memory dies include an input port and two distinct groups of memory dies coupled on two distinct internal input/output (10) paths of the memory package, and memory dies of each group of memory dies includes two or more memory dies that are coupled in parallel onto a respective internal 10 path (eg., Fig. 2B [0049] Chip 264 can be structured similarly or the same as chip 262, with DQB0 and DQB1 connectors, and CA connectors. Chip 264 is illustrated as having subarrays 282 mapped with data paths through logic 284 to the DQ I/O for the chip. In one example, logic 284 selectively maps the DQ I/O to subarrays 282. ; 0035 - DQ paths 126 can be global I/O paths, and a path can be shared among multiple I/O interfaces of memory dies 122.; 0051 global I/O lines refer to data paths internal to the multi-die memory package, and which connect the memory dies to the package connectors)
an interface module communicatively coupled to the plurality of one or more memory dies through the two distinct internal 10 paths, the interface module including two distinct circuitries, wherein each circuitry is coupled to a respective one of the two distinct groups of memory dies and configured to (eg., 0070 Fig. 4F - logic 476 maps connectors of chips 472 and 474 to the CA bus of package 470. logic 476 selects among different internal command signal paths to couple to the CA bus I/O that provides commands to package 470. In one example, chips 472 and 474 operate in byte mode. Logic 476 can provide the selection of command connectors for the chips to provide CAS selection and the mapping of subarrays to the external data I/O connectors of package 470).
Cox does not disclose, but Harari discloses
perform 10 external to the memory package at a first 10 width and a first 10 speed, and perform 10 internal to the memory package at a respective second 10 width and a respective second 10 speed;wherein at least one or more of respective second 10 widths is different from the first 10 widths and at least one of respective second 10 speeds is different from the first 10 speed. (eg.,. 0121 - the two buses can run at different frequencies and different widths (e.g., one side could use an 8-bit bus, and the other side can use a 16-bit bus).; 0122 - controller 300 of this embodiment can use buffering and can run these interfaces at different speeds. This allows the controller 300 to also match two different speed buses, for example, a flash side interface bus running at 140 MB/sec and an ONFI bus that runs at either 132 or 166 MB/sec.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, providing the benefit of devices and methods that provide compatibility between a host device having an onboard NAND controller and successive generations of NAND flash memory devices (see Harari, 0039).
Cox in view of Harari does not disclose, but Yang discloses
wherein an interface module is communicatively coupled to the plurality of memory dies through the two distinct internal IO paths, the interface module including two distinct circuitries, and wherein the two distinct circuitries of the interface module are located on two distinct interface chips, and each circuitry interface chip has a separate substrate from the plurality of memory dies and is coupled between the input port of the memory package and the two or more memory dies of a respective one of the two distinct groups of memory dies within the memory package (eg., [0044] FIG. 1B illustrates a storage module 200 that includes plural non-volatile storage systems 100. - The interface between storage controller 202 and non-volatile storage systems 100 may be a bus interface,; [0046] FIG. 2A is a block diagram illustrating components of controller 102 in more detail. Controller 102 includes a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the one or more non-volatile memory die 104,)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, with Yang, providing the benefit of For a fast read, the controller can instruct the memory to operate differently (see Yang, 0055) these embodiments provide faster system read with higher data integrity from a system perspective, resulting in a more-reliable system with overall higher-performance fast reads as compared to other storage systems (0063).
Claim 16 is rejected for reasons similar to Claim 2 above.
Claim 18 is rejected for reasons similar to Claim 4 above.
Claims 3, 10, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cox (US 20180254079) and in view of Harari (cited above), Yang (cited above) and further in view of Ma (US 20200293467 A1)
Claim 3. Cox and Harari and Yang does not disclose, but Ma discloses
wherein the circuitry comprises multiplexer and demultiplexer circuitry to convert between external 10 at the first 10 width and the first 10 speed to internal 10 at the second 10 width and the second 10 speed (eg., 0036 Fig. 3 - a multiplexer/demultiplexer (MUX/DeMUX) .. multiplexing unit 1084 to perform data exchange between the memory blocks and the host controller 110,; 0037 - multiplexing unit 1084 to perform data exchange between the memory blocks and the computing unit 1086,; 0053 - computing unit 7062 is coupled to the multiplexing unit of each data buffer 708 through the high-speed interface XDQ ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox and Harari, and Yang with Ma, providing the benefit of integrated in the data buffers and the registering clock driver is responsible for scheduling control (see Ma, 0053) provide a memory controller to meet the bandwidth requirement of a memory module for high data throughput applications (0004).
Claim 10 is rejected for reasons similar to Claim 3 above.
Claim 17 is rejected for reasons similar to Claim 3 above.
Claims 5, 12, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cox (US 20180254079) and in view of Harari (cited above), Yang (cited above) and further in view of Ooi (US 20190227963)
Claim 5. Cox discloses
second 10 width is two times the first 10 width (eg., 0077 Fig. 5 - I/O 552 and I/O 554 can connect to the same N/2 signal lines, and logic (e.g., logic 532, 534, 522, and/or other logic) can select which I/O to use for a particular memory access transaction..)
Cox and Harari and Yang does not disclose, but Ooi discloses
wherein the circuitry comprises 2:1 multiplexer and 1:2 demultiplexer circuitry to convert between external 10 and internal 10 where the and the second 10 speed is one half of the first 10 speed (eg., 0083 Fig. 15 - the multiplexer 1506 may be a 2:1 multiplexer; 0089 - the 1:2 demultiplexer 1518 may demultiplex the serialized 2 bits of data and synchronize the data to the receiver router clock domain 1212 so that the data may be appropriately transferred; 0081 - modularized integrated circuit device 1500 may process and transfer data between portions of a die ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox and and Yang Harari, with Ooi, providing the benefit of the 1:2 demultiplexer 1518 may demultiplex the serialized 2 bits of data and synchronize the data to the receiver router clock domain 1212 so that the data may be appropriately transferred (see Ooi, 0001).
Claim 12 is rejected for reasons similar to Claim 5 above.
Claim 19 is rejected for reasons similar to Claim 5 above.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cox (US 20180254079) and in view of Harari (cited above), Yang (cited above) and further in view of NA (US 20210072902), Ooi (US 20190227963) and Rosenband (US 8397013)
Claim 20. Cox in view of Harari and Yang does not disclose, but NA discloses
wherein each circuitry of the interface module includes - configured to implement signal conversion between (i) an external signal having the first and (ii) a plurality of internal signals that are provided by a respective group of memory dies and (e.g., [0055] The interface circuit 320 may include the demultiplexer circuit 322, a plurality of registers 324, the multiplexer circuit 326; 0030 - memory device 300 may perform operations (e.g., a write operation, a read operation, and an erase operation) with respect to the data DATA in response to signals from the memory controller 200. In an example embodiment, the memory device 300 may generate a data strobe signal based on a read enable signal from the memory controller 200, and provide the memory controller 200 with the data strobe signal generated based on a read enable signal.; 0033 - data operation control signal may include at least one selected from various control signals including, for example, a voltage control signal, a row decoder control signal, a column decoder control signal, and a data input/output control signal.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, and Yang with NA, providing the benefit of reducing data communication time and increasing the operating speed of the memory device and the storage device (see Na, 0005).
Cox and Harari and Yang and NA does not disclose, but Ooi discloses
packaging the plurality of memory dies and the interface module co-located on the same package substrate of memory package (eg., Fig. 7 [0043] Data communication between the dies 302, 304 of the modularized integrated circuit device 102 may occur via embedded interface bridges, such as signal-conducting channels, disposed in a passive silicon interposer 306 (e.g., a 2.5D silicon interposer); 0050 FIG. 7 and FIG. 8 depict a high-level organization of the NOC interface 802 used to facilitate inter-die and intra-die communication in modularized integrated circuit devices 700, 800)
an N:1 mux and 1:N demux circuit ; IO width and the first IO speed; having the respective second IO width and the respective second IO speed, where N is an integer greater than 1. (eg., 0083 Fig. 15 - the multiplexer 1506 may be a 2:1 multiplexer; 0089 - the 1:2 demultiplexer 1518 may demultiplex the serialized 2 bits of data and synchronize the data to the receiver router clock domain 1212 so that the data may be appropriately transferred; 0081 - modularized integrated circuit device 1500 may process and transfer data between portions of a die ; 0051 - NOC interface 802 may provide high-bandwidth, low-latency communication to much of the modularized integrated circuit device 700, 800; 0052 - FNOC interface 810 may bridge the peripheral IP die 304 to the glue die 302 using the high-speed (e.g., 1-1.5 GHz or higher), high-bandwidth (e.g., high bandwidth of 0.25-0.5 terabytes or higher per second per direction per link) NOC interface 802. Advanced Interference Bus-Edge (AIB-E) (e.g., edge interface) may further facilitate using the NOC interface 802. For example, the AIB-E may bridge together the NOC interfaces of the glue dies 302, the NOC interface within a glue die (e.g., 302A), and/or the NOC interface of the glue die 302 to the FNOC interface 810 of the periphery IP die 304.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox and Harari, and Yang and NA with Ooi, providing the benefit of the 1:2 demultiplexer 1518 may demultiplex the serialized 2 bits of data and synchronize the data to the receiver router clock domain 1212 so that the data may be appropriately transferred (see Ooi, 0001) perform data processing, data synchronizing, and data transfer to a destination within the modularized integrated circuit device (0053).
Cox and Harari, Yang, NA and Ooi does not disclose, but Rosenband discloses
wherein the N:1 mux and 1:N demux circuit is coupled between the input port of the memory package and the respective group of two or more memory dies (eg., col 6:50-56 - by MUX/Interleave logic 214 that provides a MUX/DEMUX and/or memory interleave from a single memory interface to one or more Sub-Stacks 204, 202.sub.1-202.sub.n,. The MUX/Interleave logic 214 is necessary to match the speed of the slow memory 104 (flash) to the fast memory 106 (DRAM).)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox and Harari, Yang and NA with Ooi, with Rosenband providing the benefit of converts from one protocol (such as DDR3, corresponding to a fast memory protocol) to another (such as ONFI, corresponding to a slow memory protocol) and necessary to match the speed of the slow memory 104 (flash) to the fast memory 106 (DRAM).)(see Rosenband, col 6:45-56)
Response to Arguments
Applicant's arguments filed 6/3/2026 have been fully considered but they are not persuasive.
For claims 1, 8 and 15, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Cox in view of Harari does not disclose, but Yang discloses
wherein the two distinct circuitries of the interface module are located on two distinct interface chips, and each circuitry interface chip has a separate substrate from the plurality of memory dies and is coupled between the input port of the memory package and the two or more memory dies of a respective one of the two distinct groups of memory dies within the memory package; wherein each of the two distinct circuitries is (eg., [0044] FIG. 1B illustrates a storage module 200 that includes plural non-volatile storage systems 100. - The interface between storage controller 202 and non-volatile storage systems 100 may be a bus interface,; [0046] FIG. 2A is a block diagram illustrating components of controller 102 in more detail. Controller 102 includes a front end module 108 that interfaces with a host, a back end module 110 that interfaces with the one or more non-volatile memory die 104,)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, with Yang, providing the benefit of For a fast read, the controller can instruct the memory to operate differently (see Yang, 0055) these embodiments provide faster system read with higher data integrity from a system perspective, resulting in a more-reliable system with overall higher-performance fast reads as compared to other storage systems (0063).
Regarding arguments for Claim 20, Cox in view of Harari does not disclose, but NA discloses
wherein each circuitry of the interface module includes - configured to implement signal conversion between (i) an external signal having the first and (ii) a plurality of internal signals that are provided by a respective group of memory dies and (e.g., [0055] The interface circuit 320 may include the demultiplexer circuit 322, a plurality of registers 324, the multiplexer circuit 326; 0030 - memory device 300 may perform operations (e.g., a write operation, a read operation, and an erase operation) with respect to the data DATA in response to signals from the memory controller 200. In an example embodiment, the memory device 300 may generate a data strobe signal based on a read enable signal from the memory controller 200, and provide the memory controller 200 with the data strobe signal generated based on a read enable signal.; 0033 - data operation control signal may include at least one selected from various control signals including, for example, a voltage control signal, a row decoder control signal, a column decoder control signal, and a data input/output control signal.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox with Harari, with NA, providing the benefit of reducing data communication time and increasing the operating speed of the memory device and the storage device (see Na, 0005).
Cox and Harari and NA does not disclose, but Ooi discloses
packaging the plurality of memory dies and the interface module co-located on the same package substrate of memory package (eg., Fig. 7 [0043] Data communication between the dies 302, 304 of the modularized integrated circuit device 102 may occur via embedded interface bridges, such as signal-conducting channels, disposed in a passive silicon interposer 306 (e.g., a 2.5D silicon interposer); 0050 FIG. 7 and FIG. 8 depict a high-level organization of the NOC interface 802 used to facilitate inter-die and intra-die communication in modularized integrated circuit devices 700, 800)
an N:1 mux and 1:N demux circuit ; IO width and the first IO speed; having the respective second IO width and the respective second IO speed, where N is an integer greater than 1. (eg., 0083 Fig. 15 - the multiplexer 1506 may be a 2:1 multiplexer; 0089 - the 1:2 demultiplexer 1518 may demultiplex the serialized 2 bits of data and synchronize the data to the receiver router clock domain 1212 so that the data may be appropriately transferred; 0081 - modularized integrated circuit device 1500 may process and transfer data between portions of a die ; 0051 - NOC interface 802 may provide high-bandwidth, low-latency communication to much of the modularized integrated circuit device 700, 800; 0052 - FNOC interface 810 may bridge the peripheral IP die 304 to the glue die 302 using the high-speed (e.g., 1-1.5 GHz or higher), high-bandwidth (e.g., high bandwidth of 0.25-0.5 terabytes or higher per second per direction per link) NOC interface 802. Advanced Interference Bus-Edge (AIB-E) (e.g., edge interface) may further facilitate using the NOC interface 802. For example, the AIB-E may bridge together the NOC interfaces of the glue dies 302, the NOC interface within a glue die (e.g., 302A), and/or the NOC interface of the glue die 302 to the FNOC interface 810 of the periphery IP die 304.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with dies on multichips on a memory package as disclosed by Cox and Harari, and NA with Ooi, providing the benefit of the 1:2 demultiplexer 1518 may demultiplex the serialized 2 bits of data and synchronize the data to the receiver router clock domain 1212 so that the data may be appropriately transferred (see Ooi, 0001) perform data processing, data synchronizing, and data transfer to a destination within the modularized integrated circuit device (0053).
Applicant’s arguments for dependent claims are based on their respective base independent claims 1, 8, 15, which are addressed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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