DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 14-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jung et al. (“Jung” US 2023/0060513).
Regarding claim 14, Jung discloses:
An electronic device (Figure 2) comprising:
a semiconductor die (310) coupled to a package substrate (100) through a plurality of vias (220, see Figure 2), the package substrate (100) comprised of a plurality of layers of a first material (see para. [0020], discloses a multilayered substrate comprising an epoxy resin or polyimide); and
at least one interface layer (340) comprised of an interface material (insulating filler material, see para. [0024], the interface layer 340 may be an epoxy resin with a filler included such as silica) different from the plurality of layers of the first material (the interface layer includes a filler in the epoxy resin, rather than the epoxy resin alone which is the first material of the substrate) and sealed from exposure to air (interface layer 340 is sealed from the external environment/air outside of the package by the insulating structure 350), the interface material comprising a moisture-sensitive (an epoxy material is not impervious, and Applicant’s specification discloses an epoxy as the interface layer, see para. [0010] of the instant specification, thus the epoxy interface layer of Jung is also moisture-sensitive) nonconductive material (340 is not electrically conductive as epoxy resin with silica filler is not an electrically conductive material), the at least one interface layer (340) disposed at least at one of a layer within the package substrate or in contact with a first surface of the semiconductor die (310, lower surface is the first surface of the die 310, with which the interface layer 340 is in contact, see Figure 2) and between the first surface of the semiconductor die (310, lower surface in Figure 2) and the package substrate (100, interface layer 340 is between the lower surface of the semiconductor die 310 and the package substrate 100, see Figure 2).
Regarding claim 15, Jung discloses:
The electronic device of claim 14, wherein the semiconductor die (310) comprises a microprocessor (para. [0050] discloses several microprocessors for semiconductor die 310).
Regarding claim 16, Jung discloses:
The electronic device of claim 14, wherein the semiconductor die (310) comprises a system- on-chip (SOC) (para. [0050] discloses that semiconductor die 310 includes at least one processor and an SOC is known in the art as a single chip, Jung’s semiconductor die 310, that includes several components or processors).
Regarding claim 17, Jung discloses:
The electronic device of claim 14, wherein the at least one interface layer (340) includes a first end (left end) and a second end (right end), and wherein a buffer material (350) is disposed at the first end and the second end (see Figure 2), the buffer material (350) being configured to seal the at least one interface layer (340) from an environment surrounding the semiconductor die (310, see Figures 1A and 2, which shows that the buffer material 350 encloses and seals off the interface layer 340).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 8, and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (“Jung” US 2023/0060513), Wang et al. (“Wang” US 2022/0122896), and Pogge et al. (“Pogge” US Patent No. 6,864,165).
Regarding claim 1, Jung discloses:
A semiconductor package (Figure 1B), comprising:
a package substrate (100) comprised of a plurality of layers of a first material (see para. [0020], discloses a multilayered substrate comprising an epoxy resin or polyimide);
an integrated circuit (IC) (320) attached to the package substrate (100) at a first surface of the IC (lower surface of IC 320 is attached to the package substrate 100 through intervening layers) through a plurality of vias (22, see Figure 1B); and
at least one interface layer (285) comprised of an interface material (epoxy resin with silica filler, see para. [0024]) different from materials of the plurality of layers of the first material (the first material may be an epoxy resin or polyimide which is different from an epoxy resin with filler) [and sealed from exposure to air], the interface material (285) comprising a moisture-sensitive (an epoxy material is not impervious, and Applicant’s specification discloses an epoxy as the interface layer, see para. [0010] of the instant specification, thus the epoxy interface layer of Jung is also moisture-sensitive) nonconductive material (epoxy resin with silica filler is not electrically conductive), the at least one interface layer (285) disposed at one of a layer within the package substrate or between the first surface of the IC (lower surface of IC 320) and the package substrate (100, interface layer 285 is between the package substrate 100 and the lower surface of IC 320), wherein:
the at least one interface layer (285) includes a first end (left end) and a second end (right end).
Jung does not explicitly disclose that the interface layer is sealed from exposure to air.
Wang discloses an interface layer (150, see Figure 1B) sealed from exposure to air (interface layer 150 is sealed from exposure to air as seen in Figure 1B, as 150 is sealed and entirely covered by an encapsulant 152, see also para. [0034]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Wang into the teachings of Jung in the manner above. All the elements of Jung and Wang were known in the prior art and one skilled in the art could have combined the sealed interface layer as disclosed by Wang into the teachings of Jung with no change in their respective functions, and the combination would have yielded the predictable result of providing a seal to the external environment to further protect components of the device to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Jung does not disclose a buffer material is disposed at the first end and the second end (of the interface layer, the buffer material being configured to seal the at least one interface layer from an environment surrounding the semiconductor package; and the buffer material comprises an electrically conductive ring.
However, Liu discloses wherein a buffer material (106) is disposed at the first end and the second end (left and right ends of interface layer (105, see Figure 1) (of the interface layer 105), the buffer material (106) being configured to seal the at least one interface layer (105, the buffer layer 106 seals the interface layer 105 from the external environment, see para. [0029]) from an environment surrounding the semiconductor package (see Figure 1 and para. [0029]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Liu into the teachings of Jung in the manner above because inclusion of a buffer material around the interface layer lower moisture absorption and increases thermal performance (Liu, para. [0029]).
Further, Pogge discloses in Figures 6D and 6F a buffer material (stiffener 41) disposed at left and right ends of an interface layer (underfill/organic material 71, analogous to Jung’s interface material 285) and comprising an electrically conductive ring (the stiffener/buffer material surround the semiconductor device, a gap therebetween filled with filling material, thus the buffer material is a ring shape surrounding the semiconductor device, see col. 3 lines 12-16, and the stiffener is also made of metal, which is electrically conductive, see col. 5 lines 37-40).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Pogge into the teachings of Jung and Liu above for the purpose of selecting a buffer material according to the package reliability requirements (Pogge col. 5 lines 37-40). Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Regarding claim 8, Jung discloses:
The semiconductor package of claim 1, further comprising an interposer layer (210) between the IC (320) and the package substrate (100, see Figure 1B).
Regarding claim 10, Jung discloses:
The semiconductor package of claim 8, further comprising a layer (340) comprised of the interface material (same composition as interface layer 285, see para. [0052]) disposed between the interposer layer (210) and the IC (320, see Figure 2).
Regarding claim 11, Jung discloses:
The semiconductor package of claim 1, wherein the interface material (285) comprises a material that changes in impedance according to changes in temperature (interface material comprises epoxy resin, see para. [0024], which changes in impedance according to changes in temperature).
Jung’s interface material is comprised of epoxy (see Jung, para. [0024]) and so is the instant application’s interface material (see instant specification, para. [0010]), thus the properties of the instant application’s interface material and Jung’s interface material are shared. Therefore, a change in impedance due to a change in temperature is also a property of Jung’s interface material despite this property not being explicitly recited by Jung.
Regarding claim 12, Jung discloses:
The semiconductor package of claim 1, wherein the interface material comprises a material that changes in impedance according to changes in humidity (interface material of Jung comprises epoxy resin, see para. [0024], which changes in impedance according to changes in humidity).
Jung’s interface material is comprised of an epoxy resin (see Jung, para. [0024]) and so is the instant application’s interface material (see instant specification, para. [0010]), thus the properties of the instant application’s interface material and Jung’s interface material are shared. Therefore, a change in impedance due to a change in humidity is also a property of Jung’s interface material despite this property not being explicitly recited by Jung.
Regarding claim 13, Jung discloses:
The semiconductor package of claim 1, wherein the interface material comprises a material that changes in impedance according to a chemical interaction of the interface material with at least one of a gas or a liquid (interface material of Jung comprises epoxy resin, see para. [0024], which changes in impedance according to a chemical interaction of the interface material with at least one of a gas or a liquid).
Jung’s interface material is comprised of an epoxy resin (see Jung, para. [0024]) and so is the instant application’s interface material (see instant specification, para. [0010]), thus the properties of the instant application’s interface material and Jung’s interface material are shared. Therefore, a change in impedance due to a chemical interaction of the interface material with at least one of a gas or a liquid is also a property of Jung’s interface material despite this property not being explicitly recited by Jung.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Jung and Wang as applied to claim 1 above, and further in view of Elian et al. (“Elian” US 2021/0325454).
Regarding claim 4, Jung discloses a method for testing the device (see para. [0046]-[0049], but does not explicitly disclose specifically:
The semiconductor package of claim 1, wherein the IC includes an impedance measuring circuit to measure impedance of the at least one interface layer.
Elian discloses the IC (502, 550, Figure 5) includes an impedance measuring circuit (502, see impedance measurement para. [0042]-[0045]) to measure impedance of the at least one interface layer (molding compound 552, Elian discloses the measuring circuit can measure impedance to detect delamination in molding materials and glues, and polymeric/epoxy materials are well-known non-electrically conductive molding materials and/or glues).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Elian into the teachings of Jung in the manner above for the purpose of implementing hardware to detect long-term degradation of package materials (see Elian, para. [0045]).
Regarding claim 5, Elian discloses:
The semiconductor package of claim 4, wherein the IC (502, 550) is configured to measure impedance (para. [0045]) at a plurality of points on the at least one interface layer (552, see para. [0042]-[0045] which discloses that the measurement circuitry is connected to internal contact, external contacts, and combinations thereof, i.e. 510, 512, 522, 520 in Figure 5, to measure impedance of the molding materials).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Elian into the teachings of Jung in the manner above with no change in their respective functions, and the combination would have yielded the predictable result of measuring impedance to detect the state of health of the package materials at multiple points within the package to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 6, Elian discloses:
The semiconductor package of claim 5, wherein the plurality of points corresponds to conductive bumps on the first surface of the IC (510, 512, 522, 520, these interconnects are on the lower surface of the IC in Figure 5, see para. [0042]-[0045], Elain’s measurement circuitry is configured to measure impedance at a plurality of connections to the IC).
Regarding claim 7, Elian discloses:
The semiconductor package of claim 5, wherein the plurality of points corresponds to bumps of a chip connector (510, 512, 522, 520, these interconnects are connections to the chip 550, Elain’s measurement circuitry is configured to measure impedance at a plurality of connections to the IC).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jung and Wang as applied to claim 8 above, and further in view of Chang et al. (“Chang” US 2021/0202336).
Regarding claim 9, Jung discloses:
The semiconductor package of claim 8, wherein the interposer layer (210) comprises silicon (see para. [0027]).
Jung does not disclose that the interposer layer includes a layer comprised of the interface material.
Chang discloses an interposer layer (1and 37, see Figure 2) that includes a layer comprised of the interface material (37, see para. [0043], the interface material layer 37 comprises a resin material with filler which is the interface material of Jung).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Chang into the teachings of Jung in the manner above for the purpose of providing additional rigidity to the interposer (see Chang, para. [0051]). Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Response to Arguments
Applicant’s amendments to claim 14, filed December 26 2025, with respect to the 112(b) rejection of claim 14 have been fully considered and overcome the 112(b) rejection. The 112(b) rejection of claim 14 has been withdrawn.
Applicant’s arguments with respect to claim 14 have been fully considered but are not persuasive. Applicant argues that Jung does not disclose interface material "in contact with a first surface of the semiconductor die and between the first surface of the semiconductor die and the package substrate." Jung's insulating filler 285 is separated from the IC 320 by interposer 200. However, in the Non-Final Office Action and above, the Examiner mapped the claimed interface material to Jung’s second insulating filler 340, not the insulating filler 285. See the Non-Final Office Action, first paragraph of page 4, and above. The second insulating filler 340 of Jung is in contact with a first surface (lower surface) of the semiconductor die 310 and is between the first surface of the semiconductor die 310 and the package substrate 100, see Figure 2 of Jung.
Applicant’s arguments with respect to the remaining claims, regarding the limitation “the buffer material comprises an electrically conductive ring” of claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899